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  1. CODE
  2. ______________________
  3. LIBRARY ieee;
  4. USE ieee.std_logic_1164.ALL;
  5. use ieee.numeric_std.ALL;
  6.  
  7. entity DataMEMORY is
  8. Port ( MAR : in STD_LOGIC_vector (15 downto 0);
  9. MDR : in STD_LOGIC_vector (15 downto 0);
  10. WE : in std_logic;
  11.  
  12. Readdata : out STD_LOGIC_vector (15 downto 0));
  13. end DataMEMORY;
  14. architecture Behavioral of DataMEMORY is
  15. type dataMemory is array (0 to 65535) of std_logic_vector(15 downto 0);
  16. signal DM : dataMemory:=((others=> (others=>'0')));
  17. begin
  18.  
  19. process (MAR)
  20. begin
  21. if (WE='1') then
  22. DM(to_integer(unsigned(MAR)))<=MDR;
  23.  
  24. end if ;
  25.  
  26.  
  27. end process;
  28.  
  29. Readdata<=DM(to_integer(unsigned(MAR)));
  30. end Behavioral;
  31.  
  32.  
  33.  
  34.  
  35. TESTBENCH
  36. ____________________________________
  37. LIBRARY ieee;
  38. USE ieee.std_logic_1164.ALL;
  39. use ieee.numeric_std.ALL;
  40. -- Uncomment the following library declaration if using
  41. -- arithmetic functions with Signed or Unsigned values
  42. --USE ieee.numeric_std.ALL;
  43.  
  44. ENTITY DataMEMORYTB IS
  45. END DataMEMORYTB;
  46.  
  47. ARCHITECTURE behavior OF DataMEMORYTB IS
  48.  
  49. -- Component Declaration for the Unit Under Test (UUT)
  50.  
  51. COMPONENT DataMEMORY
  52. PORT(
  53. MAR : IN std_logic_vector(15 downto 0);
  54. MDR : IN std_logic_vector(15 downto 0);
  55. WE : IN std_logic ;
  56.  
  57. Readdata : OUT std_logic_vector(15 downto 0)
  58. );
  59. END COMPONENT;
  60.  
  61.  
  62. --Inputs
  63. signal MAR : std_logic_vector(15 downto 0) := (others => '0');
  64. signal MDR : std_logic_vector(15 downto 0) := (others => '0');
  65. signal WE : std_logic := '0';
  66.  
  67. --Outputs
  68. signal Readdata : std_logic_vector(15 downto 0);
  69. -- No clocks detected in port list. Replace <clock> below with
  70. -- appropriate port name
  71.  
  72.  
  73. BEGIN
  74.  
  75. -- Instantiate the Unit Under Test (UUT)
  76. uut: DataMEMORY PORT MAP (
  77. MAR => MAR,
  78. MDR => MDR,
  79. WE => WE,
  80. Readdata => Readdata
  81. );
  82.  
  83.  
  84.  
  85.  
  86. -- Stimulus process
  87. stim_proc: process
  88. begin
  89.  
  90.  
  91. -- insert stimulus here
  92. WE<='1';
  93. MAR<="1000000000000000";
  94. MDR<="1010101010101010";
  95. wait for 100 ns;
  96. WE<='0';
  97. MAR<="1000000000000000";
  98. wait for 100 ns;
  99. MAR<="1100000000000000";
  100. WE<='1';
  101. MDR<="1000000000000000";
  102. wait for 100 ns;
  103.  
  104. MAR<="0000000000000000";
  105. WE<='0';
  106. wait for 100 ns;
  107.  
  108. MAR<="0000000000000010";
  109. WE<='0';
  110. wait for 100 ns;
  111.  
  112. wait;
  113. end process;
  114.  
  115. END;
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