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clk_summary.microSD_after my changes

armoon
Mar 3rd, 2020
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  1. enable prepare protect duty
  2. clock count count count rate accuracy phase cycle
  3. ---------------------------------------------------------------------------------------------
  4. xtal 11 11 0 24000000 0 0 50000
  5. ffd1b000.pwm#mux1 0 0 0 24000000 0 0 50000
  6. ffd1b000.pwm#mux0 1 1 0 24000000 0 0 50000
  7. ff802000.pwm#mux1 1 1 0 24000000 0 0 50000
  8. ff802000.pwm#mux0 0 0 0 24000000 0 0 50000
  9. cts_oscin 0 0 0 24000000 0 0 50000
  10. g12a_ao_cec_pre 0 0 0 24000000 0 0 50000
  11. g12a_ao_cec_div 0 0 0 32742 0 0 50000
  12. g12a_ao_cec_sel 0 0 0 32742 0 0 50000
  13. g12a_ao_cec 0 0 0 32742 0 0 50000
  14. g12a_ao_32k_by_oscin_pre 0 0 0 24000000 0 0 50000
  15. g12a_ao_32k_by_oscin_sel 0 0 0 24000000 0 0 50000
  16. g12a_ao_32k_by_oscin 0 0 0 24000000 0 0 50000
  17. g12a_ao_cts_rtc_oscin 0 0 0 24000000 0 0 50000
  18. g12a_ao_32k_by_oscin_div 0 0 0 32742 0 0 50000
  19. g12a_ao_saradc_mux 0 0 0 24000000 0 0 50000
  20. g12a_ao_saradc_div 0 0 0 150000 0 0 50000
  21. g12a_ao_saradc_gate 0 0 0 150000 0 0 50000
  22. cpub_clk_dyn0_sel 0 0 0 24000000 0 0 50000
  23. cpub_clk_dyn0 0 0 0 24000000 0 0 50000
  24. cpub_clk_dyn0_div 0 0 0 24000000 0 0 50000
  25. sys1_pll_dco 1 1 0 3792000000 0 0 50000
  26. sys1_pll 0 0 0 1896000000 0 0 50000
  27. cpu_clk 0 0 0 1896000000 0 0 50000
  28. cpu_clk_trace_div 0 0 0 59250000 0 0 50000
  29. cpu_clk_trace 0 0 0 59250000 0 0 50000
  30. sys1_pll_div16_en 0 0 0 1896000000 0 0 50000
  31. sys1_pll_div16 0 0 0 118500000 0 0 50000
  32. ts_div 1 1 0 960000 0 0 50000
  33. ts 2 2 0 960000 0 0 50000
  34. pcie_pll_dco 1 1 0 0 0 0 50000
  35. pcie_pll_dco_div2 1 1 0 0 0 0 50000
  36. pcie_pll_od 1 1 0 0 0 0 50000
  37. pcie_pll_pll 1 1 0 0 0 0 50000
  38. cpu_clk_dyn0_sel 0 0 0 24000000 0 0 50000
  39. cpu_clk_dyn0 0 0 0 24000000 0 0 50000
  40. cpu_clk_dyn 0 0 0 24000000 0 0 50000
  41. cpu_clk_dyn0_div 0 0 0 24000000 0 0 50000
  42. mali_1_sel 0 0 0 24000000 0 0 50000
  43. mali_1_div 0 0 0 24000000 0 0 50000
  44. mali_1 0 0 0 24000000 0 0 50000
  45. mali_0_sel 0 0 0 24000000 0 0 50000
  46. mali_0_div 0 0 0 24000000 0 0 50000
  47. mali_0 0 0 0 24000000 0 0 50000
  48. mali 0 0 0 24000000 0 0 50000
  49. hdmi_sel 1 1 0 24000000 0 0 50000
  50. hdmi_div 1 1 0 24000000 0 0 50000
  51. hdmi 2 2 0 24000000 0 0 50000
  52. hdmi_pll_dco 0 0 0 5191999878 0 0 50000
  53. hdmi_pll_od 0 0 0 1297999970 0 0 50000
  54. hdmi_pll_od2 0 0 0 648999985 0 0 50000
  55. hdmi_pll 0 0 0 648999985 0 0 50000
  56. vid_pll_div 0 0 0 129799997 0 0 50000
  57. vid_pll_sel 0 0 0 129799997 0 0 50000
  58. vid_pll 0 0 0 129799997 0 0 50000
  59. vclk2_sel 0 0 0 129799997 0 0 50000
  60. vclk2_input 0 0 0 129799997 0 0 50000
  61. vclk2_div 0 0 0 64899999 0 0 50000
  62. vclk2 0 0 0 64899999 0 0 50000
  63. vclk2_div1 0 0 0 64899999 0 0 50000
  64. vclk2_div12_en 0 0 0 64899999 0 0 50000
  65. vclk2_div12 0 0 0 5408333 0 0 50000
  66. vclk2_div6_en 0 0 0 64899999 0 0 50000
  67. vclk2_div6 0 0 0 10816666 0 0 50000
  68. vclk2_div4_en 0 0 0 64899999 0 0 50000
  69. vclk2_div4 0 0 0 16224999 0 0 50000
  70. vclk2_div2_en 0 0 0 64899999 0 0 50000
  71. vclk2_div2 0 0 0 32449999 0 0 50000
  72. vclk_sel 0 0 0 129799997 0 0 50000
  73. vclk_input 0 0 0 129799997 0 0 50000
  74. vclk_div 0 0 0 64899999 0 0 50000
  75. vclk 0 0 0 64899999 0 0 50000
  76. vclk_div1 0 0 0 64899999 0 0 50000
  77. hdmi_tx_sel 0 0 0 64899999 0 0 50000
  78. hdmi_tx 0 0 0 64899999 0 0 50000
  79. cts_vdac_sel 0 0 0 64899999 0 0 50000
  80. cts_vdac 0 0 0 64899999 0 0 50000
  81. cts_encp_sel 0 0 0 64899999 0 0 50000
  82. cts_encp 0 0 0 64899999 0 0 50000
  83. cts_enci_sel 0 0 0 64899999 0 0 50000
  84. cts_enci 0 0 0 64899999 0 0 50000
  85. vclk_div12_en 0 0 0 64899999 0 0 50000
  86. vclk_div12 0 0 0 5408333 0 0 50000
  87. vclk_div6_en 0 0 0 64899999 0 0 50000
  88. vclk_div6 0 0 0 10816666 0 0 50000
  89. vclk_div4_en 0 0 0 64899999 0 0 50000
  90. vclk_div4 0 0 0 16224999 0 0 50000
  91. vclk_div2_en 0 0 0 64899999 0 0 50000
  92. vclk_div2 0 0 0 32449999 0 0 50000
  93. hifi_pll_dco 0 0 0 0 0 0 50000
  94. hifi_pll 0 0 0 0 0 0 50000
  95. gp0_pll_dco 0 0 0 0 0 0 50000
  96. gp0_pll 0 0 0 0 0 0 50000
  97. sys_pll_dco 1 1 0 4800000000 0 0 50000
  98. sys_pll 0 0 0 1200000000 0 0 50000
  99. sys_pll_div16_en 0 0 0 1200000000 0 0 50000
  100. sys_pll_div16 0 0 0 75000000 0 0 50000
  101. fixed_pll_dco 1 1 0 3999999939 0 0 50000
  102. mpll_50m_div 0 0 0 49999999 0 0 50000
  103. mpll_50m 0 0 0 49999999 0 0 50000
  104. ff64c000.mdio-multiplexer#mux 0 0 0 49999999 0 0 50000
  105. ff64c000.mdio-multiplexer#pll 0 0 0 499999990 0 0 50000
  106. fixed_pll 3 3 0 1999999970 0 0 50000
  107. fclk_div7_div 0 0 0 285714281 0 0 50000
  108. fclk_div7 0 0 0 285714281 0 0 50000
  109. fclk_div5_div 0 0 0 399999994 0 0 50000
  110. fclk_div5 0 0 0 399999994 0 0 50000
  111. fclk_div4_div 1 1 0 499999992 0 0 50000
  112. fclk_div4 1 1 0 499999992 0 0 50000
  113. vapb_1_sel 0 0 0 499999992 0 0 50000
  114. vapb_1_div 0 0 0 499999992 0 0 50000
  115. vapb_1 0 0 0 499999992 0 0 50000
  116. vapb_0_sel 1 1 0 499999992 0 0 50000
  117. vapb_0_div 1 1 0 249999996 0 0 50000
  118. vapb_0 1 1 0 249999996 0 0 50000
  119. vapb_sel 1 1 0 249999996 0 0 50000
  120. vapb 1 1 0 249999996 0 0 50000
  121. fclk_div3_div 1 1 0 666666656 0 0 50000
  122. fclk_div3 3 3 0 666666656 0 0 50000
  123. cpu_clk_dyn1_sel 0 0 0 666666656 0 0 50000
  124. cpu_clk_dyn1 0 0 0 666666656 0 0 50000
  125. cpu_clk_dyn1_div 0 0 0 666666656 0 0 50000
  126. vpu_1_sel 0 0 0 666666656 0 0 50000
  127. vpu_1_div 0 0 0 666666656 0 0 50000
  128. vpu_1 0 0 0 666666656 0 0 50000
  129. vpu_0_sel 1 1 0 666666656 0 0 50000
  130. vpu_0_div 1 1 0 666666656 0 0 50000
  131. vpu_0 1 1 0 666666656 0 0 50000
  132. vpu 1 1 0 666666656 0 0 50000
  133. mpeg_clk_sel 1 1 0 666666656 0 0 50000
  134. mpeg_clk_div 1 1 0 222222219 0 0 50000
  135. clk81 11 11 0 222222219 0 0 50000
  136. g12a_ao_clk81 0 0 0 222222219 0 0 50000
  137. g12a_ao_m4_hclk 0 0 0 222222219 0 0 50000
  138. g12a_ao_m4_fclk 0 0 0 222222219 0 0 50000
  139. g12a_ao_rti 0 0 0 222222219 0 0 50000
  140. g12a_ao_ahb_sram 0 0 0 222222219 0 0 50000
  141. g12a_ao_m3 0 0 0 222222219 0 0 50000
  142. g12a_ao_mailbox 0 0 0 222222219 0 0 50000
  143. g12a_ao_saradc 0 0 0 222222219 0 0 50000
  144. g12a_ao_ir_out 0 0 0 222222219 0 0 50000
  145. g12a_ao_uart2 0 0 0 222222219 0 0 50000
  146. g12a_ao_prod_i2c 0 0 0 222222219 0 0 50000
  147. g12a_ao_uart 1 1 0 222222219 0 0 50000
  148. g12a_ao_i2c_s0 0 0 0 222222219 0 0 50000
  149. g12a_ao_i2c_m0 0 0 0 222222219 0 0 50000
  150. g12a_ao_ir_in 0 0 0 222222219 0 0 50000
  151. g12a_ao_ahb 0 0 0 222222219 0 0 50000
  152. g12a_sec_ahb_apb3 0 0 0 222222219 0 0 50000
  153. g12a_reset_sec 0 0 0 222222219 0 0 50000
  154. g12a_rom_boot 0 0 0 222222219 0 0 50000
  155. g12a_efuse 1 1 0 222222219 0 0 50000
  156. g12a_dma 0 0 0 222222219 0 0 50000
  157. g12a_vclk2_other1 0 0 0 222222219 0 0 50000
  158. g12a_vclk2_vencl 0 0 0 222222219 0 0 50000
  159. g12a_vclk2_venclmmc 0 0 0 222222219 0 0 50000
  160. g12a_vclk2_encl 0 0 0 222222219 0 0 50000
  161. g12a_vclk2_enct 0 0 0 222222219 0 0 50000
  162. g12a_rng1 0 0 0 222222219 0 0 50000
  163. g12a_enc480p 0 0 0 222222219 0 0 50000
  164. g12a_iec958_gate 0 0 0 222222219 0 0 50000
  165. g12a_aoclk_gate 0 0 0 222222219 0 0 50000
  166. g12a_dac_clk 0 0 0 222222219 0 0 50000
  167. g12a_vclk2_encp 0 0 0 222222219 0 0 50000
  168. g12a_vclk2_enci 0 0 0 222222219 0 0 50000
  169. g12a_vclk2_other 0 0 0 222222219 0 0 50000
  170. g12a_vclk2_venct1 0 0 0 222222219 0 0 50000
  171. g12a_vclk2_venct0 0 0 0 222222219 0 0 50000
  172. g12a_vclk2_vencp1 0 0 0 222222219 0 0 50000
  173. g12a_vclk2_vencp0 0 0 0 222222219 0 0 50000
  174. g12a_vclk2_venci1 0 0 0 222222219 0 0 50000
  175. g12a_vclk2_venci0 0 0 0 222222219 0 0 50000
  176. g12a_gic 0 0 0 222222219 0 0 50000
  177. g12a_vpu_intr 1 1 0 222222219 0 0 50000
  178. g12a_uart2 0 0 0 222222219 0 0 50000
  179. g12a_mmc_pclk 0 0 0 222222219 0 0 50000
  180. g12a_usb1_to_ddr 0 0 0 222222219 0 0 50000
  181. g12a_bt656 0 0 0 222222219 0 0 50000
  182. g12a_htx_pclk 1 1 0 222222219 0 0 50000
  183. g12a_htx_hdcp22 0 0 0 222222219 0 0 50000
  184. g12a_ahb_ctrl_bus 0 0 0 222222219 0 0 50000
  185. g12a_ahb_data_bus 0 0 0 222222219 0 0 50000
  186. g12a_ahb_arb0 0 0 0 222222219 0 0 50000
  187. g12a_pcie_phy 0 0 0 222222219 0 0 50000
  188. g12a_usb_general 1 1 0 222222219 0 0 50000
  189. g12a_parser 0 0 0 222222219 0 0 50000
  190. g12a_pcie_comb 0 0 0 222222219 0 0 50000
  191. g12a_reset 0 0 0 222222219 0 0 50000
  192. g12a_g2d 0 0 0 222222219 0 0 50000
  193. g12a_uart1 0 0 0 222222219 0 0 50000
  194. g12a_adc 0 0 0 222222219 0 0 50000
  195. g12a_audio_ififo 0 0 0 222222219 0 0 50000
  196. g12a_demux 0 0 0 222222219 0 0 50000
  197. g12a_eth_core 1 1 0 222222219 0 0 50000
  198. g12a_audio 2 2 0 222222219 0 0 50000
  199. aud_top 1 1 0 222222219 0 0 50000
  200. aud_ddr_arb 1 1 0 222222219 0 0 50000
  201. aud_pdm 0 0 0 222222219 0 0 50000
  202. aud_tdmin_a 0 0 0 222222219 0 0 50000
  203. aud_tdmin_b 0 0 0 222222219 0 0 50000
  204. aud_tdmin_c 0 0 0 222222219 0 0 50000
  205. aud_tdmin_lb 0 0 0 222222219 0 0 50000
  206. aud_tdmout_a 0 0 0 222222219 0 0 50000
  207. aud_tdmout_b 0 0 0 222222219 0 0 50000
  208. aud_tdmout_c 0 0 0 222222219 0 0 50000
  209. aud_frddr_a 0 0 0 222222219 0 0 50000
  210. aud_frddr_b 0 0 0 222222219 0 0 50000
  211. aud_frddr_c 0 0 0 222222219 0 0 50000
  212. aud_toddr_a 0 0 0 222222219 0 0 50000
  213. aud_toddr_b 0 0 0 222222219 0 0 50000
  214. aud_toddr_c 0 0 0 222222219 0 0 50000
  215. aud_loopback 0 0 0 222222219 0 0 50000
  216. aud_spdifin 0 0 0 222222219 0 0 50000
  217. aud_spdifout 0 0 0 222222219 0 0 50000
  218. aud_resample 0 0 0 222222219 0 0 50000
  219. aud_power_detect 0 0 0 222222219 0 0 50000
  220. aud_spdifout_b 0 0 0 222222219 0 0 50000
  221. g12a_audio_codec 0 0 0 222222219 0 0 50000
  222. g12a_emmc_c 1 1 0 222222219 0 0 50000
  223. g12a_emmc_b 1 1 0 222222219 0 0 50000
  224. g12a_emmc_a 0 0 0 222222219 0 0 50000
  225. g12a_assist_misc 0 0 0 222222219 0 0 50000
  226. g12a_mipi_dsi_phy 0 0 0 222222219 0 0 50000
  227. g12a_hiu_reg 0 0 0 222222219 0 0 50000
  228. g12a_spicc_1 0 0 0 222222219 0 0 50000
  229. g12a_uart0 0 0 0 222222219 0 0 50000
  230. g12a_rng0 0 0 0 222222219 0 0 50000
  231. g12a_sd 0 0 0 222222219 0 0 50000
  232. g12a_sana 0 0 0 222222219 0 0 50000
  233. g12a_i2c 0 0 0 222222219 0 0 50000
  234. g12a_spicc_0 0 0 0 222222219 0 0 50000
  235. g12a_periphs 0 0 0 222222219 0 0 50000
  236. g12a_pl301 0 0 0 222222219 0 0 50000
  237. g12a_isa 0 0 0 222222219 0 0 50000
  238. g12a_eth_phy 1 1 0 222222219 0 0 50000
  239. g12a_mipi_dsi_host 0 0 0 222222219 0 0 50000
  240. g12a_audio_locker 0 0 0 222222219 0 0 50000
  241. g12a_dos 0 0 0 222222219 0 0 50000
  242. g12a_ddr 0 0 0 222222219 0 0 50000
  243. fclk_div2_div 1 1 0 999999985 0 0 50000
  244. fclk_div2 3 3 0 999999985 0 0 50000
  245. ff3f0000.ethernet#m250_sel 1 1 0 999999985 0 0 50000
  246. ff3f0000.ethernet#m250_div 1 1 0 249999997 0 0 50000
  247. ff3f0000.ethernet#fixed_div2 1 1 0 124999998 0 0 50000
  248. ff3f0000.ethernet#rgmii_tx_en 1 1 0 124999998 0 0 50000
  249. ffe05000.sd#mux 1 1 0 999999985 0 0 50000
  250. ffe05000.sd#div 1 1 0 50000000 0 0 50000
  251. cpub_clk_dyn1_sel 1 1 0 999999985 0 0 50000
  252. cpub_clk_dyn1 1 1 0 999999985 0 0 50000
  253. cpub_clk_dyn 1 1 0 999999985 0 0 50000
  254. cpub_clk 1 1 0 999999985 0 0 50000
  255. cpub_clk_div8 0 0 0 124999998 0 0 50000
  256. cpub_clk_div7 0 0 0 142857140 0 0 50000
  257. cpub_clk_div6 0 0 0 166666664 0 0 50000
  258. cpub_clk_trace_sel 0 0 0 166666664 0 0 50000
  259. cpub_clk_trace 0 0 0 166666664 0 0 50000
  260. cpub_clk_div5 0 0 0 199999997 0 0 50000
  261. cpub_clk_apb_sel 0 0 0 199999997 0 0 50000
  262. cpub_clk_apb 0 0 0 199999997 0 0 50000
  263. cpub_clk_div4 0 0 0 249999996 0 0 50000
  264. cpub_clk_div3 0 0 0 333333328 0 0 50000
  265. cpub_clk_atb_sel 0 0 0 333333328 0 0 50000
  266. cpub_clk_atb 0 0 0 333333328 0 0 50000
  267. cpub_clk_div2 0 0 0 499999992 0 0 50000
  268. cpub_clk_axi_sel 0 0 0 499999992 0 0 50000
  269. cpub_clk_axi 0 0 0 499999992 0 0 50000
  270. cpub_clk_div16_en 0 0 0 999999985 0 0 50000
  271. cpub_clk_div16 0 0 0 62499999 0 0 50000
  272. cpub_clk_dyn1_div 0 0 0 999999985 0 0 50000
  273. mpll_prediv 0 0 0 1999999969 0 0 50000
  274. mpll0_div 0 0 0 270948747 0 0 50000
  275. mpll0 0 0 0 270948747 0 0 50000
  276. aud_spdifout_b_clk_sel 0 0 0 270948747 0 0 50000
  277. aud_spdifout_b_clk_div 0 0 0 270948747 0 0 50000
  278. aud_spdifout_b_clk 0 0 0 270948747 0 0 50000
  279. aud_pdm_sysclk_sel 0 0 0 270948747 0 0 50000
  280. aud_pdm_sysclk_div 0 0 0 270948747 0 0 50000
  281. aud_pdm_sysclk 0 0 0 270948747 0 0 50000
  282. aud_pdm_dclk_sel 0 0 0 270948747 0 0 50000
  283. aud_pdm_dclk_div 0 0 0 270948747 0 0 50000
  284. aud_pdm_dclk 0 0 0 270948747 0 0 50000
  285. aud_spdifin_clk_sel 0 0 0 270948747 0 0 50000
  286. aud_spdifin_clk_div 0 0 0 270948747 0 0 50000
  287. aud_spdifin_clk 0 0 0 270948747 0 0 50000
  288. aud_spdifout_clk_sel 0 0 0 270948747 0 0 50000
  289. aud_spdifout_clk_div 0 0 0 270948747 0 0 50000
  290. aud_spdifout_clk 0 0 0 270948747 0 0 50000
  291. aud_mst_f_mclk_sel 0 0 0 270948747 0 0 50000
  292. aud_mst_f_mclk_div 0 0 0 270948747 0 0 50000
  293. aud_mst_f_mclk 0 0 0 270948747 0 0 50000
  294. aud_mst_f_sclk_pre_en 0 0 0 270948747 0 0 50000
  295. aud_mst_f_sclk_div 0 0 0 264599 0 0 50000
  296. aud_mst_f_sclk_post_en 0 0 0 264599 0 0 50000
  297. aud_mst_f_lrclk_div 0 0 0 259 0 0 97
  298. aud_mst_f_lrclk 0 0 0 259 0 0 97
  299. aud_mst_f_sclk 0 0 0 264599 0 0 50000
  300. aud_mst_e_mclk_sel 0 0 0 270948747 0 0 50000
  301. aud_mst_e_mclk_div 0 0 0 270948747 0 0 50000
  302. aud_mst_e_mclk 0 0 0 270948747 0 0 50000
  303. aud_mst_e_sclk_pre_en 0 0 0 270948747 0 0 50000
  304. aud_mst_e_sclk_div 0 0 0 264599 0 0 50000
  305. aud_mst_e_sclk_post_en 0 0 0 264599 0 0 50000
  306. aud_mst_e_lrclk_div 0 0 0 259 0 0 97
  307. aud_mst_e_lrclk 0 0 0 259 0 0 97
  308. aud_mst_e_sclk 0 0 0 264599 0 0 50000
  309. aud_mst_d_mclk_sel 0 0 0 270948747 0 0 50000
  310. aud_mst_d_mclk_div 0 0 0 270948747 0 0 50000
  311. aud_mst_d_mclk 0 0 0 270948747 0 0 50000
  312. aud_mst_d_sclk_pre_en 0 0 0 270948747 0 0 50000
  313. aud_mst_d_sclk_div 0 0 0 264599 0 0 50000
  314. aud_mst_d_sclk_post_en 0 0 0 264599 0 0 50000
  315. aud_mst_d_lrclk_div 0 0 0 259 0 0 97
  316. aud_mst_d_lrclk 0 0 0 259 0 0 97
  317. aud_mst_d_sclk 0 0 0 264599 0 0 50000
  318. aud_mst_c_mclk_sel 0 0 0 270948747 0 0 50000
  319. aud_mst_c_mclk_div 0 0 0 270948747 0 0 50000
  320. aud_mst_c_mclk 0 0 0 270948747 0 0 50000
  321. aud_mst_c_sclk_pre_en 0 0 0 270948747 0 0 50000
  322. aud_mst_c_sclk_div 0 0 0 264599 0 0 50000
  323. aud_mst_c_sclk_post_en 0 0 0 264599 0 0 50000
  324. aud_mst_c_lrclk_div 0 0 0 259 0 0 97
  325. aud_mst_c_lrclk 0 0 0 259 0 0 97
  326. aud_mst_c_sclk 0 0 0 264599 0 0 50000
  327. aud_mst_b_mclk_sel 0 0 0 270948747 0 0 50000
  328. aud_mst_b_mclk_div 0 0 0 270948747 0 0 50000
  329. aud_mst_b_mclk 0 0 0 270948747 0 0 50000
  330. aud_mst_b_sclk_pre_en 0 0 0 270948747 0 0 50000
  331. aud_mst_b_sclk_div 0 0 0 264599 0 0 50000
  332. aud_mst_b_sclk_post_en 0 0 0 264599 0 0 50000
  333. aud_mst_b_lrclk_div 0 0 0 259 0 0 97
  334. aud_mst_b_lrclk 0 0 0 259 0 0 97
  335. aud_mst_b_sclk 0 0 0 264599 0 0 50000
  336. aud_mst_a_mclk_sel 0 0 0 270948747 0 0 50000
  337. aud_mst_a_mclk_div 0 0 0 270948747 0 0 50000
  338. aud_mst_a_mclk 0 0 0 270948747 0 0 50000
  339. aud_mclk_pad_1 0 0 0 270948747 0 0 50000
  340. aud_mclk_pad_0 0 0 0 270948747 0 0 50000
  341. aud_mst_a_sclk_pre_en 0 0 0 270948747 0 0 50000
  342. aud_mst_a_sclk_div 0 0 0 264599 0 0 50000
  343. aud_mst_a_sclk_post_en 0 0 0 264599 0 0 50000
  344. aud_mst_a_lrclk_div 0 0 0 259 0 0 97
  345. aud_mst_a_lrclk 0 0 0 259 0 0 97
  346. aud_lrclk_pad_2 0 0 0 259 0 0 97
  347. aud_lrclk_pad_1 0 0 0 259 0 0 97
  348. aud_lrclk_pad_0 0 0 0 259 0 0 97
  349. aud_tdmout_c_lrclk 0 0 0 259 0 0 97
  350. aud_tdmout_b_lrclk 0 0 0 259 0 0 97
  351. aud_tdmout_a_lrclk 0 0 0 259 0 0 97
  352. aud_tdmin_lb_lrclk 0 0 0 259 0 0 97
  353. aud_tdmin_c_lrclk 0 0 0 259 0 0 97
  354. aud_tdmin_b_lrclk 0 0 0 259 0 0 97
  355. aud_tdmin_a_lrclk 0 0 0 259 0 0 97
  356. aud_mst_a_sclk 0 0 0 264599 0 0 50000
  357. aud_sclk_pad_2 0 0 0 264599 0 0 50000
  358. aud_sclk_pad_1 0 0 0 264599 0 0 50000
  359. aud_sclk_pad_0 0 0 0 264599 0 0 50000
  360. aud_tdmout_c_sclk_sel 0 0 0 264599 0 0 50000
  361. aud_tdmout_c_sclk_pre_en 0 0 0 264599 0 0 50000
  362. aud_tdmout_c_sclk_post_en 0 0 0 264599 0 0 50000
  363. aud_tdmout_c_sclk 0 0 0 264599 0 0 50000
  364. aud_tdmout_b_sclk_sel 0 0 0 264599 0 0 50000
  365. aud_tdmout_b_sclk_pre_en 0 0 0 264599 0 0 50000
  366. aud_tdmout_b_sclk_post_en 0 0 0 264599 0 0 50000
  367. aud_tdmout_b_sclk 0 0 0 264599 0 0 50000
  368. aud_tdmout_a_sclk_sel 0 0 0 264599 0 0 50000
  369. aud_tdmout_a_sclk_pre_en 0 0 0 264599 0 0 50000
  370. aud_tdmout_a_sclk_post_en 0 0 0 264599 0 0 50000
  371. aud_tdmout_a_sclk 0 0 0 264599 0 0 50000
  372. aud_tdmin_lb_sclk_sel 0 0 0 264599 0 0 50000
  373. aud_tdmin_lb_sclk_pre_en 0 0 0 264599 0 0 50000
  374. aud_tdmin_lb_sclk_post_en 0 0 0 264599 0 0 50000
  375. aud_tdmin_lb_sclk 0 0 0 264599 0 0 50000
  376. aud_tdmin_c_sclk_sel 0 0 0 264599 0 0 50000
  377. aud_tdmin_c_sclk_pre_en 0 0 0 264599 0 0 50000
  378. aud_tdmin_c_sclk_post_en 0 0 0 264599 0 0 50000
  379. aud_tdmin_c_sclk 0 0 0 264599 0 0 50000
  380. aud_tdmin_b_sclk_sel 0 0 0 264599 0 0 50000
  381. aud_tdmin_b_sclk_pre_en 0 0 0 264599 0 0 50000
  382. aud_tdmin_b_sclk_post_en 0 0 0 264599 0 0 50000
  383. aud_tdmin_b_sclk 0 0 0 264599 0 0 50000
  384. aud_tdmin_a_sclk_sel 0 0 0 264599 0 0 50000
  385. aud_tdmin_a_sclk_pre_en 0 0 0 264599 0 0 50000
  386. aud_tdmin_a_sclk_post_en 0 0 0 264599 0 0 50000
  387. aud_tdmin_a_sclk 0 0 0 264599 0 0 50000
  388. mpll1_div 0 0 0 393212849 0 0 50000
  389. mpll1 0 0 0 393212849 0 0 50000
  390. mpll2_div 0 0 0 294909637 0 0 50000
  391. mpll2 0 0 0 294909637 0 0 50000
  392. mpll3_div 0 0 0 0 0 0 50000
  393. mpll3 0 0 0 0 0 0 50000
  394. fclk_div2p5_div 0 0 0 799999987 0 0 50000
  395. fclk_div2p5 0 0 0 799999987 0 0 50000
  396. vdec_hevcf_sel 0 0 0 799999987 0 0 50000
  397. vdec_hevcf_div 0 0 0 799999987 0 0 50000
  398. vdec_hevcf 0 0 0 799999987 0 0 50000
  399. vdec_hevc_sel 0 0 0 799999987 0 0 50000
  400. vdec_hevc_div 0 0 0 799999987 0 0 50000
  401. vdec_hevc 0 0 0 799999987 0 0 50000
  402. vdec_1_sel 0 0 0 799999987 0 0 50000
  403. vdec_1_div 0 0 0 799999987 0 0 50000
  404. vdec_1 0 0 0 799999987 0 0 50000
  405. sd_emmc_c_clk0_sel 1 1 0 24000000 0 0 50000
  406. sd_emmc_c_clk0_div 1 1 0 24000000 0 0 50000
  407. sd_emmc_c_clk0 1 1 0 24000000 0 0 50000
  408. ffe07000.mmc#mux 1 1 0 24000000 0 0 50000
  409. ffe07000.mmc#div 1 1 0 400000 0 0 50000
  410. sd_emmc_b_clk0_sel 0 0 0 24000000 0 0 50000
  411. sd_emmc_b_clk0_div 0 0 0 24000000 0 0 50000
  412. sd_emmc_b_clk0 0 0 0 24000000 0 0 50000
  413. sd_emmc_a_clk0_sel 0 0 0 24000000 0 0 50000
  414. sd_emmc_a_clk0_div 0 0 0 24000000 0 0 50000
  415. sd_emmc_a_clk0 0 0 0 24000000 0 0 50000
  416. cpu_clk_axi_div 0 0 0 0 0 0 50000
  417. cpu_clk_axi 0 0 0 0 0 0 50000
  418. cpu_clk_atb_div 0 0 0 0 0 0 50000
  419. cpu_clk_atb 0 0 0 0 0 0 50000
  420. cpu_clk_apb_div 0 0 0 0 0 0 50000
  421. cpu_clk_apb 0 0 0 0 0 0 50000
  422. cpu_clk_div16_en 0 0 0 0 0 0 50000
  423. cpu_clk_div16 0 0 0 0 0 0 50000
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