$ rm -rf build/digilent_nexys_video; litex-boards/litex_boards/targets/digilent_nexys_video.py --build --cpu-type rocket --cpu-variant linux --cpu-num-cores 4 --cpu-mem-width 2 --sys-clk-freq 50e6 --with-ethernet --with-sdcard --with-sata --sata-gen 1 --csr-csv ./csr.csv --csr-json ./csr.json

...
INFO:SoCBusHandler:main_ram Region added at Origin: 0x80000000, Size: 0x20000000, Mode: RWX, Cached: True Linker: False.
INFO:S7PLL:Creating S7PLL, speedgrade -1.
INFO:S7PLL:Registering Single Ended ClkIn of 125.00MHz.
INFO:S7PLL:Creating ClkOut0 eth_tx of 125.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut1 eth_tx_delayed of 125.00MHz (+-10000.00ppm).
Traceback (most recent call last):
  File "/home/somlo/LITEX/litex-boards/litex_boards/targets/digilent_nexys_video.py", line 206, in <module>
    main()
  File "/home/somlo/LITEX/litex-boards/litex_boards/targets/digilent_nexys_video.py", line 182, in main
    soc = BaseSoC(
          ^^^^^^^^
  File "/home/somlo/LITEX/litex-boards/litex_boards/targets/digilent_nexys_video.py", line 108, in __init__
    self.add_ethernet(phy=self.ethphy)
  File "/home/somlo/LITEX/litex/litex/soc/integration/soc.py", line 1666, in add_ethernet
    ethmac = LiteEthMAC(
             ^^^^^^^^^^^
  File "/home/somlo/LITEX/liteeth/liteeth/mac/__init__.py", line 37, in __init__
    self.submodules.core = LiteEthMACCore(
                           ^^^^^^^^^^^^^^^
  File "/home/somlo/LITEX/liteeth/liteeth/mac/core.py", line 126, in __init__
    tx_datapath.add_crc()
  File "/home/somlo/LITEX/liteeth/liteeth/mac/core.py", line 94, in add_crc
    tx_crc = BufferizeEndpoints({"sink": DIR_SINK})(tx_crc) # FIXME: Still required?
             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/migen/fhdl/decorators.py", line 49, in __call__
    return self.wrap_instance(victim)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/migen/fhdl/decorators.py", line 36, in wrap_instance
    self.transform_instance(victim)
  File "/home/somlo/LITEX/litex/litex/soc/interconnect/stream.py", line 998, in transform_instance
    pipe_valid = pipe_valid,
                 ^^^^^^^^^^
NameError: name 'pipe_valid' is not defined. Did you mean: 'PipeValid'?