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  1. env PYTHONPATH=. python3 examples/basic.py nmigen_boards.orangecrab_r0_2.OrangeCrabR0_2Platform
  2. create bit enable
  3. events
  4. (0, 'rise') (sig zero_stb)
  5.  
  6. event_enable <systemonachip.register.event.AggregateEventEnable object at 0x7fddd71d6850>
  7. event_status <systemonachip.register.event.AggregateEventStatus object at 0x7fddd71d6910>
  8. event zero <systemonachip.event.Event object at 0x7fddd71d6810>
  9. csrs
  10. (8, 0) (rec enable r_data r_stb w_data w_stb)
  11. (12, None) (rec value r_data r_stb w_data w_stb)
  12. (4, None) (rec reload_ r_data r_stb w_data w_stb)
  13.  
  14. Traceback (most recent call last):
  15. File "examples/basic.py", line 101, in <module>
  16. f.write(verilog.convert(soc))
  17. File "/home/ericb/.local/lib/python3.7/site-packages/nmigen/back/verilog.py", line 77, in convert
  18. return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)
  19. File "/home/ericb/.local/lib/python3.7/site-packages/nmigen/back/verilog.py", line 65, in _convert_rtlil_text
  20. raise YosysError(error.strip())
  21. nmigen.back.verilog.YosysError: ERROR: Parser error in line 21049: syntax error
  22.  
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