env PYTHONPATH=. python3 examples/basic.py nmigen_boards.orangecrab_r0_2.OrangeCrabR0_2Platform
create bit enable
events
(0, 'rise') (sig zero_stb)

event_enable <systemonachip.register.event.AggregateEventEnable object at 0x7fddd71d6850>
event_status <systemonachip.register.event.AggregateEventStatus object at 0x7fddd71d6910>
event zero <systemonachip.event.Event object at 0x7fddd71d6810>
csrs
(8, 0) (rec enable r_data r_stb w_data w_stb)
(12, None) (rec value r_data r_stb w_data w_stb)
(4, None) (rec reload_ r_data r_stb w_data w_stb)

Traceback (most recent call last):
  File "examples/basic.py", line 101, in <module>
    f.write(verilog.convert(soc))
  File "/home/ericb/.local/lib/python3.7/site-packages/nmigen/back/verilog.py", line 77, in convert
    return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)
  File "/home/ericb/.local/lib/python3.7/site-packages/nmigen/back/verilog.py", line 65, in _convert_rtlil_text
    raise YosysError(error.strip())
nmigen.back.verilog.YosysError: ERROR: Parser error in line 21049: syntax error