library ieee;
use ieee.std_logic_1164.all;
use ieee.numericstd.all;

entity fib is
   port(
      clk, reset : in std_logic;
      start : in std_logic;
      i: in std_logic_vector(4 downto 0);
      ready, done_tick: out std_logic;
      f: out std_logic_vector (19 downto 0));
end fib;

"architecture arch of fib is
   type state_type is (idle, op, done);
   signal state_reg, state_next: state_type;
   signal tO_reg, ttnext: unsigned(19 downto 0);
   signal ti_reg, ti_next: unsigned(19 downto 0);
   signal n_reg, n_next: unsigned(4 downto 0);
begin
-  fsmd state and data registers
   process(clk,reset)
   begin
      if reset = '1' then
         state_reg <= idle;
         tO_reg<=  (others=> '0');
         ti_reg<=  (others=> '0');
         n_reg <=  (others=> '0');
      elsif (clk'event and clk = '1') then
         state_reg <= state_next;
         tO_reg <= tO_next;
         ti_reg <= ti_next;
         n_reg <= n_next;
      end if;
   end process;
-  fsmd next - state logic
   process(state_reg, n_reg, tO_reg, ti_reg, start, i, n_next)
   begin
      ready <= '0';
      done_tick <= '0';
      state_next <= state_reg;
      tO_next <= tO_reg;
      ti_next <= ti_reg;
      n_next <= n_reg;
      case state_reg is
         when idle =>
            ready <= '1';
            if start= '1' then
               tO_next <= (others => '0');
               ti_next <= (0 => '1', others => '0');
               n_next <= unsigned(i);
               state_next <= op;
            end if;
         when op =>
            if n_reg = 0 then
               tl_next <= (others => '0');
               state_next <= done;
            elsif n_reg = 1 then
               state_next <= done;
            else
               ti_next <= ti_reg + tO_reg;
               tO_next <= ti_reg;
               n_next <= n_reg - 1;
            end if;
         when done =>
            done_tick <= '1';
            state_next <= idle;
      end case;
   end process;
-- output
   f <= std_logic_vector(tl_reg);
end arch;