Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- module reg_maps_to_wire(input A, B, clk,
- output reg f1, f2);
- always @(posedge clk) begin
- f2 <= f1 ^ f2;
- f1 <= ~(A & B);
- end
- endmodule
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement