library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity weight_bram_wrapper_tb is
end;

architecture bench of weight_bram_wrapper_tb is

component weight_bram_wrapper
port (
  BRAM_PORTA_addr : in STD_LOGIC_VECTOR ( 12 downto 0 );
  BRAM_PORTA_clk : in STD_LOGIC;
  BRAM_PORTA_din : in STD_LOGIC_VECTOR ( 31 downto 0 );
  BRAM_PORTA_dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
  BRAM_PORTA_en : in STD_LOGIC;
  BRAM_PORTA_we : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component;

signal BRAM_PORTA_addr: STD_LOGIC_VECTOR ( 12 downto 0 );
signal BRAM_PORTA_clk: STD_LOGIC;
signal BRAM_PORTA_din: STD_LOGIC_VECTOR ( 31 downto 0 );
signal BRAM_PORTA_dout: STD_LOGIC_VECTOR ( 31 downto 0 );
signal BRAM_PORTA_en: STD_LOGIC;
signal BRAM_PORTA_we: STD_LOGIC_VECTOR ( 3 downto 0 ) ;

begin

uut: weight_bram_wrapper port map ( BRAM_PORTA_addr => BRAM_PORTA_addr,
                                  BRAM_PORTA_clk  => BRAM_PORTA_clk,
                                  BRAM_PORTA_din  => BRAM_PORTA_din,
                                  BRAM_PORTA_dout => BRAM_PORTA_dout,
                                  BRAM_PORTA_en   => BRAM_PORTA_en,
                                  BRAM_PORTA_we   => BRAM_PORTA_we );

stimulus: process
begin

-- Put initialisation code here


-- Put test bench stimulus code here

wait;
end process;


end;