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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * P2020 RDB Device Tree Source
  4. *
  5. * Copyright 2009-2012 Freescale Semiconductor Inc.
  6. */
  7.  
  8. /dts-v1/;
  9.  
  10. /include/ "fsl/p2020si-pre.dtsi"
  11.  
  12. #include <dt-bindings/gpio/gpio.h>
  13. #include <dt-bindings/input/input.h>
  14.  
  15. / {
  16. model = "WatchGuard XTM 330";
  17. compatible = "fsl,P2020RDB";
  18.  
  19. aliases {
  20. ethernet0 = &enet0;
  21. ethernet1 = &enet1;
  22. ethernet2 = &enet2;
  23. serial0 = &serial0;
  24. serial1 = &serial1;
  25. pci0 = &pci0;
  26. pci1 = &pci1;
  27. };
  28.  
  29. memory {
  30. device_type = "memory";
  31. };
  32.  
  33. lbc: localbus@ffe05000 {
  34. reg = <0 0xffe05000 0 0x1000>;
  35.  
  36. /* NOR and NAND Flashes */
  37. ranges = <0x00 0x00 0x00 0xefe00000 0x200000 0x01 0x00 0x00 0xffa00000 0x40000>;
  38.  
  39. nor@0,0 {
  40. #address-cells = <0x01>;
  41. #size-cells = <0x01>;
  42. compatible = "cfi-flash";
  43. reg = <0x00 0x00 0x200000>;
  44. bank-width = <0x02>;
  45. device-width = <0x01>;
  46.  
  47. partition@00000000 {
  48. reg = <0x00 0x20000>;
  49. label = "NOR (RW) WG CFG0";
  50. };
  51.  
  52. partition@00020000 {
  53. reg = <0x20000 0x10000>;
  54. label = "NOR (RW) WG CFG1";
  55. };
  56.  
  57. partition@00030000 {
  58. reg = <0x30000 0x10000>;
  59. label = "NOR (RW) WG MFG DATA";
  60. };
  61.  
  62. partition@00040000 {
  63. reg = <0x40000 0xb0000>;
  64. label = "NOR (RW) WG bootOpt Data & reserved";
  65. };
  66.  
  67. partition@000F0000 {
  68. reg = <0xf0000 0x10000>;
  69. label = "NOR (RW) WG U-Boot ENV";
  70. };
  71.  
  72. partition@00100000 {
  73. reg = <0x100000 0x80000>;
  74. label = "NOR (RW) WG U-Boot Image";
  75. };
  76.  
  77. partition@00180000 {
  78. reg = <0x180000 0x80000>;
  79. label = "NOR (RW) WG U-Boot FAILSAFE";
  80. };
  81. };
  82.  
  83. nand@1,0 {
  84. #address-cells = <0x01>;
  85. #size-cells = <0x01>;
  86. compatible = "fsl,p2020-fcm-nand\0fsl,elbc-fcm-nand";
  87. reg = <0x01 0x00 0x40000>;
  88. nand-ecc-step-size = <512>;
  89. nand-ecc-strength = <16>;
  90.  
  91. partition@00000000 {
  92. reg = <0x00 0x20000>;
  93. label = "NAND (RW) WG DTB Image";
  94. };
  95.  
  96. partition@00020000 {
  97. reg = <0x20000 0x500000>;
  98. label = "NAND (RW) WG SYSA Kernel";
  99. };
  100.  
  101. partition@00520000 {
  102. reg = <0x520000 0x79e0000>;
  103. label = "NAND (RW) WG SYSA_CODE";
  104. };
  105.  
  106. partition@07f00000 {
  107. reg = <0x7f00000 0x16000000>;
  108. label = "NAND (RW) WG SYSA_DATA";
  109. };
  110.  
  111. partition@1df00000 {
  112. reg = <0x1df00000 0x500000>;
  113. label = "NAND (RW) WG SYSB Kernel";
  114. };
  115.  
  116. partition@1e400000 {
  117. reg = <0x1e400000 0x1800000>;
  118. label = "NAND (RW) WG SYSB_CODE";
  119. };
  120.  
  121. partition@1fc00000 {
  122. reg = <0x1fc00000 0x400000>;
  123. label = "NAND (RW) WG KDUMP";
  124. };
  125. };
  126.  
  127. };
  128.  
  129. soc: soc@ffe00000 {
  130. ranges = <0x0 0x0 0xffe00000 0x100000>;
  131.  
  132. gpio0: gpio-controller@fc00 {
  133. };
  134.  
  135. i2c@3000 {
  136. temperature-sensor@4c {
  137. compatible = "adi,adt7461";
  138. reg = <0x4c>;
  139. };
  140.  
  141. eeprom@50 {
  142. compatible = "atmel,24c256";
  143. reg = <0x50>;
  144. };
  145.  
  146. rtc@68 {
  147. compatible = "dallas,ds1339";
  148. reg = <0x68>;
  149. };
  150. };
  151.  
  152. i2c@3100 {
  153. pmic@11 {
  154. compatible = "zl2006";
  155. reg = <0x11>;
  156. };
  157.  
  158. gpio@18 {
  159. compatible = "nxp,pca9557";
  160. reg = <0x18>;
  161. };
  162.  
  163. eeprom@52 {
  164. compatible = "atmel,24c01";
  165. reg = <0x52>;
  166. };
  167. };
  168.  
  169.  
  170.  
  171. mdio0: mdio@24520 {
  172. reg = <0x24520 0x20>;
  173. switch0: switch@10 {
  174. compatible = "marvell,mv88e6085";
  175. reg = <0x10 0x0>;
  176.  
  177. dsa,member = <0 0>;
  178.  
  179. mdio {
  180. #address-cells = <1>;
  181. #size-cells = <0>;
  182.  
  183. switch0phy0: switch0phy0@0 {
  184. reg = <0x00>;
  185. interrupt-parent = <&switch0>;
  186. };
  187.  
  188. switch0phy1: switch0phy1@1 {
  189. reg = <0x01>;
  190. interrupt-parent = <&switch0>;
  191. };
  192.  
  193. switch0phy2: switch0phy2@2 {
  194. reg = <0x02>;
  195. interrupt-parent = <&switch0>;
  196. };
  197.  
  198. switch0phy3: switch0phy3@3 {
  199. reg = <0x03>;
  200. interrupt-parent = <&switch0>;
  201. };
  202.  
  203. switch0phy4: switch0phy4@4 {
  204. reg = <0x04>;
  205. interrupt-parent = <&switch0>;
  206. };
  207. };
  208.  
  209. ports {
  210.  
  211. port@0 {
  212. reg = <0>;
  213. label = "seth4";
  214. phy-handle = <&switch0phy0>;
  215. };
  216.  
  217. port@1 {
  218. reg = <1>;
  219. label = "seth5";
  220. phy-handle = <&switch0phy1>;
  221. };
  222.  
  223. port@2 {
  224. reg = <2>;
  225. label = "seth6";
  226. phy-handle = <&switch0phy2>;
  227. };
  228.  
  229. switch0phy5: port@5 {
  230. reg = <5>;
  231. label = "cpu0";
  232. ethernet = <&enet0>;
  233. phy-mode = "rgmii-id";
  234. fixed-link {
  235. speed = <1000>;
  236. full-duplex;
  237. };
  238. };
  239. };
  240. };
  241.  
  242. switch1: switch@11 {
  243. compatible = "marvell,mv88e6085";
  244. reg = <0x11>;
  245.  
  246. dsa,member = <1 0>;
  247.  
  248. mdio {
  249. #address-cells = <1>;
  250. #size-cells = <0>;
  251.  
  252. switch1phy0: switch1phy0@0 {
  253. reg = <0x00>;
  254. interrupt-parent = <&switch1>;
  255. };
  256.  
  257. switch1phy1: switch1phy1@1 {
  258. reg = <0x01>;
  259. interrupt-parent = <&switch1>;
  260. };
  261.  
  262. switch1phy2: switch1phy2@2 {
  263. reg = <0x02>;
  264. interrupt-parent = <&switch1>;
  265. };
  266.  
  267. switch1phy3: switch1phy3@3 {
  268. reg = <0x03>;
  269. interrupt-parent = <&switch1>;
  270. };
  271.  
  272. switch1phy4: switch1phy4@4 {
  273. reg = <0x04>;
  274. interrupt-parent = <&switch1>;
  275. };
  276. };
  277.  
  278. ports {
  279.  
  280. port@0 {
  281. reg = <0>;
  282. label = "seth0";
  283. phy-handle = <&switch1phy0>;
  284. };
  285.  
  286. port@1 {
  287. reg = <1>;
  288. label = "seth1";
  289. phy-handle = <&switch1phy1>;
  290. };
  291.  
  292. port@2 {
  293. reg = <2>;
  294. label = "seth2";
  295. phy-handle = <&switch1phy2>;
  296. };
  297.  
  298. port@3 {
  299. reg = <3>;
  300. label = "seth3";
  301. phy-handle = <&switch1phy3>;
  302. };
  303.  
  304. switch1phy5: port@5 {
  305. reg = <5>;
  306. label = "cpu1";
  307. ethernet = <&enet2>;
  308. phy-mode = "rgmii-id";
  309. fixed-link {
  310. speed = <1000>;
  311. full-duplex;
  312. };
  313. };
  314. };
  315. };
  316. };
  317.  
  318. mdio@25520 {
  319. #address-cells = <0x01>;
  320. #size-cells = <0x00>;
  321. compatible = "fsl,gianfar-tbi";
  322. reg = <0x25520 0x20>;
  323. };
  324.  
  325. mdio@26520 {
  326. #address-cells = <0x01>;
  327. #size-cells = <0x00>;
  328. compatible = "fsl,gianfar-tbi";
  329. reg = <0x26520 0x20>;
  330. };
  331.  
  332. enet0: ethernet@24000 {
  333. #address-cells = <0x01>;
  334. #size-cells = <0x01>;
  335. cell-index = <0x00>;
  336. device_type = "network";
  337. model = "eTSEC";
  338. compatible = "gianfar";
  339. reg = <0x24000 0x1000>;
  340. ranges = <0x00 0x24000 0x1000>;
  341. fixed-link = <0x01 0x01 0x3e8 0x00 0x00>;
  342. phy-connection-type = "rgmii-id";
  343. phy-handle = <&switch0phy5>;
  344. };
  345.  
  346. ethernet@25000 {
  347. status = "disabled";
  348. };
  349.  
  350. enet1: enet2: ethernet@26000 {
  351. phy-connection-type = "rgmii-id";
  352. device_type = "network";
  353. model = "eTSEC";
  354. compatible = "gianfar";
  355. reg = <0x26000 0x1000>;
  356. ranges = <0x00 0x26000 0x1000>;
  357. fixed-link = <0x02 0x01 0x3e8 0x00 0x00>;
  358. phy-handle = <&switch1phy5>;
  359. };
  360.  
  361.  
  362. usb@22000 {
  363. phy_type = "ulpi";
  364. dr_mode = "host";
  365. };
  366.  
  367. ptp_clock@24e00 {
  368. fsl,tclk-period = <5>;
  369. fsl,tmr-prsc = <200>;
  370. fsl,tmr-add = <0xCCCCCCCD>;
  371. fsl,tmr-fiper1 = <0x3B9AC9FB>;
  372. fsl,tmr-fiper2 = <0x0001869B>;
  373. fsl,max-adj = <249999999>;
  374. };
  375.  
  376. pic@40000 {
  377. interrupt-controller;
  378. #address-cells = <0x00>;
  379. #interrupt-cells = <0x04>;
  380. reg = <0x40000 0x40000>;
  381. compatible = "fsl,mpic";
  382. device_type = "open-pic";
  383. big-endian;
  384. single-cpu-affinity;
  385. last-interrupt-source = <0xff>;
  386. linux,phandle = <0x01>;
  387. phandle = <0x01>;
  388. };
  389.  
  390. timer@41100 {
  391. compatible = "fsl,mpic-global-timer";
  392. reg = <0x41100 0x100 0x41300 0x04>;
  393. interrupts = <0x00 0x00 0x03 0x00 0x01 0x00 0x03 0x00 0x02 0x00 0x03 0x00 0x03 0x00 0x03 0x00>;
  394. };
  395.  
  396. timer@42100 {
  397. compatible = "fsl,mpic-global-timer";
  398. reg = <0x42100 0x100 0x42300 0x04>;
  399. interrupts = <0x04 0x00 0x03 0x00 0x05 0x00 0x03 0x00 0x06 0x00 0x03 0x00 0x07 0x00 0x03 0x00>;
  400. };
  401. };
  402.  
  403. pci0: pcie@ffe08000 {
  404. reg = <0 0xffe08000 0 0x1000>;
  405. status = "disabled";
  406. };
  407.  
  408. pci1: pcie@ffe09000 {
  409. reg = <0 0xffe09000 0 0x1000>;
  410. ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
  411. 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
  412. pcie@0 {
  413. ranges = <0x2000000 0x0 0xa0000000
  414. 0x2000000 0x0 0xa0000000
  415. 0x0 0x20000000
  416.  
  417. 0x1000000 0x0 0x0
  418. 0x1000000 0x0 0x0
  419. 0x0 0x100000>;
  420. };
  421. };
  422.  
  423. pci2: pcie@ffe0a000 {
  424. reg = <0 0xffe0a000 0 0x1000>;
  425. ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
  426. 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
  427. pcie@0 {
  428. ranges = <0x2000000 0x0 0x80000000
  429. 0x2000000 0x0 0x80000000
  430. 0x0 0x20000000
  431.  
  432. 0x1000000 0x0 0x0
  433. 0x1000000 0x0 0x0
  434. 0x0 0x100000>;
  435. };
  436. };
  437. };
  438.  
  439. /include/ "fsl/p2020si-post.dtsi"
  440.  
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