`timescale 1ns / 1ps

// LCD Write Test ("Hello")
// ----------------------------------------------------------------------------
// For:     Hitachi HD44780 Controller (And Compatible)
//          8-Bit Mode
//
// Author:  Geoff Sevart

module LCD_Hitachi_HD44780_8Bit_WriteTestDiagnostic(
         input CLK,
         output [7:0] LCD_D,
         output LCD_RS,
         output LCD_RW,
         output LCD_E,
         output Done
    );

    reg [31:0] counter_cycles;
    reg [7:0] caseindex;

    reg [7:0] ib_DB;
    reg ib_RS;
    reg ib_E;

    reg ib_Done;

    initial begin
        ib_DB = 0;
        ib_RS = 0;
        ib_E = 0;

        ib_Done = 0;
    end

    always @(posedge CLK) begin
        case(caseindex)
            //*** *** *** WRITE DDRAM BYTE *** *** ***

            0: begin
                //Set Data, RS, and E - Then Wait for Data Setup

                ib_DB <= 8'b01001000;
                ib_RS <= 1;
                ib_E <= 0;
                caseindex <= 1;
            end

            1: begin
                //Delay

                if (counter_cycles == 10) begin
                    counter_cycles <= 0;
                    caseindex <= 2;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            2: begin
                //Raise E - Then Wait for Recognition

                ib_E <= 1;
                caseindex <= 3;
            end

            3: begin
                //Delay

                if (counter_cycles == 25) begin
                    counter_cycles <= 0;
                    caseindex <= 4;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            4: begin
                //Drop E - Then Wait for Command to Complete

                ib_E <= 0;
                caseindex <= 5;
            end

            5: begin
                //Delay

                if (counter_cycles == 2500) begin
                    counter_cycles <= 0;
                    caseindex <= 6;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            //*** *** *** WRITE DDRAM BYTE *** *** ***

            6: begin
                //Set Data, RS, and E - Then Wait for Data Setup

                ib_DB <= 8'b01100101;
                ib_RS <= 1;
                ib_E <= 0;
                caseindex <= 7;
            end

            7: begin
                //Delay

                if (counter_cycles == 10) begin
                    counter_cycles <= 0;
                    caseindex <= 8;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            8: begin
                //Raise E - Then Wait for Recognition

                ib_E <= 1;
                caseindex <= 9;
            end

            9: begin
                //Delay

                if (counter_cycles == 25) begin
                    counter_cycles <= 0;
                    caseindex <= 10;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            10: begin
                //Drop E - Then Wait for Command to Complete

                ib_E <= 0;
                caseindex <= 11;
            end

            11: begin
                //Delay

                if (counter_cycles == 2500) begin
                    counter_cycles <= 0;
                    caseindex <= 12;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            //*** *** *** WRITE DDRAM BYTE *** *** ***

            12: begin
                //Set Data, RS, and E - Then Wait for Data Setup

                ib_DB <= 8'b01101100;
                ib_RS <= 1;
                ib_E <= 0;
                caseindex <= 13;
            end

            13: begin
                //Delay

                if (counter_cycles == 10) begin
                    counter_cycles <= 0;
                    caseindex <= 14;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            14: begin
                //Raise E - Then Wait for Recognition

                ib_E <= 1;
                caseindex <= 15;
            end

            15: begin
                //Delay

                if (counter_cycles == 25) begin
                    counter_cycles <= 0;
                    caseindex <= 16;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            16: begin
                //Drop E - Then Wait for Command to Complete

                ib_E <= 0;
                caseindex <= 17;
            end

            17: begin
                //Delay

                if (counter_cycles == 2500) begin
                    counter_cycles <= 0;
                    caseindex <= 18;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            //*** *** *** WRITE DDRAM BYTE *** *** ***

            18: begin
                //Set Data, RS, and E - Then Wait for Data Setup

                ib_DB <= 8'b01101100;
                ib_RS <= 1;
                ib_E <= 0;
                caseindex <= 19;
            end

            19: begin
                //Delay

                if (counter_cycles == 10) begin
                    counter_cycles <= 0;
                    caseindex <= 20;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            20: begin
                //Raise E - Then Wait for Recognition

                ib_E <= 1;
                caseindex <= 21;
            end

            21: begin
                //Delay

                if (counter_cycles == 25) begin
                    counter_cycles <= 0;
                    caseindex <= 22;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            22: begin
                //Drop E - Then Wait for Command to Complete

                ib_E <= 0;
                caseindex <= 23;
            end

            23: begin
                //Delay

                if (counter_cycles == 2500) begin
                    counter_cycles <= 0;
                    caseindex <= 24;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            //*** *** *** WRITE DDRAM BYTE *** *** ***

            24: begin
                //Set Data, RS, and E - Then Wait for Data Setup

                ib_DB <= 8'b01101111;
                ib_RS <= 1;
                ib_E <= 0;
                caseindex <= 25;
            end

            25: begin
                //Delay

                if (counter_cycles == 10) begin
                    counter_cycles <= 0;
                    caseindex <= 26;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            26: begin
                //Raise E - Then Wait for Recognition

                ib_E <= 1;
                caseindex <= 27;
            end

            27: begin
                //Delay

                if (counter_cycles == 25) begin
                    counter_cycles <= 0;
                    caseindex <= 28;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            28: begin
                //Drop E - Then Wait for Command to Complete

                ib_E <= 0;
                caseindex <= 29;
            end

            29: begin
                //Delay

                if (counter_cycles == 2500) begin
                    counter_cycles <= 0;
                    caseindex <= 30;
                end else begin
                    counter_cycles <= counter_cycles + 1;
                end
            end

            30: begin
                ib_Done <= 1;
            end
        endcase
    end

    assign LCD_Data = ib_Done ? 1'bz : ib_DB;
    assign LCD_RS = ib_Done ? 1'bz : ib_RS;
    assign LCD_RW = ib_Done ? 1'bz : 0;
    assign LCD_E = ib_Done ? 1'bz : ib_E;

    assign Done = ib_Done;

endmodule