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- Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
- 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017
- The NetBSD Foundation, Inc. All rights reserved.
- Copyright (c) 1982, 1986, 1989, 1991, 1993
- The Regents of the University of California. All rights reserved.
- NetBSD 8.99.2 (RPI2) #2: Tue Sep 26 08:18:28 DST 2017
- nick@DESKTOP-EOUPKTI:/home/nick/obj.evbearmv7hf-el/home/nick/netbsd-src/sys/arch/evbarm/compile/RPI2
- total memory = 944 MB
- avail memory = 923 MB
- sysctl_createv: sysctl_create(machine_arch) returned 17
- armfdt0 (root)
- fdt0 at armfdt0: Raspberry Pi 2 Model B Rev 1.1
- fdt1 at fdt0
- fdt2 at fdt0
- cpus0 at fdt0
- cpu0 at cpus0: 600 MHz Cortex-A7 r0p5 (Cortex V7A core)
- cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
- cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
- cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
- cpu0: 512KB/64B 8-way write-through L2 PIPT Unified cache
- vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
- cpu1 at cpus0
- cpu2 at cpus0
- cpu3 at cpus0
- bcmicu0 at fdt1
- bcmicu1 at fdt1: Multiprocessor
- gtmr0 at fdt0: Generic Timer
- armgtmr0 at gtmr0: ARMv7 Generic 64-bit Timer (19200 kHz)
- fclock0 at fdt2: 19200000 Hz fixed clock
- /soc/dsi@7e209000 at fdt1 not configured
- bcmgpio0 at fdt1: GPIO controller
- gpio0 at bcmgpio0: 32 pins
- gpio1 at bcmgpio0: 22 pins
- bcmcm0 at fdt1: CM
- bcmdmac0 at fdt1: DMA0 DMA2 DMA4 DMA5 DMA8 DMA9 DMA10
- /soc/power at fdt1 not configured
- /soc/aux@0x7e215000 at fdt1 not configured
- bsciic0 at fdt1: Broadcom Serial Controller
- iic0 at bsciic0: I2C bus
- fclock1 at fdt2: 480000000 Hz fixed clock
- bcmmbox0 at fdt1: VC mailbox
- bcmmbox0: interrupting on intr icu irq 193
- vcmbox0 at bcmmbox0
- /soc/firmware at fdt1 not configured
- /chosen at fdt0 not configured
- gpioleds0 at fdt0: ACT PWR
- /soc/timer@7e003000 at fdt1 not configured
- watchdog0 at fdt1: Power management, Reset and Watchdog controller
- bcmrng0 at fdt1: RNG
- plcom0 at fdt1
- plcom0: txfifo disabled
- plcom0: console
- bsciic1 at fdt1: Broadcom Serial Controller
- iic1 at bsciic1: I2C bus
- /soc/pixelvalve@7e206000 at fdt1 not configured
- /soc/pixelvalve@7e207000 at fdt1 not configured
- /soc/thermal@7e212000 at fdt1 not configured
- /soc/pwm@7e20c000 at fdt1 not configured
- sdhc0 at fdt1: SDHC controller
- sdhc0: interrupting on icu irq 190
- /soc/hvs@7e400000 at fdt1 not configured
- bsciic2 at fdt1: Broadcom Serial Controller
- iic2 at bsciic2: I2C bus
- /soc/vec@7e806000 at fdt1 not configured
- /soc/pixelvalve@7e807000 at fdt1 not configured
- /soc/hdmi@7e902000 at fdt1 not configured
- dwctwo0 at fdt1: USB controller
- dwctwo0: interrupting on icu irq 137
- /soc/v3d@7ec00000 at fdt1 not configured
- /soc/gpu at fdt1 not configured
- /soc/arm-pmu at fdt1 not configured
- cpu1: 600 MHz Cortex-A7 r0p5 (Cortex V7A core)
- cpu1: DC enabled IC enabled WB disabled EABT branch prediction enabled
- cpu1: 32KB/32B 2-way L1 VIPT Instruction cache
- cpu1: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
- cpu1: 512KB/64B 8-way write-through L2 PIPT Unified cache
- vfp1 at cpu1: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
- cpu3: 600 MHz Cortex-A7 r0p5 (Cortex V7A core)
- cpu3: DC enabled IC enabled WB disabled EABT branch prediction enabled
- cpu3: 32KB/32B 2-way L1 VIPT Instruction cache
- cpu3: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
- cpu3: 512KB/64B 8-way write-through L2 PIPT Unified cache
- vfp3 at cpu3: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
- cpu2: 600 MHz Cortex-A7 r0p5 (Cortex V7A core)
- cpu2: DC enabled IC enabled WB disabled EABT branch prediction enabled
- cpu2: 32KB/32B 2-way L1 VIPT Instruction cache
- cpu2: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
- cpu2: 512KB/64B 8-way write-through L2 PIPT Unified cache
- vfp2 at cpu2: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
- sdhc0: SDHC 3.0, rev 153, platform DMA, 250000 kHz, HS 3.3V, re-tuning mode 1, 1024 byte blocks
- sdmmc0 at sdhc0 slot 0
- usb0 at dwctwo0: USB revision 2.0
- uhub0 at usb0: vendor 0000 (0000) DWC2 root hub (0000), class 9/0, rev 2.00/1.00, addr 1
- uhub1 at uhub0 port 1: vendor 0424 (0x424) product 9514 (0x9514), class 9/0, rev 2.00/2.00, addr 2
- uhub1: multiple transaction translators
- uhub0: illegal enable change, port 1
- sdmmc0: switch func mode 0 failed
- sdmmc0: mem init failed
- ld0 at sdmmc0: <0x02:0x544d:SA08G:0x10:0x26ec28e4:0x0bb>
- ld0: 7460 MB, 3789 cyl, 64 head, 63 sec, 512 bytes/sect x 15278080 sectors
- ld0c: error reading fsbn 0 (ld0 bn 0; cn 0 tn 0 sn 0), retrying
- ld0c: error reading fsbn 0 (ld0 bn 0; cn 0 tn 0 sn 0), retrying
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