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  1. Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
  2. 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017
  3. The NetBSD Foundation, Inc. All rights reserved.
  4. Copyright (c) 1982, 1986, 1989, 1991, 1993
  5. The Regents of the University of California. All rights reserved.
  6.  
  7. NetBSD 8.99.2 (RPI2) #2: Tue Sep 26 08:18:28 DST 2017
  8. nick@DESKTOP-EOUPKTI:/home/nick/obj.evbearmv7hf-el/home/nick/netbsd-src/sys/arch/evbarm/compile/RPI2
  9. total memory = 944 MB
  10. avail memory = 923 MB
  11. sysctl_createv: sysctl_create(machine_arch) returned 17
  12. armfdt0 (root)
  13. fdt0 at armfdt0: Raspberry Pi 2 Model B Rev 1.1
  14. fdt1 at fdt0
  15. fdt2 at fdt0
  16. cpus0 at fdt0
  17. cpu0 at cpus0: 600 MHz Cortex-A7 r0p5 (Cortex V7A core)
  18. cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
  19. cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
  20. cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
  21. cpu0: 512KB/64B 8-way write-through L2 PIPT Unified cache
  22. vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
  23. cpu1 at cpus0
  24. cpu2 at cpus0
  25. cpu3 at cpus0
  26. bcmicu0 at fdt1
  27. bcmicu1 at fdt1: Multiprocessor
  28. gtmr0 at fdt0: Generic Timer
  29. armgtmr0 at gtmr0: ARMv7 Generic 64-bit Timer (19200 kHz)
  30. fclock0 at fdt2: 19200000 Hz fixed clock
  31. /soc/dsi@7e209000 at fdt1 not configured
  32. bcmgpio0 at fdt1: GPIO controller
  33. gpio0 at bcmgpio0: 32 pins
  34. gpio1 at bcmgpio0: 22 pins
  35. bcmcm0 at fdt1: CM
  36. bcmdmac0 at fdt1: DMA0 DMA2 DMA4 DMA5 DMA8 DMA9 DMA10
  37. /soc/power at fdt1 not configured
  38. /soc/aux@0x7e215000 at fdt1 not configured
  39. bsciic0 at fdt1: Broadcom Serial Controller
  40. iic0 at bsciic0: I2C bus
  41. fclock1 at fdt2: 480000000 Hz fixed clock
  42. bcmmbox0 at fdt1: VC mailbox
  43. bcmmbox0: interrupting on intr icu irq 193
  44. vcmbox0 at bcmmbox0
  45. /soc/firmware at fdt1 not configured
  46. /chosen at fdt0 not configured
  47. gpioleds0 at fdt0: ACT PWR
  48. /soc/timer@7e003000 at fdt1 not configured
  49. watchdog0 at fdt1: Power management, Reset and Watchdog controller
  50. bcmrng0 at fdt1: RNG
  51. plcom0 at fdt1
  52. plcom0: txfifo disabled
  53. plcom0: console
  54. bsciic1 at fdt1: Broadcom Serial Controller
  55. iic1 at bsciic1: I2C bus
  56. /soc/pixelvalve@7e206000 at fdt1 not configured
  57. /soc/pixelvalve@7e207000 at fdt1 not configured
  58. /soc/thermal@7e212000 at fdt1 not configured
  59. /soc/pwm@7e20c000 at fdt1 not configured
  60. sdhc0 at fdt1: SDHC controller
  61. sdhc0: interrupting on icu irq 190
  62. /soc/hvs@7e400000 at fdt1 not configured
  63. bsciic2 at fdt1: Broadcom Serial Controller
  64. iic2 at bsciic2: I2C bus
  65. /soc/vec@7e806000 at fdt1 not configured
  66. /soc/pixelvalve@7e807000 at fdt1 not configured
  67. /soc/hdmi@7e902000 at fdt1 not configured
  68. dwctwo0 at fdt1: USB controller
  69. dwctwo0: interrupting on icu irq 137
  70. /soc/v3d@7ec00000 at fdt1 not configured
  71. /soc/gpu at fdt1 not configured
  72. /soc/arm-pmu at fdt1 not configured
  73. cpu1: 600 MHz Cortex-A7 r0p5 (Cortex V7A core)
  74. cpu1: DC enabled IC enabled WB disabled EABT branch prediction enabled
  75. cpu1: 32KB/32B 2-way L1 VIPT Instruction cache
  76. cpu1: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
  77. cpu1: 512KB/64B 8-way write-through L2 PIPT Unified cache
  78. vfp1 at cpu1: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
  79. cpu3: 600 MHz Cortex-A7 r0p5 (Cortex V7A core)
  80. cpu3: DC enabled IC enabled WB disabled EABT branch prediction enabled
  81. cpu3: 32KB/32B 2-way L1 VIPT Instruction cache
  82. cpu3: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
  83. cpu3: 512KB/64B 8-way write-through L2 PIPT Unified cache
  84. vfp3 at cpu3: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
  85. cpu2: 600 MHz Cortex-A7 r0p5 (Cortex V7A core)
  86. cpu2: DC enabled IC enabled WB disabled EABT branch prediction enabled
  87. cpu2: 32KB/32B 2-way L1 VIPT Instruction cache
  88. cpu2: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
  89. cpu2: 512KB/64B 8-way write-through L2 PIPT Unified cache
  90. vfp2 at cpu2: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
  91. sdhc0: SDHC 3.0, rev 153, platform DMA, 250000 kHz, HS 3.3V, re-tuning mode 1, 1024 byte blocks
  92. sdmmc0 at sdhc0 slot 0
  93. usb0 at dwctwo0: USB revision 2.0
  94. uhub0 at usb0: vendor 0000 (0000) DWC2 root hub (0000), class 9/0, rev 2.00/1.00, addr 1
  95. uhub1 at uhub0 port 1: vendor 0424 (0x424) product 9514 (0x9514), class 9/0, rev 2.00/2.00, addr 2
  96. uhub1: multiple transaction translators
  97. uhub0: illegal enable change, port 1
  98. sdmmc0: switch func mode 0 failed
  99. sdmmc0: mem init failed
  100. ld0 at sdmmc0: <0x02:0x544d:SA08G:0x10:0x26ec28e4:0x0bb>
  101. ld0: 7460 MB, 3789 cyl, 64 head, 63 sec, 512 bytes/sect x 15278080 sectors
  102. ld0c: error reading fsbn 0 (ld0 bn 0; cn 0 tn 0 sn 0), retrying
  103. ld0c: error reading fsbn 0 (ld0 bn 0; cn 0 tn 0 sn 0), retrying
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