VERA_ADDR_LO = $9f20
VERA_ADDR_MID = $9f21
VERA_ADDR_HI = $9f22
VERA_DATA0 = $9f23

verareg =$9f20

veralo  = verareg+0
veramid = verareg+1
verahi  = verareg+2
veradat = verareg+3
veradat2= verareg+4
veractl = verareg+5
veraien = verareg+6
veraisr = verareg+7

vreg_cmp  = $F0000
vreg_pal  = $F1000
vreg_lay1 = $F2000
vreg_lay2 = $F3000
vreg_spr  = $F4000
vreg_sprd = $F5000

AUTO_INC_1 = $100000

.macro vset addr
	lda #<(addr >> 16) | $10
	sta verahi
	lda #<(addr >> 8)
	sta veramid
	lda #<(addr)
	sta veralo
.endmacro

.segment "CODE"

        .word   $0801       ; load address
        .word   $080b       ; address of next basic line
        .word   2019        ; line number
        .byte   $9E             ; SYS token
        .byte   '2', '0', '6', '1'
        .byte   $00             ; end of BASIC line
        .word   0               ; BASIC end marker

		sei

    ; video init
    lda #0
    sta veractl ; set ADDR1 active
    sta veramid
    lda #$1F    ; $F0000 increment 1
    sta verahi
    lda #$00
    sta veralo
    lda #1
    sta veradat ; VGA output

	vset (0 | AUTO_INC_1)

    lda #0
    sta 4
    lda #$2c
    sta 5
    lda #1
    sta 6
	ldy #0
	lda #<bitmap
	sta 2
	lda #>bitmap
	sta 3
loop1:	lda (2),y
	sta veradat
	inc 2
	bne loop2
	inc 3
	lda #$9f
	cmp 3
	bne test2
; start RAM bank address
    lda #$a0
    sta 3
    lda #0
    sta $9f61
test2:
; test for next RAM bank
    lda #$c0
    cmp 3
    bne loop2
    lda #$a0
    sta 3
    inc $9f61
loop2:
    dec 4
    lda 4
    cmp #$ff
	bne loop1
	dec 5
	lda 5
	cmp #$ff
	bne loop1
	dec 6
	bpl loop1

	vset (vreg_pal | AUTO_INC_1)

	ldx #2
	ldy #0
	lda #<palette
	sta 2
	lda #>palette
	sta 3
loop3:	lda (2),y
	sta veradat
	iny
	bne loop3
	inc 3
	dex
	bne loop3

	vset (vreg_lay2 | AUTO_INC_1)

	lda #0
	sta veradat

	vset (vreg_lay1 | AUTO_INC_1)

	lda #7 << 5 | 1; // mode=7, enabled=1
	sta veradat ; 0
	; ignore
	sta veradat ; 1
	; ignore
	sta veradat ; 2
	; ignore
	sta veradat ; 3
	lda #(0 >> 2) & $ff; // map_base
	sta veradat; 4
	lda #0 >> 10;
	sta veradat ; 5

	vset (vreg_cmp + 1 | AUTO_INC_1)

	lda #64
	sta veradat ; hscale=2x
	sta veradat ; vscale=2x



stop:	jmp stop

palette:
    .incbin "mode7-palette.bin"

bitmap: