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  1. => fdt print /
  2. / {
  3. interrupt-parent = <0x00008002>;
  4. model = "linux,dummy-virt";
  5. #size-cells = <0x00000002>;
  6. #address-cells = <0x00000002>;
  7. compatible = "linux,dummy-virt";
  8. psci {
  9. migrate = <0xc4000005>;
  10. cpu_on = <0xc4000003>;
  11. cpu_off = <0x84000002>;
  12. cpu_suspend = <0xc4000001>;
  13. method = "hvc";
  14. compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
  15. };
  16. memory@40000000 {
  17. reg = <0x00000000 0x40000000 0x00000000 0x08000000>;
  18. device_type = "memory";
  19. };
  20. platform-bus@c000000 {
  21. interrupt-parent = <0x00008002>;
  22. ranges = <0x00000000 0x00000000 0x0c000000 0x02000000>;
  23. #address-cells = <0x00000001>;
  24. #size-cells = <0x00000001>;
  25. compatible = "qemu,platform", "simple-bus";
  26. };
  27. fw-cfg@9020000 {
  28. dma-coherent;
  29. reg = <0x00000000 0x09020000 0x00000000 0x00000018>;
  30. compatible = "qemu,fw-cfg-mmio";
  31. };
  32. virtio_mmio@a000000 {
  33. dma-coherent;
  34. interrupts = <0x00000000 0x00000010 0x00000001>;
  35. reg = <0x00000000 0x0a000000 0x00000000 0x00000200>;
  36. compatible = "virtio,mmio";
  37. };
  38. virtio_mmio@a000200 {
  39. dma-coherent;
  40. interrupts = <0x00000000 0x00000011 0x00000001>;
  41. reg = <0x00000000 0x0a000200 0x00000000 0x00000200>;
  42. compatible = "virtio,mmio";
  43. };
  44. virtio_mmio@a000400 {
  45. dma-coherent;
  46. interrupts = <0x00000000 0x00000012 0x00000001>;
  47. reg = <0x00000000 0x0a000400 0x00000000 0x00000200>;
  48. compatible = "virtio,mmio";
  49. };
  50. virtio_mmio@a000600 {
  51. dma-coherent;
  52. interrupts = <0x00000000 0x00000013 0x00000001>;
  53. reg = <0x00000000 0x0a000600 0x00000000 0x00000200>;
  54. compatible = "virtio,mmio";
  55. };
  56. virtio_mmio@a000800 {
  57. dma-coherent;
  58. interrupts = <0x00000000 0x00000014 0x00000001>;
  59. reg = <0x00000000 0x0a000800 0x00000000 0x00000200>;
  60. compatible = "virtio,mmio";
  61. };
  62. virtio_mmio@a000a00 {
  63. dma-coherent;
  64. interrupts = <0x00000000 0x00000015 0x00000001>;
  65. reg = <0x00000000 0x0a000a00 0x00000000 0x00000200>;
  66. compatible = "virtio,mmio";
  67. };
  68. virtio_mmio@a000c00 {
  69. dma-coherent;
  70. interrupts = <0x00000000 0x00000016 0x00000001>;
  71. reg = <0x00000000 0x0a000c00 0x00000000 0x00000200>;
  72. compatible = "virtio,mmio";
  73. };
  74. virtio_mmio@a000e00 {
  75. dma-coherent;
  76. interrupts = <0x00000000 0x00000017 0x00000001>;
  77. reg = <0x00000000 0x0a000e00 0x00000000 0x00000200>;
  78. compatible = "virtio,mmio";
  79. };
  80. virtio_mmio@a001000 {
  81. dma-coherent;
  82. interrupts = <0x00000000 0x00000018 0x00000001>;
  83. reg = <0x00000000 0x0a001000 0x00000000 0x00000200>;
  84. compatible = "virtio,mmio";
  85. };
  86. virtio_mmio@a001200 {
  87. dma-coherent;
  88. interrupts = <0x00000000 0x00000019 0x00000001>;
  89. reg = <0x00000000 0x0a001200 0x00000000 0x00000200>;
  90. compatible = "virtio,mmio";
  91. };
  92. virtio_mmio@a001400 {
  93. dma-coherent;
  94. interrupts = <0x00000000 0x0000001a 0x00000001>;
  95. reg = <0x00000000 0x0a001400 0x00000000 0x00000200>;
  96. compatible = "virtio,mmio";
  97. };
  98. virtio_mmio@a001600 {
  99. dma-coherent;
  100. interrupts = <0x00000000 0x0000001b 0x00000001>;
  101. reg = <0x00000000 0x0a001600 0x00000000 0x00000200>;
  102. compatible = "virtio,mmio";
  103. };
  104. virtio_mmio@a001800 {
  105. dma-coherent;
  106. interrupts = <0x00000000 0x0000001c 0x00000001>;
  107. reg = <0x00000000 0x0a001800 0x00000000 0x00000200>;
  108. compatible = "virtio,mmio";
  109. };
  110. virtio_mmio@a001a00 {
  111. dma-coherent;
  112. interrupts = <0x00000000 0x0000001d 0x00000001>;
  113. reg = <0x00000000 0x0a001a00 0x00000000 0x00000200>;
  114. compatible = "virtio,mmio";
  115. };
  116. virtio_mmio@a001c00 {
  117. dma-coherent;
  118. interrupts = <0x00000000 0x0000001e 0x00000001>;
  119. reg = <0x00000000 0x0a001c00 0x00000000 0x00000200>;
  120. compatible = "virtio,mmio";
  121. };
  122. virtio_mmio@a001e00 {
  123. dma-coherent;
  124. interrupts = <0x00000000 0x0000001f 0x00000001>;
  125. reg = <0x00000000 0x0a001e00 0x00000000 0x00000200>;
  126. compatible = "virtio,mmio";
  127. };
  128. virtio_mmio@a002000 {
  129. dma-coherent;
  130. interrupts = <0x00000000 0x00000020 0x00000001>;
  131. reg = <0x00000000 0x0a002000 0x00000000 0x00000200>;
  132. compatible = "virtio,mmio";
  133. };
  134. virtio_mmio@a002200 {
  135. dma-coherent;
  136. interrupts = <0x00000000 0x00000021 0x00000001>;
  137. reg = <0x00000000 0x0a002200 0x00000000 0x00000200>;
  138. compatible = "virtio,mmio";
  139. };
  140. virtio_mmio@a002400 {
  141. dma-coherent;
  142. interrupts = <0x00000000 0x00000022 0x00000001>;
  143. reg = <0x00000000 0x0a002400 0x00000000 0x00000200>;
  144. compatible = "virtio,mmio";
  145. };
  146. virtio_mmio@a002600 {
  147. dma-coherent;
  148. interrupts = <0x00000000 0x00000023 0x00000001>;
  149. reg = <0x00000000 0x0a002600 0x00000000 0x00000200>;
  150. compatible = "virtio,mmio";
  151. };
  152. virtio_mmio@a002800 {
  153. dma-coherent;
  154. interrupts = <0x00000000 0x00000024 0x00000001>;
  155. reg = <0x00000000 0x0a002800 0x00000000 0x00000200>;
  156. compatible = "virtio,mmio";
  157. };
  158. virtio_mmio@a002a00 {
  159. dma-coherent;
  160. interrupts = <0x00000000 0x00000025 0x00000001>;
  161. reg = <0x00000000 0x0a002a00 0x00000000 0x00000200>;
  162. compatible = "virtio,mmio";
  163. };
  164. virtio_mmio@a002c00 {
  165. dma-coherent;
  166. interrupts = <0x00000000 0x00000026 0x00000001>;
  167. reg = <0x00000000 0x0a002c00 0x00000000 0x00000200>;
  168. compatible = "virtio,mmio";
  169. };
  170. virtio_mmio@a002e00 {
  171. dma-coherent;
  172. interrupts = <0x00000000 0x00000027 0x00000001>;
  173. reg = <0x00000000 0x0a002e00 0x00000000 0x00000200>;
  174. compatible = "virtio,mmio";
  175. };
  176. virtio_mmio@a003000 {
  177. dma-coherent;
  178. interrupts = <0x00000000 0x00000028 0x00000001>;
  179. reg = <0x00000000 0x0a003000 0x00000000 0x00000200>;
  180. compatible = "virtio,mmio";
  181. };
  182. virtio_mmio@a003200 {
  183. dma-coherent;
  184. interrupts = <0x00000000 0x00000029 0x00000001>;
  185. reg = <0x00000000 0x0a003200 0x00000000 0x00000200>;
  186. compatible = "virtio,mmio";
  187. };
  188. virtio_mmio@a003400 {
  189. dma-coherent;
  190. interrupts = <0x00000000 0x0000002a 0x00000001>;
  191. reg = <0x00000000 0x0a003400 0x00000000 0x00000200>;
  192. compatible = "virtio,mmio";
  193. };
  194. virtio_mmio@a003600 {
  195. dma-coherent;
  196. interrupts = <0x00000000 0x0000002b 0x00000001>;
  197. reg = <0x00000000 0x0a003600 0x00000000 0x00000200>;
  198. compatible = "virtio,mmio";
  199. };
  200. virtio_mmio@a003800 {
  201. dma-coherent;
  202. interrupts = <0x00000000 0x0000002c 0x00000001>;
  203. reg = <0x00000000 0x0a003800 0x00000000 0x00000200>;
  204. compatible = "virtio,mmio";
  205. };
  206. virtio_mmio@a003a00 {
  207. dma-coherent;
  208. interrupts = <0x00000000 0x0000002d 0x00000001>;
  209. reg = <0x00000000 0x0a003a00 0x00000000 0x00000200>;
  210. compatible = "virtio,mmio";
  211. };
  212. virtio_mmio@a003c00 {
  213. dma-coherent;
  214. interrupts = <0x00000000 0x0000002e 0x00000001>;
  215. reg = <0x00000000 0x0a003c00 0x00000000 0x00000200>;
  216. compatible = "virtio,mmio";
  217. };
  218. virtio_mmio@a003e00 {
  219. dma-coherent;
  220. interrupts = <0x00000000 0x0000002f 0x00000001>;
  221. reg = <0x00000000 0x0a003e00 0x00000000 0x00000200>;
  222. compatible = "virtio,mmio";
  223. };
  224. pcie@10000000 {
  225. interrupt-map-mask = <0x00001800 0x00000000 0x00000000 0x00000007>;
  226. interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00008002 0x00000000 0x00000000 0x00000000 0x00000003 0x00000004 0x00000000 0x00000000 0x00000000 0x00000002 0x00008002 0x00000000 0x00000000 0x00000000 0x00000004 0x00000004 0x00000000 0x00000000 0x00000000 0x00000003 0x00008002 0x00000000 0x00000000 0x00000000 0x00000005 0x00000004 0x00000000 0x00000000 0x00000000 0x00000004 0x00008002 0x00000000 0x00000000 0x00000000 0x00000006 0x00000004 0x00000800 0x00000000 0x00000000 0x00000001 0x00008002 0x00000000 0x00000000 0x00000000 0x00000004 0x00000004 0x00000800 0x00000000 0x00000000 0x00000002 0x00008002 0x00000000 0x00000000 0x00000000 0x00000005 0x00000004 0x00000800 0x00000000 0x00000000 0x00000003 0x00008002 0x00000000 0x00000000 0x00000000 0x00000006 0x00000004 0x00000800 0x00000000 0x00000000 0x00000004 0x00008002 0x00000000 0x00000000 0x00000000 0x00000003 0x00000004 0x00001000 0x00000000 0x00000000 0x00000001 0x00008002 0x00000000 0x00000000 0x00000000 0x00000005 0x00000004 0x00001000 0x00000000 0x00000000 0x00000002 0x00008002 0x00000000 0x00000000 0x00000000 0x00000006 0x00000004 0x00001000 0x00000000 0x00000000 0x00000003 0x00008002 0x00000000 0x00000000 0x00000000 0x00000003 0x00000004 0x00001000 0x00000000 0x00000000 0x00000004 0x00008002 0x00000000 0x00000000 0x00000000 0x00000004 0x00000004 0x00001800 0x00000000 0x00000000 0x00000001 0x00008002 0x00000000 0x00000000 0x00000000 0x00000006 0x00000004 0x00001800 0x00000000 0x00000000 0x00000002 0x00008002 0x00000000 0x00000000 0x00000000 0x00000003 0x00000004 0x00001800 0x00000000 0x00000000 0x00000003 0x00008002 0x00000000 0x00000000 0x00000000 0x00000004 0x00000004 0x00001800 0x00000000 0x00000000 0x00000004 0x00008002 0x00000000 0x00000000 0x00000000 0x00000005 0x00000004>;
  227. #interrupt-cells = <0x00000001>;
  228. ranges = <0x01000000 0x00000000 0x00000000 0x00000000 0x3eff0000 0x00000000 0x00010000 0x02000000 0x00000000 0x10000000 0x00000000 0x10000000 0x00000000 0x2eff0000 0x03000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000080 0x00000000>;
  229. reg = <0x00000040 0x10000000 0x00000000 0x10000000>;
  230. msi-map = <0x00000000 0x00008003 0x00000000 0x00010000>;
  231. dma-coherent;
  232. bus-range = <0x00000000 0x000000ff>;
  233. linux,pci-domain = <0x00000000>;
  234. #size-cells = <0x00000002>;
  235. #address-cells = <0x00000003>;
  236. device_type = "pci";
  237. compatible = "pci-host-ecam-generic";
  238. };
  239. pl031@9010000 {
  240. clock-names = "apb_pclk";
  241. clocks = <0x00008000>;
  242. interrupts = <0x00000000 0x00000002 0x00000004>;
  243. reg = <0x00000000 0x09010000 0x00000000 0x00001000>;
  244. compatible = "arm,pl031", "arm,primecell";
  245. };
  246. pl011@9000000 {
  247. clock-names = "uartclk", "apb_pclk";
  248. clocks = <0x00008000 0x00008000>;
  249. interrupts = <0x00000000 0x00000001 0x00000004>;
  250. reg = <0x00000000 0x09000000 0x00000000 0x00001000>;
  251. compatible = "arm,pl011", "arm,primecell";
  252. };
  253. pmu {
  254. interrupts = <0x00000001 0x00000007 0x00000104>;
  255. compatible = "arm,armv8-pmuv3";
  256. };
  257. intc@8000000 {
  258. phandle = <0x00008002>;
  259. reg = <0x00000000 0x08000000 0x00000000 0x00010000 0x00000000 0x08010000 0x00000000 0x00010000>;
  260. compatible = "arm,cortex-a15-gic";
  261. ranges;
  262. #size-cells = <0x00000002>;
  263. #address-cells = <0x00000002>;
  264. interrupt-controller;
  265. #interrupt-cells = <0x00000003>;
  266. v2m@8020000 {
  267. phandle = <0x00008003>;
  268. reg = <0x00000000 0x08020000 0x00000000 0x00001000>;
  269. msi-controller;
  270. compatible = "arm,gic-v2m-frame";
  271. };
  272. };
  273. flash@0 {
  274. bank-width = <0x00000004>;
  275. reg = <0x00000000 0x00000000 0x00000000 0x04000000 0x00000000 0x04000000 0x00000000 0x04000000>;
  276. compatible = "cfi-flash";
  277. };
  278. cpus {
  279. #size-cells = <0x00000000>;
  280. #address-cells = <0x00000001>;
  281. cpu-map {
  282. socket0 {
  283. cluster0 {
  284. core0 {
  285. cpu = <0x00008001>;
  286. };
  287. };
  288. };
  289. };
  290. cpu@0 {
  291. phandle = <0x00008001>;
  292. reg = <0x00000000>;
  293. compatible = "arm,cortex-a57";
  294. device_type = "cpu";
  295. };
  296. };
  297. timer {
  298. interrupts = <0x00000001 0x0000000d 0x00000104 0x00000001 0x0000000e 0x00000104 0x00000001 0x0000000b 0x00000104 0x00000001 0x0000000a 0x00000104>;
  299. always-on;
  300. compatible = "arm,armv8-timer", "arm,armv7-timer";
  301. };
  302. apb-pclk {
  303. phandle = <0x00008000>;
  304. clock-output-names = "clk24mhz";
  305. clock-frequency = <0x016e3600>;
  306. #clock-cells = <0x00000000>;
  307. compatible = "fixed-clock";
  308. };
  309. chosen {
  310. stdout-path = "/pl011@9000000";
  311. rng-seed = <0xc0ea6ff4 0xc8b6e2a5 0xf8abec8b 0x67961ddd 0x75b2b8e2 0xee18c70d 0x4420cd15 0x3b4f109c>;
  312. kaslr-seed = <0xaa14cf5e 0xca97f01c>;
  313. };
  314. };
  315.  
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