OpenRISC-1200 (rev 1)
D-Cache: no
I-Cache: 4096 bytes, 16 bytes/line, 1 way(s)
DMMU: no
IMMU: no
MAC unit: yes
Debug unit: yes
Performance counters: no
Power management: yes
Interrupt controller: yes
Timer: yes
Custom unit(s): no
ORBIS32: yes
ORBIS64: no
ORFPX32: no
ORFPX64: no
Test support for l.addc...yes
Test support for l.cmov...yes
Test support for l.cust1...no
Test support for l.cust2...no
Test support for l.cust3...no
Test support for l.cust4...no
Test support for l.cust5...no
Test support for l.cust6...no
Test support for l.cust7...no
Test support for l.cust8...no
Test support for l.div...yes
Test support for l.divu...yes
Test support for l.extbs...yes
Test support for l.extbz...yes
Test support for l.exths...yes
Test support for l.exthz...yes
Test support for l.extws...yes
Test support for l.extwz...yes
Test support for l.ff1...yes
Test support for l.fl1...yes
Test support for l.lws...no
Test support for l.mac...yes
Test support for l.maci...yes
Test support for l.macrc...yes
Test support for l.mul...yes
Test support for l.muli...yes
Test support for l.mulu...yes
Test support for l.ror...yes
Test support for l.rori...yes
Test timer functionality...OK
Set clock source to LOSC...done
Test CLK freq...22416 Hz = 22 KHz
Set clock source to Internal OSC ...done
Test CLK freq...11376016 Hz = 11 MHz
Set clock source to HOSC (POSTDIV=0, DIV=0)...done
Test CLK freq...23995504 Hz = 24 MHz
Set clock source to HOSC (POSTDIV=0, DIV=1)...done
Test CLK freq...11991184 Hz = 12 MHz
Set clock source to HOSC (POSTDIV=1, DIV=1)...done
Test CLK freq...11992912 Hz = 12 MHz
Setup PLL6 (M=1, K=1, N=24)...done
Set clock source to PLL6 (POSTDIV=1, DIV=0)...done
Test CLK freq...299769984 Hz = 300 MHz

  == Benchmark ==
   == Code in SRAM A2 (I-cache ON), data in SRAM A2 ==
      Instructions fetch : 1.0 cycles per instruction
      Back-to-back L.LWZ : 3.0 cycles per 32-bit read
           L.LWZ + L.NOP : 4.0 cycles per 32-bit read
   == Code in SRAM A2 (I-cache ON), data in SRAM A1 ==
      Instructions fetch : 1.0 cycles per instruction
      Back-to-back L.LWZ : 3.0 cycles per 32-bit read
           L.LWZ + L.NOP : 15.9 cycles per 32-bit read
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▒%4߲#▒▒▒▒1▒▒L/▒}▒▒K▒▒C▒*▒▒*▒▒▒▒\▒▒9,Bg▒▒▒}.5|▒▒#▒▒R▒4▒t▒▒el}▒Cq▒▒?▒`.▒*▒▒▒▒3▒Q▒▒;▒▒▒▒*u▒y▒▒-T▒`▒`I?J▒▒͓*ס▒▒B   == Code in SRAM A2 (I-cache OFF), data in SRAM A2 ==
      Instructions fetch : 3.0 cycles per instruction
      Back-to-back L.LWZ : 4.5 cycles per 32-bit read
           L.LWZ + L.NOP : 8.0 cycles per 32-bit read
   == Code in SRAM A2 (I-cache OFF), data in SRAM A1 ==
      Instructions fetch : 3.0 cycles per instruction
      Back-to-back L.LWZ : 16.2 cycles per 32-bit read
           L.LWZ + L.NOP : 20.9 cycles per 32-bit read

Set clock source to PLL6 (POSTDIV=2, DIV=0)...done
Test CLK freq...199834576 Hz = 200 MHz
Set clock source to PLL6 (POSTDIV=2, DIV=1)...done
Test CLK freq...99923056 Hz = 100 MHz
Setup PLL6 (M=2, K=1, N=24)...done
Test CLK freq...99952864 Hz = 100 MHz
Setup PLL6 (M=1, K=2, N=24)...done
Test CLK freq...149942720 Hz = 150 MHz
Setup PLL6 (M=1, K=1, N=12)...done
Test CLK freq...51984800 Hz = 52 MHz
Restore clock config to original state...done
All tests completed!