licznik_testbench

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   17:53:09 05/20/2019
-- Design Name:
-- Module Name:   C:/Users/Student/Desktop/fpga_lab_t_s/Licznik1/licznik1_testbench.vhd
-- Project Name:  Licznik1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: module1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY licznik1_testbench IS
END licznik1_testbench;

ARCHITECTURE behavior OF licznik1_testbench IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT module1
    PORT(
         clk : IN  std_logic;
         res : IN  std_logic;
         outmod : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal clk : std_logic := '0';
   signal res : std_logic := '0';

 	--Outputs
   signal outmod : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
   uut: module1 PORT MAP (
          clk => clk,
          res => res,
          outmod => outmod
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for 10 ns;
		clk <= '1';
		wait for 10 ns;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
			res <= '1';
		wait for 20 ns;
			res <= '0';

      wait;
   end process;

END;