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Jun 22nd, 2015
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  1. Release 14.7 par P.20131013 (lin64)
  2. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  3.  
  4. w530:: Mon Jun 22 18:40:48 2015
  5.  
  6. par -ol high -w nandreader-nandreadersoc-pipistrello_map.ncd
  7. nandreader-nandreadersoc-pipistrello.ncd
  8. nandreader-nandreadersoc-pipistrello.pcf
  9.  
  10.  
  11. Constraints file: nandreader-nandreadersoc-pipistrello.pcf.
  12. Loading device for application Rf_Device from file '6slx45.nph' in environment /mnt/lu/opt/Xilinx/14.7/ISE_DS/ISE/.
  13. "top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -3
  14.  
  15. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
  16. Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
  17.  
  18.  
  19. Device speed data version: "PRODUCTION 1.23 2013-10-13".
  20.  
  21.  
  22.  
  23. Device Utilization Summary:
  24.  
  25. Slice Logic Utilization:
  26. Number of Slice Registers: 2,401 out of 54,576 4%
  27. Number used as Flip Flops: 2,396
  28. Number used as Latches: 0
  29. Number used as Latch-thrus: 0
  30. Number used as AND/OR logics: 5
  31. Number of Slice LUTs: 3,098 out of 27,288 11%
  32. Number used as logic: 2,873 out of 27,288 10%
  33. Number using O6 output only: 2,157
  34. Number using O5 output only: 62
  35. Number using O5 and O6: 654
  36. Number used as ROM: 0
  37. Number used as Memory: 199 out of 6,408 3%
  38. Number used as Dual Port RAM: 192
  39. Number using O6 output only: 0
  40. Number using O5 output only: 16
  41. Number using O5 and O6: 176
  42. Number used as Single Port RAM: 0
  43. Number used as Shift Register: 7
  44. Number using O6 output only: 6
  45. Number using O5 output only: 0
  46. Number using O5 and O6: 1
  47. Number used exclusively as route-thrus: 26
  48. Number with same-slice register load: 24
  49. Number with same-slice carry load: 2
  50. Number with other load: 0
  51.  
  52. Slice Logic Distribution:
  53. Number of occupied Slices: 1,175 out of 6,822 17%
  54. Number of MUXCYs used: 468 out of 13,644 3%
  55. Number of LUT Flip Flop pairs used: 3,629
  56. Number with an unused Flip Flop: 1,538 out of 3,629 42%
  57. Number with an unused LUT: 531 out of 3,629 14%
  58. Number of fully used LUT-FF pairs: 1,560 out of 3,629 42%
  59. Number of slice register sites lost
  60. to control set restrictions: 0 out of 54,576 0%
  61.  
  62. A LUT Flip Flop pair for this architecture represents one LUT paired with
  63. one Flip Flop within a slice. A control set is a unique combination of
  64. clock, reset, set, and enable signals for a registered element.
  65. The Slice Logic Distribution report is not meaningful if the design is
  66. over-mapped for a non-slice resource or if Placement fails.
  67.  
  68. IO Utilization:
  69. Number of bonded IOBs: 77 out of 218 35%
  70. Number of LOCed IOBs: 77 out of 77 100%
  71. IOB Flip Flops: 6
  72.  
  73. Specific Feature Utilization:
  74. Number of RAMB16BWERs: 11 out of 116 9%
  75. Number of RAMB8BWERs: 3 out of 232 1%
  76. Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
  77. Number used as BUFIO2s: 1
  78. Number used as BUFIO2_2CLKs: 0
  79. Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
  80. Number of BUFG/BUFGMUXs: 3 out of 16 18%
  81. Number used as BUFGs: 3
  82. Number used as BUFGMUX: 0
  83. Number of DCM/DCM_CLKGENs: 0 out of 8 0%
  84. Number of ILOGIC2/ISERDES2s: 16 out of 376 4%
  85. Number used as ILOGIC2s: 0
  86. Number used as ISERDES2s: 16
  87. Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
  88. Number of OLOGIC2/OSERDES2s: 22 out of 376 5%
  89. Number used as OLOGIC2s: 4
  90. Number used as OSERDES2s: 18
  91. Number of BSCANs: 0 out of 4 0%
  92. Number of BUFHs: 0 out of 256 0%
  93. Number of BUFPLLs: 1 out of 8 12%
  94. Number of BUFPLL_MCBs: 0 out of 4 0%
  95. Number of DSP48A1s: 3 out of 58 5%
  96. Number of ICAPs: 0 out of 1 0%
  97. Number of MCBs: 0 out of 2 0%
  98. Number of PCILOGICSEs: 0 out of 2 0%
  99. Number of PLL_ADVs: 1 out of 4 25%
  100. Number of PMVs: 0 out of 1 0%
  101. Number of STARTUPs: 0 out of 1 0%
  102. Number of SUSPEND_SYNCs: 0 out of 1 0%
  103.  
  104.  
  105. Overall effort level (-ol): High
  106. Router effort level (-rl): High
  107.  
  108. Starting initial Timing Analysis. REAL time: 8 secs
  109. Finished initial Timing Analysis. REAL time: 8 secs
  110.  
  111. WARNING:Par:288 - The signal obj_ledio_led0_IBUF has no load. PAR will not attempt to route this signal.
  112. WARNING:Par:288 - The signal obj_ledio_led1_IBUF has no load. PAR will not attempt to route this signal.
  113. WARNING:Par:288 - The signal obj_ledio_led2_IBUF has no load. PAR will not attempt to route this signal.
  114. WARNING:Par:288 - The signal obj_ledio_led3_IBUF has no load. PAR will not attempt to route this signal.
  115. WARNING:Par:288 - The signal nandreadersoc_nandreadersoc_nandreadersoc_serial_cts_IBUF has no load. PAR will not attempt to route this
  116. signal.
  117. WARNING:Par:288 - The signal nandreadersoc_nandreadersoc_nandreadersoc_serial_rts_IBUF has no load. PAR will not attempt to route this
  118. signal.
  119. WARNING:Par:288 - The signal obj_second_serial_cts_IBUF has no load. PAR will not attempt to route this signal.
  120. WARNING:Par:288 - The signal obj_second_serial_rts_IBUF has no load. PAR will not attempt to route this signal.
  121. Starting Router
  122.  
  123.  
  124. Phase 1 : 20465 unrouted; REAL time: 9 secs
  125.  
  126. Phase 2 : 17902 unrouted; REAL time: 11 secs
  127.  
  128. Phase 3 : 7900 unrouted; REAL time: 20 secs
  129.  
  130. Phase 4 : 7900 unrouted; (Setup:0, Hold:3807, Component Switching Limit:0) REAL time: 22 secs
  131.  
  132. Updating file: nandreader-nandreadersoc-pipistrello.ncd with current fully routed design.
  133.  
  134. Phase 5 : 0 unrouted; (Setup:0, Hold:3360, Component Switching Limit:0) REAL time: 35 secs
  135.  
  136. Phase 6 : 0 unrouted; (Setup:0, Hold:3360, Component Switching Limit:0) REAL time: 35 secs
  137.  
  138. Phase 7 : 0 unrouted; (Setup:0, Hold:3360, Component Switching Limit:0) REAL time: 35 secs
  139.  
  140. Phase 8 : 0 unrouted; (Setup:0, Hold:3360, Component Switching Limit:0) REAL time: 35 secs
  141.  
  142. Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 36 secs
  143.  
  144. Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 39 secs
  145. Total REAL time to Router completion: 39 secs
  146. Total CPU time to Router completion: 41 secs
  147.  
  148. Partition Implementation Status
  149. -------------------------------
  150.  
  151. No Partitions were found in this design.
  152.  
  153. -------------------------------
  154.  
  155. Generating "PAR" statistics.
  156.  
  157. **************************
  158. Generating Clock Report
  159. **************************
  160.  
  161. +---------------------+--------------+------+------+------------+-------------+
  162. | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
  163. +---------------------+--------------+------+------+------------+-------------+
  164. | sys_clk | BUFGMUX_X2Y2| No | 812 | 0.168 | 1.381 |
  165. +---------------------+--------------+------+------+------------+-------------+
  166. | sdram_half_clk | BUFGMUX_X3Y13| No | 17 | 0.484 | 1.743 |
  167. +---------------------+--------------+------+------+------------+-------------+
  168. |nandreadersoc_crg_cl | | | | | |
  169. |k_sdram_half_shifted | | | | | |
  170. | | BUFGMUX_X2Y3| No | 4 | 0.000 | 1.774 |
  171. +---------------------+--------------+------+------+------------+-------------+
  172. | sdram_full_wr_clk | Local| | 34 | 0.028 | 1.533 |
  173. +---------------------+--------------+------+------+------------+-------------+
  174.  
  175. * Net Skew is the difference between the minimum and maximum routing
  176. only delays for the net. Note this is different from Clock Skew which
  177. is reported in TRCE timing report. Clock Skew is the difference between
  178. the minimum and maximum path delays which includes logic delays.
  179.  
  180. * The fanout is the number of component pins not the individual BEL loads,
  181. for example SLICE loads not FF loads.
  182.  
  183. Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
  184.  
  185. Number of Timing Constraints that were not applied: 4
  186.  
  187. Asterisk (*) preceding a constraint indicates it was not met.
  188. This may be due to a setup or hold violation.
  189.  
  190. ----------------------------------------------------------------------------------------------------------
  191. Constraint | Check | Worst Case | Best Case | Timing | Timing
  192. | | Slack | Achievable | Errors | Score
  193. ----------------------------------------------------------------------------------------------------------
  194. TS_nandreadersoc_crg_pll_2_ = PERIOD TIME | SETUP | 0.012ns| 6.650ns| 0| 0
  195. GRP "nandreadersoc_crg_pll_2_" TS | HOLD | 0.476ns| | 0| 0
  196. _nandreadersoc_crg_clk50b / 3 PHASE 5 ns | | | | |
  197. HIGH 50% | | | | |
  198. ----------------------------------------------------------------------------------------------------------
  199. TS_nandreadersoc_crg_pll_5_ = PERIOD TIME | SETUP | 0.226ns| 12.381ns| 0| 0
  200. GRP "nandreadersoc_crg_pll_5_" TS | HOLD | 0.043ns| | 0| 0
  201. _nandreadersoc_crg_clk50b / 1.5 HIGH 50% | | | | |
  202. ----------------------------------------------------------------------------------------------------------
  203. TS_nandreadersoc_crg_clk50b = PERIOD TIME | MINLOWPULSE | 15.000ns| 5.000ns| 0| 0
  204. GRP "nandreadersoc_crg_clk50b" TS | | | | |
  205. clk50 HIGH 50% | | | | |
  206. ----------------------------------------------------------------------------------------------------------
  207. TS_nandreadersoc_crg_pll_3_ = PERIOD TIME | MINPERIOD | 4.936ns| 1.730ns| 0| 0
  208. GRP "nandreadersoc_crg_pll_3_" TS | | | | |
  209. _nandreadersoc_crg_clk50b / 3 PHASE 4.629 | | | | |
  210. 62963 ns HIGH 50% | | | | |
  211. ----------------------------------------------------------------------------------------------------------
  212. TSclk50 = PERIOD TIMEGRP "GRPclk50" 20 ns | MINPERIOD | 19.075ns| 0.925ns| 0| 0
  213. HIGH 50% | | | | |
  214. ----------------------------------------------------------------------------------------------------------
  215. TS_nandreadersoc_crg_pll_0_ = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
  216. GRP "nandreadersoc_crg_pll_0_" TS | | | | |
  217. _nandreadersoc_crg_clk50b / 6 HIGH 50% | | | | |
  218. ----------------------------------------------------------------------------------------------------------
  219.  
  220.  
  221. Derived Constraint Report
  222. Review Timing Report for more details on the following derived constraints.
  223. To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
  224. or "Run Timing Analysis" from Timing Analyzer (timingan).
  225. Derived Constraints for TSclk50
  226. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  227. | | Period | Actual Period | Timing Errors | Paths Analyzed |
  228. | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
  229. | | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
  230. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  231. |TSclk50 | 20.000ns| 0.925ns| 19.950ns| 0| 0| 0| 367284|
  232. | TS_nandreadersoc_crg_clk50b | 20.000ns| 5.000ns| 19.950ns| 0| 0| 0| 367284|
  233. | TS_nandreadersoc_crg_pll_3_ | 6.667ns| 1.730ns| N/A| 0| 0| 0| 0|
  234. | TS_nandreadersoc_crg_pll_5_ | 13.333ns| 12.381ns| N/A| 0| 0| 367034| 0|
  235. | TS_nandreadersoc_crg_pll_0_ | 3.333ns| N/A| N/A| 0| 0| 0| 0|
  236. | TS_nandreadersoc_crg_pll_2_ | 6.667ns| 6.650ns| N/A| 0| 0| 250| 0|
  237. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  238.  
  239. All constraints were met.
  240. INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
  241. constraint is not analyzed due to the following: No paths covered by this
  242. constraint; Other constraints intersect with this constraint; or This
  243. constraint was disabled by a Path Tracing Control. Please run the Timespec
  244. Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
  245.  
  246.  
  247. Generating Pad Report.
  248.  
  249. All signals are completely routed.
  250.  
  251. WARNING:Par:283 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
  252.  
  253. Total REAL time to PAR completion: 41 secs
  254. Total CPU time to PAR completion: 43 secs
  255.  
  256. Peak Memory Usage: 795 MB
  257.  
  258. Placer: Placement generated during map.
  259. Routing: Completed - No errors found.
  260. Timing: Completed - No errors found.
  261.  
  262. Number of error messages: 0
  263. Number of warning messages: 10
  264. Number of info messages: 0
  265.  
  266. Writing design to file nandreader-nandreadersoc-pipistrello.ncd
  267.  
  268.  
  269.  
  270. PAR done!
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