i

// higher level to debounce clock
// done is an led
// buswires are the 7-seg and leds


module Processor(Data, w, Clock, Done, Buswires);// remove reset F, Rx, Ry. | W is the run switch | [done]
	input [7:0] Data;
	input w, Clock;
	output wire [7:0] Buswires;
	output Done;
	reg [0:3] Rin, Rout;
	reg [7:0] Sum;
	wire Clear, AddSub, Extern, Ain, Gin, Gout, FRin;
	wire [1:0] Count;
	wire [0:3] T,I, Xreg, Y;
	wire [7:0] R0, R1, R2, R3, A, G;
	wire [7:0] Func, FuncReg; // change to match the data 7:0[done]
	integer k;

	upcount counter (Clear, Clock, Count);
	dec2to4 decT(count, 1'b1, T);

	assign Clear = Done | (~w & T[0]);
	assign Func = Data; // make func = data
	assign FRin = w & T[0];

	regn functionreg (Func, FRin, Clock, FuncReg); // func is input, Frin is load debounce the clock, funcreg is output
		defparam functionreg.n = 8; // change this to 8
	dec2to4 decl (FuncReg[6:4], 1'b1, I); 		// reorder the bits to match direction ( use a 3:8 decoder)
	dec2to4 decX (FuncReg[3:2], 1'b1, Xreg); // still a 2:4 decoder
	dec2to4 decY (FuncReg[1:0], 1'b1, Y);		// still a 2:4 decoder

	// 22- 27 is the instruction
	// you get I, Y, Xreg


	// the control signals assereted in each step, TABLE 7.2
	// Rin = X means Set Rxin
	assign Extern = I[0] & T[1];
	assign Done = ((I[0] | I[1]) & T[1]) | ((I[2] | I[3]) & T[3]);
	assign Ain = (I[2] | I[3]) & T[1];
	assign Gin = (I[2] | I[3]) & T[2];
	assign Gout = (I[2] | I[3]) & T[3];
	assign AddSub = I[3];

	always@(I,T,Xreg,Y)		// add 4 and 5 to th 2 and 3
        for(k=0;k<4;k=k+1)
        begin
            Rin[k]=((I[0]|I[1])&T[1]& Xreg[k])|
                ((I[2]|I[3])&T[3]&Xreg[k]);
            Rout[k]=(I[1] & T[1] & Y[k])|((I[2]|I[3])&
                ((T[1]&Xreg[k])|(T[2]&Y[k])));
        end

    trin tri_ext(Data,Extern,BusWires);
    regn reg_0(BusWires,Rin[0],Clock,R0);
    regn reg_1(BusWires,Rin[1],Clock,R1);
    regn reg_2(BusWires,Rin[2],Clock,R2);
    regn reg_3(BusWires,Rin[3],Clock,R3);

    trin tri_0(R0,Rout[0],BusWires);
    trin tri_1(R1,Rout[1],BusWires);
    trin tri_2(R2,Rout[2],BusWires);
    trin tri_3(R3,Rout[3],BusWires);
    regn reg_A(BusWires,Ain,Clock,A);

	// this is the ALU / CPU we need add, sub, logical and, logical or, and get complement
	// make this a case
	// case (funcreg[6:4])
	//	3'b010: Sum = A + Bus wire
	// ... do the same for the other instructions
    always@(AddSub,A,BusWires)
		case (funcreg[6:4])
			3'b0010:
				Sum = A + BusWires
			3
        if(!AddSub)
            Sum = A+BusWires;
        else
            Sum = A-BusWires;

    regn reg_G(Sum,Gin,Clock,G);
    trin tri_G(G,Gout,BusWires);

 endmodule

 // notes

 //pin plan the data;
 // data is 8 bits
 // first 4 are the instruction
 // the next 2 is the X reg
 // the last 2 is the Y reg

 // function needs to b 4 bits
 // need to beef up the instrction decode with a 3:8 decoder
 // loical and and or pg 224