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nelson33

Untitled

Sep 22nd, 2023
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  1. `timescale 1ns/1ps
  2.  
  3. module Testbench;
  4.  
  5.     reg clk = 1'b0;
  6.     reg rst_n = 1'b0;
  7.     reg enable = 1'b1;
  8.     reg flip = 1'b0;
  9.     reg [3:0] max = 4'b0100;
  10.     reg [3:0] min = 4'b0000;
  11.    
  12.     wire direction;
  13.     wire [3:0] out;
  14.  
  15.     always #5 clk <= ~clk;
  16.  
  17.     // Instantiate the counter module
  18.     Parameterized_Ping_Pong_Counter uut (
  19.         .clk(clk),
  20.         .rst_n(rst_n),
  21.         .enable(enable),
  22.         .flip(flip),
  23.         .max(max),
  24.         .min(min),
  25.         .direction(direction),
  26.         .out(out)
  27.     );
  28.  
  29.     // Stimulus
  30.     initial begin
  31.         @(negedge clk) rst_n = 1'b1;
  32.  
  33.         #90;
  34.         @(negedge clk) begin
  35.             max = 4'b1010;
  36.             min = 4'b0011;
  37.         end
  38.  
  39.         #10
  40.         @(negedge clk) rst_n = 1'b0;
  41.         @(negedge clk) rst_n = 1'b1;
  42.  
  43.         #25
  44.         @(posedge clk) flip = 1'b1;
  45.         @(posedge clk) flip = 1'b0;
  46.  
  47.         #50
  48.         @(negedge clk) begin
  49.             max = 4'd15;
  50.             min = 4'd0;
  51.         end
  52.        
  53.         #50;
  54.         @(negedge clk) begin
  55.             enable = 1'b0;
  56.         end
  57.  
  58.         #20;
  59.         @(negedge clk) begin
  60.             enable = 1'b1;
  61.         end
  62.  
  63.         #20
  64.         flip = 1'b1;
  65.         @(negedge clk) flip = 1'b0;
  66.  
  67.         #20
  68.         flip = 1'b1;
  69.         @(negedge clk) flip = 1'b0;
  70.  
  71.         $stop;
  72.     end
  73.  
  74. endmodule
  75.  
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