`timescale 1ns/1ps

module Testbench;

    reg clk = 1'b0;
    reg rst_n = 1'b0;
    reg enable = 1'b1;
    reg flip = 1'b0;
    reg [3:0] max = 4'b0100;
    reg [3:0] min = 4'b0000;

    wire direction;
    wire [3:0] out;

    always #5 clk <= ~clk;

    // Instantiate the counter module
    Parameterized_Ping_Pong_Counter uut (
        .clk(clk),
        .rst_n(rst_n),
        .enable(enable),
        .flip(flip),
        .max(max),
        .min(min),
        .direction(direction),
        .out(out)
    );

    // Stimulus
    initial begin
        @(negedge clk) rst_n = 1'b1;

        #90;
        @(negedge clk) begin
            max = 4'b1010;
            min = 4'b0011;
        end

        #10
        @(negedge clk) rst_n = 1'b0;
        @(negedge clk) rst_n = 1'b1;

        #25
        @(posedge clk) flip = 1'b1;
        @(posedge clk) flip = 1'b0;

        #50
        @(negedge clk) begin
            max = 4'd15;
            min = 4'd0;
        end

        #50;
        @(negedge clk) begin
            enable = 1'b0;
        end

        #20;
        @(negedge clk) begin
            enable = 1'b1;
        end

        #20
        flip = 1'b1;
        @(negedge clk) flip = 1'b0;

        #20
        flip = 1'b1;
        @(negedge clk) flip = 1'b0;

        $stop;
    end

endmodule