`default_nettype none

module test (
    input  wire [63:0] in,
    output reg  out
);

    genvar i;

    wire [65:0] in_full = {2'b00, in};

    (* keep="true" *) reg  [11:0] lvl1_toomany;
    (* keep="true" *) reg  [11:0] lvl1_any;

    (* keep="true" *) reg  [ 3:0] lvl2_toomany;
    (* keep="true" *) reg  [ 1:0] lvl2_any;

    // Level 1
    generate
        for (i=0; i<11; i=i+1)
        begin
            always @(*)
            begin
                // At least one ?
                lvl1_any[i] = |in_full[6*i+:6];

                // Too many ?
                case (in_full[6*i+:6])
                    6'b000000: lvl1_toomany[i] = 1'b0;
                    6'b100000: lvl1_toomany[i] = 1'b0;
                    6'b010000: lvl1_toomany[i] = 1'b0;
                    6'b001000: lvl1_toomany[i] = 1'b0;
                    6'b000100: lvl1_toomany[i] = 1'b0;
                    6'b000010: lvl1_toomany[i] = 1'b0;
                    6'b000001: lvl1_toomany[i] = 1'b0;
                    default:   lvl1_toomany[i] = 1'b1;
                endcase
            end
        end
    endgenerate

    assign lvl1_toomany[11] = 1'b0;
    assign lvl1_any[11] = 1'b0;

    // Level 2
    generate
        for (i=0; i<2; i=i+1)
        begin
            always @(*)
            begin
                // At least one ?
                lvl2_any[i] = |lvl1_any[6*i+:6];

                // Too many ?
                case (lvl1_any[6*i+:6])
                    6'b000000: lvl2_toomany[i] = 1'b0;
                    6'b100000: lvl2_toomany[i] = 1'b0;
                    6'b010000: lvl2_toomany[i] = 1'b0;
                    6'b001000: lvl2_toomany[i] = 1'b0;
                    6'b000100: lvl2_toomany[i] = 1'b0;
                    6'b000010: lvl2_toomany[i] = 1'b0;
                    6'b000001: lvl2_toomany[i] = 1'b0;
                    default:   lvl2_toomany[i] = 1'b1;
                endcase

                lvl2_toomany[2+i] = |lvl1_toomany[6*i+:6];
            end
        end
    endgenerate

    // Level 3
    always @(*)
        out = (|lvl2_toomany || lvl2_any == 2'b11);

endmodule