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- file: pt.tcl
- ########################################### # Set the power analysis mode ###########################################
- set power_enable_analysis true; set power_analysis_mode averaged;
- ########################################### # read and link the gate level netlist ###########################################
- set search_path "../source db ./ ./result"
- set link_library "typical.db"
- set target_library "typical.db"
- read_verilog jnd_90s.v
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