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Dec 22nd, 2013
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  1. .extern entry
  2. .section .init
  3. .globl _start
  4. _start:
  5.     ldr pc, reset_handler
  6.     ldr pc, undefined_handler
  7.     ldr pc, swi_handler
  8.     ldr pc, pref_abort_handler
  9.     ldr pc, data_abort_handler
  10.     ldr pc, dummy_handler
  11.     ldr pc, irq_handler
  12.     ldr pc, fiq_handler
  13. reset_handler:      .word   reset
  14. undefined_handler:  .word   dummy
  15. swi_handler:        .word   dummy
  16. pref_abort_handler: .word   dummy
  17. data_abort_handler: .word   dummy
  18. dummy_handler:      .word   dummy
  19. irq_handler:        .word   kIrq
  20. fiq_handler:        .word   dummy
  21. reset:
  22.     mov r0, $0x0000
  23.     mov r1, $0x8000
  24.     ldmia r1!, {r2,r3,r4,r5,r6,r7,r8,r9}
  25.     stmia r0!, {r2,r3,r4,r5,r6,r7,r8,r9}
  26.         ldmia r1!, {r2,r3,r4,r5,r6,r7,r8,r9}
  27.         stmia r0!, {r2,r3,r4,r5,r6,r7,r8,r9}
  28.  
  29.     mov sp, $0x8000
  30.  
  31. @ set stack in irq mode
  32.     mrs r0, cpsr
  33.     bic r0, $0b11111111
  34.     orr r0, $0b11010010
  35.     msr cpsr, r0
  36.     mov sp, $0x4000
  37.  
  38. @ come back to svc mode
  39.     mrs r0, cpsr
  40.         bic r0, $0b11111111
  41.         orr r0, $0b11010011
  42.         msr cpsr, r0
  43.  
  44. @ fill .bss section with zeros
  45.     ldr r0, =_bss_start
  46.     ldr r1, =_bss_end
  47.     mov r2, $0
  48. loop:
  49.     cmp r0, r1
  50.     strlo r2, [r0], $4
  51.     blo loop
  52.  
  53.     bl entry
  54. dummy:
  55.     b dummy
  56. kIrq:
  57.         push {r0-r7, lr}
  58.         ldr r0, =0x20200040
  59.         ldr r1, =0x8068000  @ clear event statuses
  60.     str r1, [r0]
  61.     bl kIrqHandler
  62.         pop {r0-r7, lr}
  63.         subs pc, lr, $4
  64. .section .text
  65. .globl irqEnable
  66. irqEnable:
  67.     mrs r0, cpsr
  68.     bic r0, $0b10000000
  69.     msr cpsr, r0
  70.     mov pc, lr
  71. .globl irqDisable
  72. irqDisable:
  73.     mrs r0, cpsr
  74.     mvn r2, $0b10000000
  75.     orr r2, r2, r0
  76.     msr cpsr, r0
  77.     mov pc, lr
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