adder.sv

module adder(
    input logic c,
    input logic x1,
    input logic x2,
    input logic clr,
    output logic [15:0] q = 16'd0,
    output logic o = 0
);

logic x;

sum1 sum(
    .a(x1),
    .b(x2),
    .c(c),
    .d(o),
    .q(x),
    .o(o)
);

Sreg r(
    .c(c),
    .d(x),
    .clr(clr),
    .q(q)
);

endmodule