module m_hiftreg (clk, in, outp);
    input clk;
    input [0:0] in;
    output reg outp;

    reg [2:0] state;

    parameter st0 = 3'b000;
    parameter st4 = 3'b001;
    parameter st1 = 3'b010;
    parameter st2 = 3'b011;
    parameter st5 = 3'b100;
    parameter st3 = 3'b101;
    parameter st6 = 3'b110;
    parameter st7 = 3'b111;
    parameter dontcare = 3'bxxx;

    //TRANSITIONS//
    always @(posedge clk)
    begin
        case (state)
            st0:
                casez (in)
                    1'b0: state = st0;
                    1'b1: state = st4;
                    default: state = dontcare;
                endcase
            st4:
                casez (in)
                    1'b0: state = st2;
                    1'b1: state = st6;
                    default: state = dontcare;
                endcase
            st1:
                casez (in)
                    1'b0: state = st0;
                    1'b1: state = st4;
                    default: state = dontcare;
                endcase
            st2:
                casez (in)
                    1'b0: state = st1;
                    1'b1: state = st5;
                    default: state = dontcare;
                endcase
            st5:
                casez (in)
                    1'b0: state = st2;
                    1'b1: state = st6;
                    default: state = dontcare;
                endcase
            st3:
                casez (in)
                    1'b0: state = st1;
                    1'b1: state = st5;
                    default: state = dontcare;
                endcase
            st6:
                casez (in)
                    1'b0: state = st3;
                    1'b1: state = st7;
                    default: state = dontcare;
                endcase
            st7:
                casez (in)
                    1'b0: state = st3;
                    1'b1: state = st7;
                    default: state = dontcare;
                endcase
        default: state = dontcare;
        endcase
    end

    //OUTPUT//
    always @(posedge clk)
    begin
        case (state)
            st0:
                casez (in)
                    1'b0: outp <= 1'b0;
                    1'b1: outp <= 1'b0;
                    default: outp <= 1'b?;
                endcase
            st4:
                casez (in)
                    1'b0: outp <= 1'b0;
                    1'b1: outp <= 1'b0;
                    default: outp <= 1'b?;
                endcase
            st1:
                casez (in)
                    1'b0: outp <= 1'b1;
                    1'b1: outp <= 1'b1;
                    default: outp <= 1'b?;
                endcase
            st2:
                casez (in)
                    1'b0: outp <= 1'b0;
                    1'b1: outp <= 1'b0;
                    default: outp <= 1'b?;
                endcase
            st5:
                casez (in)
                    1'b0: outp <= 1'b1;
                    1'b1: outp <= 1'b1;
                    default: outp <= 1'b?;
                endcase
            st3:
                casez (in)
                    1'b0: outp <= 1'b1;
                    1'b1: outp <= 1'b1;
                    default: outp <= 1'b?;
                endcase
            st6:
                casez (in)
                    1'b0: outp <= 1'b0;
                    1'b1: outp <= 1'b0;
                    default: outp <= 1'b?;
                endcase
            st7:
                casez (in)
                    1'b0: outp <= 1'b1;
                    1'b1: outp <= 1'b1;
                    default: outp <= 1'b?;
                endcase
        default: outp <= 1'b?;
        endcase
    end
endmodule