PIL Counter 0017

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    16:06:59 03/03/2021
// Design Name:
// Module Name:    deviefive
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module deviefive
    (
    clk,
     CLK1kHz,
     CLK100Hz,
     CLKCPU
    );

input clk;
output CLK1kHz;
output CLK100Hz;
output CLKCPU;

reg [25:0]cnt = 26'd0;

assign CLKCPU = cnt[25];
assign CLK1kHz = cnt[14];
assign CLK100Hz = cnt[17];

    always @(posedge clk) begin
        cnt[0] <= ~cnt[0];
    end

    always @(posedge cnt[0]) begin
        cnt[1] <= ~cnt[1];
    end

    always @(posedge cnt[1]) begin
        cnt[2] <= ~cnt[2];
    end

    always @(posedge cnt[2]) begin
        cnt[3] <= ~cnt[3];
    end

    always @(posedge cnt[3]) begin
        cnt[4] <= ~cnt[4];
    end

    always @(posedge cnt[4]) begin
        cnt[5] <= ~cnt[5];
    end

    always @(posedge cnt[5]) begin
        cnt[6] <= ~cnt[6];
    end

    always @(posedge cnt[6]) begin
        cnt[7] <= ~cnt[7];
    end

    always @(posedge cnt[7]) begin
        cnt[8] <= ~cnt[8];
    end

    always @(posedge cnt[8]) begin
        cnt[9] <= ~cnt[9];
    end

    always @(posedge cnt[9]) begin
        cnt[10] <= ~cnt[10];
    end

    always @(posedge cnt[10]) begin
        cnt[11] <= ~cnt[11];
    end

    always @(posedge cnt[11]) begin
        cnt[12] <= ~cnt[12];
    end

    always @(posedge cnt[12]) begin
        cnt[13] <= ~cnt[13];
    end

    always @(posedge cnt[13]) begin
        cnt[14] <= ~cnt[14]; // Unb.
    end

    always @(posedge cnt[14]) begin
        cnt[15] <= ~cnt[15];
    end

    always @(posedge cnt[15]) begin
        cnt[16] <= ~cnt[16];
    end

    always @(posedge cnt[16]) begin
        cnt[17] <= ~cnt[17];
    end

    always @(posedge cnt[17]) begin
        cnt[18] <= ~cnt[18];
    end

    always @(posedge cnt[18]) begin
        cnt[19] <= ~cnt[19];
    end

    always @(posedge cnt[19]) begin
        cnt[20] <= ~cnt[20];
    end

    always @(posedge cnt[20]) begin
        cnt[21] <= ~cnt[21];
    end

        always @(posedge cnt[21]) begin
        cnt[22] <= ~cnt[22];
    end

    always @(posedge cnt[22]) begin
        cnt[23] <= ~cnt[23];
    end

    always @(posedge cnt[23]) begin
        cnt[24] <= ~cnt[24];
    end

    always @(posedge cnt[24]) begin
        cnt[25] <= ~cnt[25];
    end

endmodule