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  1. #cpudef "CPU_65C02_CS"
  2. {
  3. #bits 8
  4.  
  5. ;------------------------------------------------------------------------------ (++ means new Instruction, +* means new Addressing Mode)
  6. ; Add with Carry
  7. ADC #{src} -> 0x69[7:0] @ src[7:0]
  8. ADC {src} -> {assert({src} <= 0xFF), 0x65[7:0] @ src[7:0]}
  9. ADC {src},X -> {assert({src} <= 0xFF), 0x75[7:0] @ src[7:0]}
  10. ADC {src} -> {assert({src} > 0xFF), 0x6D[7:0] @ src[7:0] @ src[15:8]}
  11. ADC {src},X -> {assert({src} > 0xFF), 0x7D[7:0] @ src[7:0] @ src[15:8]}
  12. ADC {src},Y -> {assert({src} > 0xFF), 0x79[7:0] @ src[7:0] @ src[15:8]}
  13. ADC ({src},X) -> 0x61[7:0] @ src[7:0]
  14. ADC ({src}),Y -> 0x71[7:0] @ src[7:0]
  15. ADC ({src}) -> 0x72[7:0] @ src[7:0] ; +*
  16.  
  17. ;------------------------------------------------------------------------------
  18. ; Logic AND
  19. AND #{src} -> 0x29[7:0] @ src[7:0]
  20. AND {src} -> {assert({src} <= 0xFF), 0x25[7:0] @ src[7:0]}
  21. AND {src},X -> {assert({src} <= 0xFF), 0x35[7:0] @ src[7:0]}
  22. AND {src} -> {assert({src} > 0xFF), 0x2D[7:0] @ src[7:0] @ src[15:8]}
  23. AND {src},X -> {assert({src} > 0xFF), 0x3D[7:0] @ src[7:0] @ src[15:8]}
  24. AND {src},Y -> {assert({src} > 0xFF), 0x39[7:0] @ src[7:0] @ src[15:8]}
  25. AND ({src},X) -> 0x21[7:0] @ src[7:0]
  26. AND ({src}),Y -> 0x31[7:0] @ src[7:0]
  27. AND ({src}) -> 0x32[7:0] @ src[7:0] ; +*
  28.  
  29. ;------------------------------------------------------------------------------
  30. ; Arithmetic Shift Left
  31. ASL A -> 0x0A[7:0]
  32. ASL {src} -> {assert({src} <= 0xFF), 0x07[7:0] @ src[7:0]}
  33. ASL {src},X -> {assert({src} <= 0xFF), 0x16[7:0] @ src[7:0]}
  34. ASL {src} -> {assert({src} > 0xFF), 0x0E[7:0] @ src[7:0] @ src[15:8]}
  35. ASL {src},X -> {assert({src} > 0xFF), 0x1E[7:0] @ src[7:0] @ src[15:8]}
  36.  
  37. ;------------------------------------------------------------------------------
  38. ; Branch Always ++
  39. BRA {src} -> 0x80[7:0] @ (src - (pc - 2))[7:0]
  40.  
  41. ;------------------------------------------------------------------------------
  42. ; Branch on Bit Clear/Reset ++
  43. BBC0 {src},{src1} -> 0x0F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  44. BBC1 {src},{src1} -> 0x1F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  45. BBC2 {src},{src1} -> 0x2F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  46. BBC3 {src},{src1} -> 0x3F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  47. BBC4 {src},{src1} -> 0x4F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  48. BBC5 {src},{src1} -> 0x5F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  49. BBC6 {src},{src1} -> 0x6F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  50. BBC7 {src},{src1} -> 0x7F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  51. BBR0 {src},{src1} -> 0x0F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  52. BBR1 {src},{src1} -> 0x1F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  53. BBR2 {src},{src1} -> 0x2F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  54. BBR3 {src},{src1} -> 0x3F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  55. BBR4 {src},{src1} -> 0x4F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  56. BBR5 {src},{src1} -> 0x5F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  57. BBR6 {src},{src1} -> 0x6F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  58. BBR7 {src},{src1} -> 0x7F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  59.  
  60. ;------------------------------------------------------------------------------
  61. ; Branch on Bit Set ++
  62. BBS0 {src},{src1} -> 0x8F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  63. BBS1 {src},{src1} -> 0x9F[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  64. BBS2 {src},{src1} -> 0xAF[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  65. BBS3 {src},{src1} -> 0xBF[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  66. BBS4 {src},{src1} -> 0xCF[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  67. BBS5 {src},{src1} -> 0xDF[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  68. BBS6 {src},{src1} -> 0xEF[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  69. BBS7 {src},{src1} -> 0xFF[7:0] @ src[7:0] @ ({src1} - pc)[7:0]
  70.  
  71. ;------------------------------------------------------------------------------
  72. ; Branch on Carry Clear
  73. BCC {src} -> 0x90[7:0] @ (src - (pc - 2))[7:0]
  74.  
  75. ;------------------------------------------------------------------------------
  76. ; Branch on Carry Set
  77. BCS {src} -> 0xB0[7:0] @ (src - (pc - 2))[7:0]
  78.  
  79. ;------------------------------------------------------------------------------
  80. ; Branch on Equal (Zero Set)
  81. BEQ {src} -> 0xF0[7:0] @ (src - (pc - 2))[7:0]
  82.  
  83. ;------------------------------------------------------------------------------
  84. ; Bit Test
  85. BIT #{src} -> 0x89[7:0] @ src[7:0] ; +*
  86. BIT {src} -> {assert({src} <= 0xFF), 0x24[7:0] @ src[7:0]}
  87. BIT {src},X -> {assert({src} <= 0xFF), 0x34[7:0] @ src[7:0]} ; +*
  88. BIT {src} -> {assert({src} > 0xFF), 0x2C[7:0] @ src[7:0] @ src[15:8]}
  89. BIT {src},X -> {assert({src} > 0xFF), 0x3C[7:0] @ src[7:0] @ src[15:8]} ; +*
  90.  
  91. ;------------------------------------------------------------------------------
  92. ; Branch on Minus (Negative Set)
  93. BMI {src} -> 0x30[7:0] @ (src - (pc - 2))[7:0]
  94.  
  95. ;------------------------------------------------------------------------------
  96. ; Branch on Not Equal (Zero Clear)
  97. BNE {src} -> 0xD0[7:0] @ (src - (pc - 2))[7:0]
  98.  
  99. ;------------------------------------------------------------------------------
  100. ; Branch on Plus (Negative Clear)
  101. BPL {src} -> 0x10[7:0] @ (src - (pc - 2))[7:0]
  102.  
  103. ;------------------------------------------------------------------------------
  104. ; Break (Interrupt)
  105. BRK -> 0x00[7:0]
  106. INT -> 0x00[7:0]
  107.  
  108. ;------------------------------------------------------------------------------
  109. ; Branch on Overflow Clear
  110. BVC {src} -> 0x50[7:0] @ (src - (pc - 2))[7:0]
  111.  
  112. ;------------------------------------------------------------------------------
  113. ; Branch on Overflow Set
  114. BVS {src} -> 0x70[7:0] @ (src - (pc - 2))[7:0]
  115.  
  116. ;------------------------------------------------------------------------------
  117. ; Clear Carry
  118. CLC -> 0x18[7:0]
  119.  
  120. ;------------------------------------------------------------------------------
  121. ; Clear Decimal
  122. CLD -> 0xD8[7:0]
  123.  
  124. ;------------------------------------------------------------------------------
  125. ; Clear Interrupt Disable
  126. CLI -> 0x58[7:0]
  127.  
  128. ;------------------------------------------------------------------------------
  129. ; Clear Overflow
  130. CLV -> 0xB8[7:0]
  131.  
  132. ;------------------------------------------------------------------------------
  133. ; Compare with Accumulator
  134. CMP #{src} -> 0xC9[7:0] @ src[7:0]
  135. CMP {src} -> {assert({src} <= 0xFF), 0xC5[7:0] @ src[7:0]}
  136. CMP {src},X -> {assert({src} <= 0xFF), 0xD5[7:0] @ src[7:0]}
  137. CMP {src} -> {assert({src} > 0xFF), 0xCD[7:0] @ src[7:0] @ src[15:8]}
  138. CMP {src},X -> {assert({src} > 0xFF), 0xDD[7:0] @ src[7:0] @ src[15:8]}
  139. CMP {src},Y -> {assert({src} > 0xFF), 0xD9[7:0] @ src[7:0] @ src[15:8]}
  140. CMP ({src},X) -> 0xC1[7:0] @ src[7:0]
  141. CMP ({src}),Y -> 0xD1[7:0] @ src[7:0]
  142. CMP ({src}) -> 0xD2[7:0] @ src[7:0] ; +*
  143.  
  144. ;------------------------------------------------------------------------------
  145. ; Compare with X
  146. CPX #{src} -> 0xE0[7:0] @ src[7:0]
  147. CPX {src} -> {assert({src} <= 0xFF), 0xE4[7:0] @ src[7:0]}
  148. CPX {src} -> {assert({src} > 0xFF), 0xEC[7:0] @ src[7:0] @ src[15:8]}
  149.  
  150. ;------------------------------------------------------------------------------
  151. ; Compare with Y
  152. CPY #{src} -> 0xC0[7:0] @ src[7:0]
  153. CPY {src} -> {assert({src} <= 0xFF), 0xC4[7:0] @ src[7:0]}
  154. CPY {src} -> {assert({src} > 0xFF), 0xCC[7:0] @ src[7:0] @ src[15:8]}
  155.  
  156. ;------------------------------------------------------------------------------
  157. ; Decrement
  158. DEC A -> 0x1A[7:0] ; +*
  159. DEA -> 0x1A[7:0] ; +*
  160. DEC {src} -> {assert({src} <= 0xFF), 0xC6[7:0] @ src[7:0]}
  161. DEC {src},X -> {assert({src} <= 0xFF), 0xD6[7:0] @ src[7:0]}
  162. DEC {src} -> {assert({src} > 0xFF), 0xCE[7:0] @ src[7:0] @ src[15:8]}
  163. DEC {src},X -> {assert({src} > 0xFF), 0xDE[7:0] @ src[7:0] @ src[15:8]}
  164.  
  165. ;------------------------------------------------------------------------------
  166. ; Decrement X
  167. DEX -> 0xCA[7:0]
  168.  
  169. ;------------------------------------------------------------------------------
  170. ; Decrement Y
  171. DEY -> 0x88[7:0]
  172.  
  173. ;------------------------------------------------------------------------------
  174. ; Logic XOR
  175. EOR #{src} -> 0x49[7:0] @ src[7:0]
  176. EOR {src} -> {assert({src} <= 0xFF), 0x45[7:0] @ src[7:0]}
  177. EOR {src},X -> {assert({src} <= 0xFF), 0x55[7:0] @ src[7:0]}
  178. EOR {src} -> {assert({src} > 0xFF), 0x4D[7:0] @ src[7:0] @ src[15:8]}
  179. EOR {src},X -> {assert({src} > 0xFF), 0x5D[7:0] @ src[7:0] @ src[15:8]}
  180. EOR {src},Y -> {assert({src} > 0xFF), 0x59[7:0] @ src[7:0] @ src[15:8]}
  181. EOR ({src},X) -> 0x41[7:0] @ src[7:0]
  182. EOR ({src}),Y -> 0x51[7:0] @ src[7:0]
  183. EOR ({src}) -> 0x52[7:0] @ src[7:0] ; +*
  184.  
  185. ;------------------------------------------------------------------------------
  186. ; Increment
  187. INC A -> 0x3A[7:0] ; +*
  188. INA -> 0x3A[7:0] ; +*
  189. INC {src} -> {assert({src} <= 0xFF), 0xE6[7:0] @ src[7:0]}
  190. INC {src},X -> {assert({src} <= 0xFF), 0xF6[7:0] @ src[7:0]}
  191. INC {src} -> {assert({src} > 0xFF), 0xEE[7:0] @ src[7:0] @ src[15:8]}
  192. INC {src},X -> {assert({src} > 0xFF), 0xFE[7:0] @ src[7:0] @ src[15:8]}
  193.  
  194. ;------------------------------------------------------------------------------
  195. ; Increment X
  196. INX -> 0xE8[7:0]
  197.  
  198. ;------------------------------------------------------------------------------
  199. ; Increment Y
  200. INY -> 0xC8[7:0]
  201.  
  202. ;------------------------------------------------------------------------------
  203. ; Jump
  204. JMP {src} -> 0x4C[7:0] @ src[7:0] @ src[15:8]
  205. JMP ({src}) -> 0x6C[7:0] @ src[7:0] @ src[15:8]
  206. JMP ({src},X) -> 0x7C[7:0] @ src[7:0] @ src[15:8]
  207.  
  208. ;------------------------------------------------------------------------------
  209. ; Jump Subroutine
  210. JSR {src} -> 0x20[7:0] @ src[7:0] @ src[15:8]
  211.  
  212. ;------------------------------------------------------------------------------
  213. ; Load Accumulator
  214. LDA #{src} -> 0xA9[7:0] @ src[7:0]
  215. LDA {src} -> {assert({src} <= 0xFF), 0xA5[7:0] @ src[7:0]}
  216. LDA {src},X -> {assert({src} <= 0xFF), 0xB5[7:0] @ src[7:0]}
  217. LDA {src} -> {assert({src} > 0xFF), 0xAD[7:0] @ src[7:0] @ src[15:8]}
  218. LDA {src},X -> {assert({src} > 0xFF), 0xBD[7:0] @ src[7:0] @ src[15:8]}
  219. LDA {src},Y -> {assert({src} > 0xFF), 0xB9[7:0] @ src[7:0] @ src[15:8]}
  220. LDA ({src},X) -> 0xA1[7:0] @ src[7:0]
  221. LDA ({src}),Y -> 0xB1[7:0] @ src[7:0]
  222. LDA ({src}) -> 0xB2[7:0] @ src[7:0] ; +*
  223.  
  224. ;------------------------------------------------------------------------------
  225. ; Load X
  226. LDX #{src} -> 0xA2[7:0] @ src[7:0]
  227. LDX {src} -> {assert({src} <= 0xFF), 0xA6[7:0] @ src[7:0]}
  228. LDX {src},Y -> {assert({src} <= 0xFF), 0xB6[7:0] @ src[7:0]}
  229. LDX {src} -> {assert({src} > 0xFF), 0xAE[7:0] @ src[7:0] @ src[15:8]}
  230. LDX {src},Y -> {assert({src} > 0xFF), 0xBE[7:0] @ src[7:0] @ src[15:8]}
  231.  
  232. ;------------------------------------------------------------------------------
  233. ; Load Y
  234. LDY #{src} -> 0xA0[7:0] @ src[7:0]
  235. LDY {src} -> {assert({src} <= 0xFF), 0xA4[7:0] @ src[7:0]}
  236. LDY {src},X -> {assert({src} <= 0xFF), 0xB4[7:0] @ src[7:0]}
  237. LDY {src} -> {assert({src} > 0xFF), 0xAC[7:0] @ src[7:0] @ src[15:8]}
  238. LDY {src},X -> {assert({src} > 0xFF), 0xBE[7:0] @ src[7:0] @ src[15:8]}
  239.  
  240. ;------------------------------------------------------------------------------
  241. ; Logical Shift Right
  242. LSR A -> 0x4A[7:0]
  243. LSR {src} -> {assert({src} <= 0xFF), 0x46[7:0] @ src[7:0]}
  244. LSR {src},X -> {assert({src} <= 0xFF), 0x56[7:0] @ src[7:0]}
  245. LSR {src} -> {assert({src} > 0xFF), 0x4E[7:0] @ src[7:0] @ src[15:8]}
  246. LSR {src},X -> {assert({src} > 0xFF), 0x5E[7:0] @ src[7:0] @ src[15:8]}
  247.  
  248. ;------------------------------------------------------------------------------
  249. ; No Operation
  250. NOP -> 0xEA[7:0]
  251.  
  252. ;------------------------------------------------------------------------------
  253. ; Logic OR
  254. ORA #{src} -> 0x09[7:0] @ src[7:0]
  255. ORA {src} -> {assert({src} <= 0xFF), 0x06[7:0] @ src[7:0]}
  256. ORA {src},X -> {assert({src} <= 0xFF), 0x15[7:0] @ src[7:0]}
  257. ORA {src} -> {assert({src} > 0xFF), 0x0D[7:0] @ src[7:0] @ src[15:8]}
  258. ORA {src},X -> {assert({src} > 0xFF), 0x1D[7:0] @ src[7:0] @ src[15:8]}
  259. ORA {src},Y -> {assert({src} > 0xFF), 0x19[7:0] @ src[7:0] @ src[15:8]}
  260. ORA ({src},X) -> 0x01[7:0] @ src[7:0]
  261. ORA ({src}),Y -> 0x11[7:0] @ src[7:0]
  262. ORA ({src}) -> 0x12[7:0] @ src[7:0] ; +*
  263.  
  264. ;------------------------------------------------------------------------------
  265. ; Push Accumulator
  266. PHA -> 0x48[7:0]
  267.  
  268. ;------------------------------------------------------------------------------
  269. ; Push Processor Status
  270. PHP -> 0x08[7:0]
  271.  
  272. ;------------------------------------------------------------------------------
  273. ; Push X Register ++
  274. PHX -> 0xDA[7:0]
  275.  
  276. ;------------------------------------------------------------------------------
  277. ; Push Y Register ++
  278. PHY -> 0x5A[7:0]
  279.  
  280. ;------------------------------------------------------------------------------
  281. ; Pull Accumulator
  282. PLA -> 0x68[7:0]
  283.  
  284. ;------------------------------------------------------------------------------
  285. ; Pull Processor Status
  286. PLP -> 0x28[7:0]
  287.  
  288. ;------------------------------------------------------------------------------
  289. ; Pull X Register ++
  290. PLX -> 0xFA[7:0]
  291.  
  292. ;------------------------------------------------------------------------------
  293. ; Pull Y Register ++
  294. PLY -> 0x7A[7:0]
  295.  
  296. ;------------------------------------------------------------------------------
  297. ; Reset Memory Bit ++
  298. RMB0 {src} -> 0x07[7:0] @ src[7:0]
  299. RMB1 {src} -> 0x17[7:0] @ src[7:0]
  300. RMB2 {src} -> 0x27[7:0] @ src[7:0]
  301. RMB3 {src} -> 0x37[7:0] @ src[7:0]
  302. RMB4 {src} -> 0x47[7:0] @ src[7:0]
  303. RMB5 {src} -> 0x57[7:0] @ src[7:0]
  304. RMB6 {src} -> 0x67[7:0] @ src[7:0]
  305. RMB7 {src} -> 0x77[7:0] @ src[7:0]
  306.  
  307. ;------------------------------------------------------------------------------
  308. ; Rotate Left
  309. ROL A -> 0x2A[7:0]
  310. ROL {src} -> {assert({src} <= 0xFF), 0x26[7:0] @ src[7:0]}
  311. ROL {src},X -> {assert({src} <= 0xFF), 0x36[7:0] @ src[7:0]}
  312. ROL {src} -> {assert({src} > 0xFF), 0x2E[7:0] @ src[7:0] @ src[15:8]}
  313. ROL {src},X -> {assert({src} > 0xFF), 0x3E[7:0] @ src[7:0] @ src[15:8]}
  314.  
  315. ;------------------------------------------------------------------------------
  316. ; Rotate Right
  317. ROR A -> 0x6A[7:0]
  318. ROR {src} -> {assert({src} <= 0xFF), 0x66[7:0] @ src[7:0]}
  319. ROR {src},X -> {assert({src} <= 0xFF), 0x76[7:0] @ src[7:0]}
  320. ROR {src} -> {assert({src} > 0xFF), 0x6E[7:0] @ src[7:0] @ src[15:8]}
  321. ROR {src},X -> {assert({src} > 0xFF), 0x7E[7:0] @ src[7:0] @ src[15:8]}
  322.  
  323. ;------------------------------------------------------------------------------
  324. ; Return from Interrupt
  325. RTI -> 0x40[7:0]
  326.  
  327. ;------------------------------------------------------------------------------
  328. ; Return from Subroutine
  329. RTS -> 0x60[7:0]
  330.  
  331. ;------------------------------------------------------------------------------
  332. ; Subtract with Carry
  333. SBC #{src} -> 0xE9[7:0] @ src[7:0]
  334. SBC {src} -> {assert({src} <= 0xFF), 0xE5[7:0] @ src[7:0]}
  335. SBC {src},X -> {assert({src} <= 0xFF), 0xF5[7:0] @ src[7:0]}
  336. SBC {src} -> {assert({src} > 0xFF), 0xED[7:0] @ src[7:0] @ src[15:8]}
  337. SBC {src},X -> {assert({src} > 0xFF), 0xFD[7:0] @ src[7:0] @ src[15:8]}
  338. SBC {src},Y -> {assert({src} > 0xFF), 0xF9[7:0] @ src[7:0] @ src[15:8]}
  339. SBC ({src},X) -> 0xE1[7:0] @ src[7:0]
  340. SBC ({src}),Y -> 0xF1[7:0] @ src[7:0]
  341. SBC ({src}) -> 0xF2[7:0] @ src[7:0] ; +*
  342.  
  343. ;------------------------------------------------------------------------------
  344. ; Set Carry
  345. SEC -> 0x38[7:0]
  346.  
  347. ;------------------------------------------------------------------------------
  348. ; Set Decimal
  349. SED -> 0xF8[7:0]
  350.  
  351. ;------------------------------------------------------------------------------
  352. ; Set Interrupt Disable
  353. SEI -> 0x78[7:0]
  354.  
  355. ;------------------------------------------------------------------------------
  356. ; Set Memory Bit ++
  357. SMB0 {src} -> 0x87[7:0] @ src[7:0]
  358. SMB1 {src} -> 0x97[7:0] @ src[7:0]
  359. SMB2 {src} -> 0xA7[7:0] @ src[7:0]
  360. SMB3 {src} -> 0xB7[7:0] @ src[7:0]
  361. SMB4 {src} -> 0xC7[7:0] @ src[7:0]
  362. SMB5 {src} -> 0xD7[7:0] @ src[7:0]
  363. SMB6 {src} -> 0xE7[7:0] @ src[7:0]
  364. SMB7 {src} -> 0xF7[7:0] @ src[7:0]
  365.  
  366. ;------------------------------------------------------------------------------
  367. ; Store Accumulator
  368. STA {src} -> {assert({src} <= 0xFF), 0x85[7:0] @ src[7:0]}
  369. STA {src},X -> {assert({src} <= 0xFF), 0x95[7:0] @ src[7:0]}
  370. STA {src} -> {assert({src} > 0xFF), 0x8D[7:0] @ src[7:0] @ src[15:8]}
  371. STA {src},X -> {assert({src} > 0xFF), 0x9D[7:0] @ src[7:0] @ src[15:8]}
  372. STA {src},Y -> {assert({src} > 0xFF), 0x99[7:0] @ src[7:0] @ src[15:8]}
  373. STA ({src},X) -> 0x81[7:0] @ src[7:0]
  374. STA ({src}),Y -> 0x91[7:0] @ src[7:0]
  375. STA ({src}) -> 0x92[7:0] @ src[7:0] ; +*
  376.  
  377. ;------------------------------------------------------------------------------
  378. ; Stop Processor (Halt) ++
  379. STP -> 0xDB[7:0]
  380. HLT -> 0xDB[7:0]
  381.  
  382. ;------------------------------------------------------------------------------
  383. ; Store X
  384. STX {src} -> {assert({src} <= 0xFF), 0x86[7:0] @ src[7:0]}
  385. STX {src},Y -> {assert({src} <= 0xFF), 0x96[7:0] @ src[7:0]}
  386. STX {src} -> {assert({src} > 0xFF), 0x8E[7:0] @ src[7:0] @ src[15:8]}
  387.  
  388. ;------------------------------------------------------------------------------
  389. ; Store Y
  390. STY {src} -> {assert({src} <= 0xFF), 0x84[7:0] @ src[7:0]}
  391. STY {src},X -> {assert({src} <= 0xFF), 0x94[7:0] @ src[7:0]}
  392. STY {src} -> {assert({src} > 0xFF), 0x8C[7:0] @ src[7:0] @ src[15:8]}
  393.  
  394. ;------------------------------------------------------------------------------
  395. ; Store Zero in Memory ++
  396. STZ {src} -> {assert({src} <= 0xFF), 0x64[7:0] @ src[7:0]}
  397. STZ {src},X -> {assert({src} <= 0xFF), 0x74[7:0] @ src[7:0]}
  398. STZ {src} -> {assert({src} > 0xFF), 0x9C[7:0] @ src[7:0] @ src[15:8]}
  399. STZ {src},X -> {assert({src} > 0xFF), 0x9E[7:0] @ src[7:0] @ src[15:8]}
  400.  
  401. ;------------------------------------------------------------------------------
  402. ; Transfer Accumulator to X
  403. TAX -> 0xAA[7:0]
  404.  
  405. ;------------------------------------------------------------------------------
  406. ; Transfer Accumulator to Y
  407. TAY -> 0xA8[7:0]
  408.  
  409. ;------------------------------------------------------------------------------
  410. ; Test and Reset memory Bit ++
  411. TRB {src} -> {assert({src} <= 0xFF), 0x14[7:0] @ src[7:0]}
  412. TRB {src} -> {assert({src} > 0xFF), 0x1C[7:0] @ src[7:0] @ src[15:8]}
  413.  
  414. ;------------------------------------------------------------------------------
  415. ; Test and Set memory Bit ++
  416. TSB {src} -> {assert({src} <= 0xFF), 0x04[7:0] @ src[7:0]}
  417. TSB {src} -> {assert({src} > 0xFF), 0x0C[7:0] @ src[7:0] @ src[15:8]}
  418.  
  419. ;------------------------------------------------------------------------------
  420. ; Transfer Stack Pointer to X
  421. TSX -> 0xBA[7:0]
  422.  
  423. ;------------------------------------------------------------------------------
  424. ; Transfer X to Accumulator
  425. TXA -> 0x8A[7:0]
  426.  
  427. ;------------------------------------------------------------------------------
  428. ; Transfer X to Stack Pointer
  429. TXS -> 0x9A[7:0]
  430.  
  431. ;------------------------------------------------------------------------------
  432. ; Transfer Y to Accumulator
  433. TYA -> 0x98[7:0]
  434. ;------------------------------------------------------------------------------
  435. ; Wait for Interrupt ++
  436. WAI -> 0xCB[7:0]
  437.  
  438. }
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