API tools faq
paste
Advertisement
Guest User

Untitled

a guest
Jul 23rd, 2017
550
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 398.58 KB | None | 0 0
raw download clone embed print report
  1. cat target/linux/aruba-2.6/patches-2.6.30/000-aruba.patch
  2. --- a/arch/mips/Kconfig
  3. +++ b/arch/mips/Kconfig
  4. @@ -115,6 +115,16 @@
  5.  
  6. otherwise choose R3000.
  7.  
  8. +config MACH_ARUBA
  9. + bool "Support for the ARUBA product line"
  10. + select DMA_NONCOHERENT
  11. + select CPU_HAS_PREFETCH
  12. + select HW_HAS_PCI
  13. + select SWAP_IO_SPACE
  14. + select SYS_SUPPORTS_32BIT_KERNEL
  15. + select SYS_HAS_CPU_MIPS32_R1
  16. + select SYS_SUPPORTS_BIG_ENDIAN
  17. +
  18. config MACH_JAZZ
  19. bool "Jazz family of machines"
  20. select ARC
  21. --- a/arch/mips/Makefile
  22. +++ b/arch/mips/Makefile
  23. @@ -172,7 +172,10 @@
  24. #
  25. # Board-dependent options and extra files
  26. #
  27. -
  28. +# Aruba
  29. +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
  30. +cflags-$(CONFIG_MACH_ARUBA) += -I$(srctree)/arch/mips/include/asm/mach-aruba
  31. +load-$(CONFIG_MACH_ARUBA) += 0x80100000
  32. #
  33. # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
  34. #
  35. diff -Nur linux-2.6.21.5-pristine/arch/mips/aruba/Makefile linux-2.6.21.5/arch/mips/aruba/Makefile
  36. --- linux-2.6.21.5-pristine/arch/mips/aruba/Makefile 1969-12-31 19:00:00.000000000 -0500
  37. +++ linux-2.6.21.5/arch/mips/aruba/Makefile 2007-09-20 00:16:52.000000000 -0400
  38. @@ -0,0 +1,49 @@
  39. +###############################################################################
  40. +#
  41. +# BRIEF MODULE DESCRIPTION
  42. +# Makefile for IDT EB434 BSP
  43. +#
  44. +# Copyright 2004 IDT Inc. (rischelp@idt.com)
  45. +#
  46. +# This program is free software; you can redistribute it and/or modify it
  47. +# under the terms of the GNU General Public License as published by the
  48. +# Free Software Foundation; either version 2 of the License, or (at your
  49. +# option) any later version.
  50. +#
  51. +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  52. +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  53. +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  54. +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  55. +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  56. +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  57. +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  58. +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59. +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  60. +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61. +#
  62. +# You should have received a copy of the GNU General Public License along
  63. +# with this program; if not, write to the Free Software Foundation, Inc.,
  64. +# 675 Mass Ave, Cambridge, MA 02139, USA.
  65. +#
  66. +#
  67. +###############################################################################
  68. +# May 2004 rkt, neb
  69. +#
  70. +# Initial Release
  71. +#
  72. +#
  73. +#
  74. +###############################################################################
  75. +
  76. +
  77. +# .S.s:
  78. +# $(CPP) $(CFLAGS) $< -o $*.s
  79. +# .S.o:
  80. +# $(CC) $(CFLAGS) -c $< -o $*.o
  81. +
  82. +obj-y := prom.o setup.o irq.o time.o flash_lock.o
  83. +obj-$(CONFIG_SERIAL_8250) += serial.o
  84. +
  85. +subdir-y += nvram
  86. +obj-y += nvram/built-in.o
  87. +
  88. diff -Nur linux-2.6.21.5-pristine/arch/mips/aruba/nvram/Makefile linux-2.6.21.5/arch/mips/aruba/nvram/Makefile
  89. --- linux-2.6.21.5-pristine/arch/mips/aruba/nvram/Makefile 1969-12-31 19:00:00.000000000 -0500
  90. +++ linux-2.6.21.5/arch/mips/aruba/nvram/Makefile 2007-09-20 00:16:52.000000000 -0400
  91. @@ -0,0 +1,46 @@
  92. +###############################################################################
  93. +#
  94. +# BRIEF MODULE DESCRIPTION
  95. +# Makefile for IDT EB434 nvram access routines
  96. +#
  97. +# Copyright 2004 IDT Inc. (rischelp@idt.com)
  98. +#
  99. +# This program is free software; you can redistribute it and/or modify it
  100. +# under the terms of the GNU General Public License as published by the
  101. +# Free Software Foundation; either version 2 of the License, or (at your
  102. +# option) any later version.
  103. +#
  104. +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  105. +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  106. +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  107. +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  108. +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  109. +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  110. +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  111. +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  112. +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  113. +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  114. +#
  115. +# You should have received a copy of the GNU General Public License along
  116. +# with this program; if not, write to the Free Software Foundation, Inc.,
  117. +# 675 Mass Ave, Cambridge, MA 02139, USA.
  118. +#
  119. +#
  120. +###############################################################################
  121. +# May 2004 rkt, neb
  122. +#
  123. +# Initial Release
  124. +#
  125. +#
  126. +#
  127. +###############################################################################
  128. +
  129. +obj-y := nvram434.o
  130. +obj-m := $(O_TARGET)
  131. +
  132. +
  133. +
  134. +
  135. +
  136. +
  137. +
  138. diff -Nur linux-2.6.21.5-pristine/arch/mips/aruba/nvram/nvram434.c linux-2.6.21.5/arch/mips/aruba/nvram/nvram434.c
  139. --- linux-2.6.21.5-pristine/arch/mips/aruba/nvram/nvram434.c 1969-12-31 19:00:00.000000000 -0500
  140. +++ linux-2.6.21.5/arch/mips/aruba/nvram/nvram434.c 2007-09-20 00:16:52.000000000 -0400
  141. @@ -0,0 +1,392 @@
  142. +/**************************************************************************
  143. + *
  144. + * BRIEF MODULE DESCRIPTION
  145. + * nvram interface routines.
  146. + *
  147. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  148. + *
  149. + * This program is free software; you can redistribute it and/or modify it
  150. + * under the terms of the GNU General Public License as published by the
  151. + * Free Software Foundation; either version 2 of the License, or (at your
  152. + * option) any later version.
  153. + *
  154. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  155. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  156. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  157. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  158. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  159. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  160. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  161. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  162. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  163. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  164. + *
  165. + * You should have received a copy of the GNU General Public License along
  166. + * with this program; if not, write to the Free Software Foundation, Inc.,
  167. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  168. + *
  169. + *
  170. + **************************************************************************
  171. + * May 2004 rkt, neb
  172. + *
  173. + * Initial Release
  174. + *
  175. + *
  176. + *
  177. + **************************************************************************
  178. + */
  179. +
  180. +#include <linux/ctype.h>
  181. +#include <linux/string.h>
  182. +#include <linux/kernel.h>
  183. +
  184. +//#include <asm/ds1553rtc.h>
  185. +#include "nvram434.h"
  186. +#define NVRAM_BASE 0xbfff8000
  187. +
  188. +extern void setenv (char *e, char *v, int rewrite);
  189. +extern void unsetenv (char *e);
  190. +extern void mapenv (int (*func)(char *, char *));
  191. +extern char *getenv (char *s);
  192. +extern void purgeenv(void);
  193. +
  194. +static void nvram_initenv(void);
  195. +
  196. +static unsigned char
  197. +nvram_getbyte(int offs)
  198. +{
  199. + return(*((unsigned char*)(NVRAM_BASE + offs)));
  200. +}
  201. +
  202. +static void
  203. +nvram_setbyte(int offs, unsigned char val)
  204. +{
  205. + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
  206. +
  207. + *nvramDataPointer = val;
  208. +}
  209. +
  210. +/*
  211. + * BigEndian!
  212. + */
  213. +static unsigned short
  214. +nvram_getshort(int offs)
  215. +{
  216. + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
  217. +}
  218. +
  219. +static void
  220. +nvram_setshort(int offs, unsigned short val)
  221. +{
  222. + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
  223. + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
  224. +}
  225. +#if 0
  226. +static unsigned int
  227. +nvram_getint(int offs)
  228. +{
  229. + unsigned int val;
  230. + val = nvram_getbyte(offs) << 24;
  231. + val |= nvram_getbyte(offs + 1) << 16;
  232. + val |= nvram_getbyte(offs + 2) << 8;
  233. + val |= nvram_getbyte(offs + 3);
  234. + return(val);
  235. +}
  236. +
  237. +static void
  238. +nvram_setint(int offs, unsigned int val)
  239. +{
  240. + nvram_setbyte(offs, val >> 24);
  241. + nvram_setbyte(offs + 1, val >> 16);
  242. + nvram_setbyte(offs + 2, val >> 8);
  243. + nvram_setbyte(offs + 3, val);
  244. +}
  245. +#endif
  246. +/*
  247. + * calculate NVRAM checksum
  248. + */
  249. +static unsigned short
  250. +nvram_calcsum(void)
  251. +{
  252. + unsigned short sum = NV_MAGIC;
  253. + int i;
  254. +
  255. + for (i = ENV_BASE; i < ENV_TOP; i += 2)
  256. + sum += nvram_getshort(i);
  257. + return(sum);
  258. +}
  259. +
  260. +/*
  261. + * update the nvram checksum
  262. + */
  263. +static void
  264. +nvram_updatesum (void)
  265. +{
  266. + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
  267. +}
  268. +
  269. +/*
  270. + * test validity of nvram by checksumming it
  271. + */
  272. +static int
  273. +nvram_isvalid(void)
  274. +{
  275. + static int is_valid;
  276. +
  277. + if (is_valid)
  278. + return(1);
  279. +
  280. + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
  281. + printk("nvram_isvalid FAILED\n");
  282. + //nvram_initenv();
  283. + }
  284. + is_valid = 1;
  285. + return(1);
  286. +}
  287. +
  288. +/* return nvram address of environment string */
  289. +static int
  290. +nvram_matchenv(char *s)
  291. +{
  292. + int envsize, envp, n, i, varsize;
  293. + char *var;
  294. +
  295. + envsize = nvram_getshort(NVOFF_ENVSIZE);
  296. +
  297. + if (envsize > ENV_AVAIL)
  298. + return(0); /* sanity */
  299. +
  300. + envp = ENV_BASE;
  301. +
  302. + if ((n = strlen (s)) > 255)
  303. + return(0);
  304. +
  305. + while (envsize > 0) {
  306. + varsize = nvram_getbyte(envp);
  307. + if (varsize == 0 || (envp + varsize) > ENV_TOP)
  308. + return(0); /* sanity */
  309. + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
  310. + char c1 = nvram_getbyte(i);
  311. + char c2 = *var;
  312. + if (islower(c1))
  313. + c1 = toupper(c1);
  314. + if (islower(c2))
  315. + c2 = toupper(c2);
  316. + if (c1 != c2)
  317. + break;
  318. + }
  319. + if (i > envp + n) { /* match so far */
  320. + if (n == varsize - 1) /* match on boolean */
  321. + return(envp);
  322. + if (nvram_getbyte(i) == '=') /* exact match on variable */
  323. + return(envp);
  324. + }
  325. + envsize -= varsize;
  326. + envp += varsize;
  327. + }
  328. + return(0);
  329. +}
  330. +
  331. +static void nvram_initenv(void)
  332. +{
  333. + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
  334. + nvram_setshort(NVOFF_ENVSIZE, 0);
  335. +
  336. + nvram_updatesum();
  337. +}
  338. +
  339. +static void
  340. +nvram_delenv(char *s)
  341. +{
  342. + int nenvp, envp, envsize, nbytes;
  343. +
  344. + envp = nvram_matchenv(s);
  345. + if (envp == 0)
  346. + return;
  347. +
  348. + nenvp = envp + nvram_getbyte(envp);
  349. + envsize = nvram_getshort(NVOFF_ENVSIZE);
  350. + nbytes = envsize - (nenvp - ENV_BASE);
  351. + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
  352. + while (nbytes--) {
  353. + nvram_setbyte(envp, nvram_getbyte(nenvp));
  354. + envp++;
  355. + nenvp++;
  356. + }
  357. + nvram_updatesum();
  358. +}
  359. +
  360. +static int
  361. +nvram_setenv(char *s, char *v)
  362. +{
  363. + int ns, nv, total;
  364. + int envp;
  365. +
  366. + if (!nvram_isvalid())
  367. + return(-1);
  368. +
  369. + nvram_delenv(s);
  370. + ns = strlen(s);
  371. + if (ns == 0)
  372. + return (-1);
  373. + if (v && *v) {
  374. + nv = strlen(v);
  375. + total = ns + nv + 2;
  376. + }
  377. + else {
  378. + nv = 0;
  379. + total = ns + 1;
  380. + }
  381. + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
  382. + return(-1);
  383. +
  384. + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
  385. +
  386. + nvram_setbyte(envp, (unsigned char) total);
  387. + envp++;
  388. +
  389. + while (ns--) {
  390. + nvram_setbyte(envp, *s);
  391. + envp++;
  392. + s++;
  393. + }
  394. +
  395. + if (nv) {
  396. + nvram_setbyte(envp, '=');
  397. + envp++;
  398. + while (nv--) {
  399. + nvram_setbyte(envp, *v);
  400. + envp++;
  401. + v++;
  402. + }
  403. + }
  404. + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
  405. + nvram_updatesum();
  406. + return 0;
  407. +}
  408. +
  409. +static char *
  410. +nvram_getenv(char *s)
  411. +{
  412. + static char buf[256]; /* FIXME: this cannot be static */
  413. + int envp, ns, nbytes, i;
  414. +
  415. + if (!nvram_isvalid())
  416. + return "INVALID NVRAM"; //((char *)0);
  417. +
  418. + envp = nvram_matchenv(s);
  419. + if (envp == 0)
  420. + return "NOT FOUND"; //((char *)0);
  421. + ns = strlen(s);
  422. + if (nvram_getbyte(envp) == ns + 1) /* boolean */
  423. + buf[0] = '\0';
  424. + else {
  425. + nbytes = nvram_getbyte(envp) - (ns + 2);
  426. + envp += ns + 2;
  427. + for (i = 0; i < nbytes; i++)
  428. + buf[i] = nvram_getbyte(envp++);
  429. + buf[i] = '\0';
  430. + }
  431. + return(buf);
  432. +}
  433. +
  434. +static void
  435. +nvram_unsetenv(char *s)
  436. +{
  437. + if (!nvram_isvalid())
  438. + return;
  439. +
  440. + nvram_delenv(s);
  441. +}
  442. +
  443. +/*
  444. + * apply func to each string in environment
  445. + */
  446. +static void
  447. +nvram_mapenv(int (*func)(char *, char *))
  448. +{
  449. + int envsize, envp, n, i, seeneql;
  450. + char name[256], value[256];
  451. + char c, *s;
  452. +
  453. + if (!nvram_isvalid())
  454. + return;
  455. +
  456. + envsize = nvram_getshort(NVOFF_ENVSIZE);
  457. + envp = ENV_BASE;
  458. +
  459. + while (envsize > 0) {
  460. + value[0] = '\0';
  461. + seeneql = 0;
  462. + s = name;
  463. + n = nvram_getbyte(envp);
  464. + for (i = envp + 1; i < envp + n; i++) {
  465. + c = nvram_getbyte(i);
  466. + if ((c == '=') && !seeneql) {
  467. + *s = '\0';
  468. + s = value;
  469. + seeneql = 1;
  470. + continue;
  471. + }
  472. + *s++ = c;
  473. + }
  474. + *s = '\0';
  475. + (*func)(name, value);
  476. + envsize -= n;
  477. + envp += n;
  478. + }
  479. +}
  480. +#if 0
  481. +static unsigned int
  482. +digit(char c)
  483. +{
  484. + if ('0' <= c && c <= '9')
  485. + return (c - '0');
  486. + if ('A' <= c && c <= 'Z')
  487. + return (10 + c - 'A');
  488. + if ('a' <= c && c <= 'z')
  489. + return (10 + c - 'a');
  490. + return (~0);
  491. +}
  492. +#endif
  493. +/*
  494. + * Wrappers to allow 'special' environment variables to get processed
  495. + */
  496. +void
  497. +setenv(char *e, char *v, int rewrite)
  498. +{
  499. + if (nvram_getenv(e) && !rewrite)
  500. + return;
  501. +
  502. + nvram_setenv(e, v);
  503. +}
  504. +
  505. +char *
  506. +getenv(char *e)
  507. +{
  508. + return(nvram_getenv(e));
  509. +}
  510. +
  511. +void
  512. +unsetenv(char *e)
  513. +{
  514. + nvram_unsetenv(e);
  515. +}
  516. +
  517. +void
  518. +purgeenv()
  519. +{
  520. + int i;
  521. + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
  522. +
  523. + for (i = ENV_BASE; i < ENV_TOP; i++)
  524. + *nvramDataPointer++ = 0;
  525. + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
  526. + nvram_setshort(NVOFF_ENVSIZE, 0);
  527. + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
  528. +}
  529. +
  530. +void
  531. +mapenv(int (*func)(char *, char *))
  532. +{
  533. + nvram_mapenv(func);
  534. +}
  535. diff -Nur linux-2.6.21.5-pristine/arch/mips/aruba/nvram/nvram434.h linux-2.6.21.5/arch/mips/aruba/nvram/nvram434.h
  536. --- linux-2.6.21.5-pristine/arch/mips/aruba/nvram/nvram434.h 1969-12-31 19:00:00.000000000 -0500
  537. +++ linux-2.6.21.5/arch/mips/aruba/nvram/nvram434.h 2007-09-20 00:16:52.000000000 -0400
  538. @@ -0,0 +1,66 @@
  539. +/**************************************************************************
  540. + *
  541. + * BRIEF MODULE DESCRIPTION
  542. + * nvram definitions.
  543. + *
  544. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  545. + *
  546. + * This program is free software; you can redistribute it and/or modify it
  547. + * under the terms of the GNU General Public License as published by the
  548. + * Free Software Foundation; either version 2 of the License, or (at your
  549. + * option) any later version.
  550. + *
  551. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  552. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  553. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  554. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  555. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  556. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  557. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  558. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  559. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  560. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  561. + *
  562. + * You should have received a copy of the GNU General Public License along
  563. + * with this program; if not, write to the Free Software Foundation, Inc.,
  564. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  565. + *
  566. + *
  567. + **************************************************************************
  568. + * May 2004 rkt, neb
  569. + *
  570. + * Initial Release
  571. + *
  572. + *
  573. + *
  574. + **************************************************************************
  575. + */
  576. +
  577. +
  578. +#ifndef _NVRAM_
  579. +#define _NVRAM_
  580. +#define NVOFFSET 0 /* use all of NVRAM */
  581. +
  582. +/* Offsets to reserved locations */
  583. + /* size description */
  584. +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
  585. +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
  586. +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
  587. +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
  588. +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
  589. +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
  590. +
  591. +#define NV_MAGIC 0xdeaf /* nvram magic number */
  592. +#define NV_RESERVED 6 /* number of reserved bytes */
  593. +
  594. +#undef NVOFF_ETHADDR
  595. +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
  596. +
  597. +/* number of bytes available for environment */
  598. +#define ENV_BASE (NVOFFSET + NV_RESERVED)
  599. +#define ENV_TOP 0x2000
  600. +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
  601. +
  602. +#endif /* _NVRAM_ */
  603. +
  604. +
  605. diff -Nur linux-2.6.21.5-pristine/arch/mips/aruba/prom.c linux-2.6.21.5/arch/mips/aruba/prom.c
  606. --- linux-2.6.21.5-pristine/arch/mips/aruba/prom.c 1969-12-31 19:00:00.000000000 -0500
  607. +++ linux-2.6.21.5/arch/mips/aruba/prom.c 2007-09-20 00:16:52.000000000 -0400
  608. @@ -0,0 +1,114 @@
  609. +/**************************************************************************
  610. + *
  611. + * BRIEF MODULE DESCRIPTION
  612. + * prom interface routines
  613. + *
  614. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  615. + *
  616. + * This program is free software; you can redistribute it and/or modify it
  617. + * under the terms of the GNU General Public License as published by the
  618. + * Free Software Foundation; either version 2 of the License, or (at your
  619. + * option) any later version.
  620. + *
  621. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  622. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  623. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  624. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  625. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  626. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  627. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  628. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  629. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  630. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  631. + *
  632. + * You should have received a copy of the GNU General Public License along
  633. + * with this program; if not, write to the Free Software Foundation, Inc.,
  634. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  635. + *
  636. + *
  637. + **************************************************************************
  638. + * May 2004 rkt, neb
  639. + *
  640. + * Initial Release
  641. + *
  642. + *
  643. + *
  644. + **************************************************************************
  645. + */
  646. +
  647. +#include <linux/autoconf.h>
  648. +#include <linux/init.h>
  649. +#include <linux/mm.h>
  650. +#include <linux/module.h>
  651. +#include <linux/string.h>
  652. +#include <linux/console.h>
  653. +#include <asm/bootinfo.h>
  654. +#include <linux/bootmem.h>
  655. +#include <linux/ioport.h>
  656. +#include <linux/serial.h>
  657. +#include <linux/serialP.h>
  658. +#include <asm/serial.h>
  659. +#include <linux/ioport.h>
  660. +
  661. +unsigned int idt_cpu_freq;
  662. +EXPORT_SYMBOL(idt_cpu_freq);
  663. +
  664. +unsigned int arch_has_pci=0;
  665. +
  666. +/* Kernel Boot parameters */
  667. +static unsigned char bootparm[] =
  668. + "init=/etc/preinit "
  669. + "mtdparts=physmap-flash.0:3520k@0x080000(zImage),2752k@0x140000(JFFS2),8k@0x3f8000(NVRAM) "
  670. + "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2 ";
  671. +
  672. +extern unsigned long mips_machgroup;
  673. +extern unsigned long mips_machtype;
  674. +
  675. +extern void setup_serial_port(void);
  676. +extern char * getenv(char *e);
  677. +
  678. +/* IDT 79EB434 memory map -- we really should be auto sizing it */
  679. +#define RAM_SIZE 32*1024*1024
  680. +
  681. +char *__init prom_getcmdline(void)
  682. +{
  683. + return &(arcs_cmdline[0]);
  684. +}
  685. +
  686. +void __init prom_init(void)
  687. +{
  688. + char *boardname;
  689. + sprintf(arcs_cmdline, "%s", bootparm);
  690. +
  691. + /* set our arch type */
  692. + mips_machgroup = MACH_GROUP_ARUBA;
  693. + mips_machtype = MACH_ARUBA_UNKNOWN;
  694. +
  695. + boardname=getenv("boardname");
  696. +
  697. + if (!strcmp(boardname,"Muscat")) {
  698. + mips_machtype = MACH_ARUBA_AP70;
  699. + idt_cpu_freq = 133000000;
  700. + arch_has_pci=1;
  701. + } else if (!strcmp(boardname,"Mataro")) {
  702. + mips_machtype = MACH_ARUBA_AP65;
  703. + idt_cpu_freq = 110000000;
  704. + } else if (!strcmp(boardname,"Merlot")) {
  705. + mips_machtype = MACH_ARUBA_AP60;
  706. + idt_cpu_freq = 90000000;
  707. + }
  708. +
  709. + /* turn on the console */
  710. + setup_serial_port();
  711. +
  712. + /*
  713. + * give all RAM to boot allocator,
  714. + * except where the kernel was loaded
  715. + */
  716. + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
  717. +}
  718. +
  719. +void prom_free_prom_memory(void)
  720. +{
  721. + printk("stubbed prom_free_prom_memory()\n");
  722. +}
  723. diff -Nur linux-2.6.21.5-pristine/arch/mips/aruba/serial.c linux-2.6.21.5/arch/mips/aruba/serial.c
  724. --- linux-2.6.21.5-pristine/arch/mips/aruba/serial.c 1969-12-31 19:00:00.000000000 -0500
  725. +++ linux-2.6.21.5/arch/mips/aruba/serial.c 2007-09-20 00:16:52.000000000 -0400
  726. @@ -0,0 +1,94 @@
  727. +/**************************************************************************
  728. + *
  729. + * BRIEF MODULE DESCRIPTION
  730. + * Serial port initialisation.
  731. + *
  732. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  733. + *
  734. + * This program is free software; you can redistribute it and/or modify it
  735. + * under the terms of the GNU General Public License as published by the
  736. + * Free Software Foundation; either version 2 of the License, or (at your
  737. + * option) any later version.
  738. + *
  739. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  740. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  741. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  742. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  743. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  744. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  745. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  746. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  747. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  748. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  749. + *
  750. + * You should have received a copy of the GNU General Public License along
  751. + * with this program; if not, write to the Free Software Foundation, Inc.,
  752. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  753. + *
  754. + *
  755. + **************************************************************************
  756. + * May 2004 rkt, neb
  757. + *
  758. + * Initial Release
  759. + *
  760. + *
  761. + *
  762. + **************************************************************************
  763. + */
  764. +
  765. +
  766. +#include <linux/autoconf.h>
  767. +#include <linux/init.h>
  768. +#include <linux/sched.h>
  769. +#include <linux/pci.h>
  770. +#include <linux/interrupt.h>
  771. +#include <linux/tty.h>
  772. +#include <linux/serial.h>
  773. +#include <linux/serial_core.h>
  774. +
  775. +#include <asm/time.h>
  776. +#include <asm/cpu.h>
  777. +#include <asm/bootinfo.h>
  778. +#include <asm/irq.h>
  779. +#include <asm/serial.h>
  780. +
  781. +#include <asm/idt-boards/rc32434/rc32434.h>
  782. +
  783. +extern int __init early_serial_setup(struct uart_port *port);
  784. +
  785. +#define BASE_BAUD (1843200 / 16)
  786. +
  787. +extern unsigned int idt_cpu_freq;
  788. +
  789. +extern int __init setup_serial_port(void)
  790. +{
  791. + static struct uart_port serial_req[2];
  792. +
  793. + memset(serial_req, 0, sizeof(serial_req));
  794. + serial_req[0].type = PORT_16550A;
  795. + serial_req[0].line = 0;
  796. + serial_req[0].flags = STD_COM_FLAGS;
  797. + serial_req[0].iotype = SERIAL_IO_MEM;
  798. + serial_req[0].regshift = 2;
  799. +
  800. + switch (mips_machtype) {
  801. + case MACH_ARUBA_AP70:
  802. + serial_req[0].irq = 104;
  803. + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
  804. + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
  805. + serial_req[0].uartclk = idt_cpu_freq;
  806. + break;
  807. + case MACH_ARUBA_AP65:
  808. + case MACH_ARUBA_AP60:
  809. + default:
  810. + serial_req[0].irq = 12;
  811. + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
  812. + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
  813. + serial_req[0].uartclk = idt_cpu_freq / 2;
  814. + break;
  815. + }
  816. +
  817. + early_serial_setup(&serial_req[0]);
  818. +
  819. + return(0);
  820. +}
  821. diff -Nur linux-2.6.21.5-pristine/arch/mips/aruba/setup.c linux-2.6.21.5/arch/mips/aruba/setup.c
  822. --- linux-2.6.21.5-pristine/arch/mips/aruba/setup.c 1969-12-31 19:00:00.000000000 -0500
  823. +++ linux-2.6.21.5/arch/mips/aruba/setup.c 2007-09-20 00:16:52.000000000 -0400
  824. @@ -0,0 +1,128 @@
  825. +/**************************************************************************
  826. + *
  827. + * BRIEF MODULE DESCRIPTION
  828. + * setup routines for IDT EB434 boards
  829. + *
  830. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  831. + *
  832. + * This program is free software; you can redistribute it and/or modify it
  833. + * under the terms of the GNU General Public License as published by the
  834. + * Free Software Foundation; either version 2 of the License, or (at your
  835. + * option) any later version.
  836. + *
  837. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  838. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  839. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  840. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  841. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  842. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  843. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  844. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  845. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  846. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  847. + *
  848. + * You should have received a copy of the GNU General Public License along
  849. + * with this program; if not, write to the Free Software Foundation, Inc.,
  850. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  851. + *
  852. + *
  853. + **************************************************************************
  854. + * May 2004 rkt, neb
  855. + *
  856. + * Initial Release
  857. + *
  858. + *
  859. + *
  860. + **************************************************************************
  861. + */
  862. +
  863. +#include <linux/init.h>
  864. +#include <linux/module.h>
  865. +#include <linux/mm.h>
  866. +#include <linux/sched.h>
  867. +#include <linux/irq.h>
  868. +#include <asm/bootinfo.h>
  869. +#include <asm/io.h>
  870. +#include <linux/ioport.h>
  871. +#include <asm/mipsregs.h>
  872. +#include <asm/pgtable.h>
  873. +#include <asm/reboot.h>
  874. +#include <asm/addrspace.h> /* for KSEG1ADDR() */
  875. +#include <asm/idt-boards/rc32434/rc32434.h>
  876. +#include <linux/pm.h>
  877. +
  878. +extern char *__init prom_getcmdline(void);
  879. +
  880. +extern void (*board_time_init) (void);
  881. +extern void aruba_time_init(void);
  882. +extern void aruba_reset(void);
  883. +
  884. +#define epldMask ((volatile unsigned char *)0xB900000d)
  885. +
  886. +static void aruba_machine_restart(char *command)
  887. +{
  888. + switch (mips_machtype) {
  889. + case MACH_ARUBA_AP70:
  890. + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
  891. + break;
  892. + case MACH_ARUBA_AP65:
  893. + case MACH_ARUBA_AP60:
  894. + default:
  895. + /* Reset*/
  896. + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
  897. + udelay(100);
  898. + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
  899. + udelay(100);
  900. + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
  901. + break;
  902. + }
  903. +}
  904. +
  905. +static void aruba_machine_halt(void)
  906. +{
  907. + for (;;) continue;
  908. +}
  909. +
  910. +extern char * getenv(char *e);
  911. +extern void unlock_ap60_70_flash(void);
  912. +
  913. +void __init plat_mem_setup(void)
  914. +{
  915. + board_time_init = aruba_time_init;
  916. +
  917. + _machine_restart = aruba_machine_restart;
  918. + _machine_halt = aruba_machine_halt;
  919. + pm_power_off = aruba_machine_halt;
  920. +
  921. + set_io_port_base(KSEG1);
  922. +
  923. + /* Enable PCI interrupts in EPLD Mask register */
  924. + *epldMask = 0x0;
  925. + *(epldMask + 1) = 0x0;
  926. +
  927. + write_c0_wired(0);
  928. + unlock_ap60_70_flash();
  929. +
  930. + printk("BOARD - %s\n",getenv("boardname"));
  931. +}
  932. +
  933. +int page_is_ram(unsigned long pagenr)
  934. +{
  935. + return 1;
  936. +}
  937. +
  938. +const char *get_system_type(void)
  939. +{
  940. + switch (mips_machtype) {
  941. + case MACH_ARUBA_AP70:
  942. + return "Aruba AP70";
  943. + case MACH_ARUBA_AP65:
  944. + return "Aruba AP65";
  945. + case MACH_ARUBA_AP60:
  946. + return "Aruba AP60/AP61";
  947. + default:
  948. + return "Aruba UNKNOWN";
  949. + }
  950. +}
  951. +
  952. +EXPORT_SYMBOL(get_system_type);
  953. diff -Nur linux-2.6.21.5-pristine/arch/mips/aruba/time.c linux-2.6.21.5/arch/mips/aruba/time.c
  954. --- linux-2.6.21.5-pristine/arch/mips/aruba/time.c 1969-12-31 19:00:00.000000000 -0500
  955. +++ linux-2.6.21.5/arch/mips/aruba/time.c 2007-09-20 00:16:52.000000000 -0400
  956. @@ -0,0 +1,110 @@
  957. +/**************************************************************************
  958. + *
  959. + * BRIEF MODULE DESCRIPTION
  960. + * timer routines for IDT EB434 boards
  961. + *
  962. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  963. + *
  964. + * This program is free software; you can redistribute it and/or modify it
  965. + * under the terms of the GNU General Public License as published by the
  966. + * Free Software Foundation; either version 2 of the License, or (at your
  967. + * option) any later version.
  968. + *
  969. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  970. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  971. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  972. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  973. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  974. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  975. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  976. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  977. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  978. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  979. + *
  980. + * You should have received a copy of the GNU General Public License along
  981. + * with this program; if not, write to the Free Software Foundation, Inc.,
  982. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  983. + *
  984. + *
  985. + **************************************************************************
  986. + * May 2004 rkt, neb
  987. + *
  988. + * Initial Release
  989. + *
  990. + *
  991. + *
  992. + **************************************************************************
  993. + */
  994. +
  995. +#include <linux/autoconf.h>
  996. +#include <linux/init.h>
  997. +#include <linux/kernel_stat.h>
  998. +#include <linux/sched.h>
  999. +#include <linux/spinlock.h>
  1000. +#include <linux/mc146818rtc.h>
  1001. +#include <linux/irq.h>
  1002. +#include <linux/timex.h>
  1003. +
  1004. +#include <linux/param.h>
  1005. +#include <asm/mipsregs.h>
  1006. +#include <asm/ptrace.h>
  1007. +#include <asm/time.h>
  1008. +#include <asm/hardirq.h>
  1009. +
  1010. +#include <asm/mipsregs.h>
  1011. +#include <asm/ptrace.h>
  1012. +#include <asm/debug.h>
  1013. +#include <asm/time.h>
  1014. +
  1015. +#include <asm/idt-boards/rc32434/rc32434.h>
  1016. +
  1017. +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
  1018. +static unsigned long r4k_cur; /* What counter should be at next timer irq */
  1019. +
  1020. +extern unsigned int idt_cpu_freq;
  1021. +
  1022. +static unsigned long __init cal_r4koff(void)
  1023. +{
  1024. + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
  1025. + return (mips_hpt_frequency / HZ);
  1026. +}
  1027. +
  1028. +void __init aruba_time_init(void)
  1029. +{
  1030. + unsigned int est_freq, flags;
  1031. + local_irq_save(flags);
  1032. +
  1033. + printk("calculating r4koff... ");
  1034. + r4k_offset = cal_r4koff();
  1035. + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
  1036. +
  1037. + est_freq = 2 * r4k_offset * HZ;
  1038. + est_freq += 5000; /* round */
  1039. + est_freq -= est_freq % 10000;
  1040. + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
  1041. + (est_freq % 1000000) * 100 / 1000000);
  1042. + local_irq_restore(flags);
  1043. +
  1044. +}
  1045. +
  1046. +void __init plat_timer_setup(struct irqaction *irq)
  1047. +{
  1048. + /* we are using the cpu counter for timer interrupts */
  1049. + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
  1050. +
  1051. + /* to generate the first timer interrupt */
  1052. + r4k_cur = (read_c0_count() + r4k_offset);
  1053. + write_c0_compare(r4k_cur);
  1054. +
  1055. +}
  1056. +
  1057. +asmlinkage void aruba_timer_interrupt(struct pt_regs *regs)
  1058. +{
  1059. + int irq = MIPS_CPU_TIMER_IRQ;
  1060. +
  1061. + irq_enter();
  1062. + kstat_this_cpu.irqs[irq]++;
  1063. +
  1064. + timer_interrupt(irq, NULL);
  1065. + irq_exit();
  1066. +}
  1067. --- a/drivers/net/Kconfig
  1068. +++ b/drivers/net/Kconfig
  1069. @@ -369,6 +369,13 @@
  1070. help
  1071. Select this if your platform comes with an external 93CX6 eeprom.
  1072.  
  1073. +config IDT_RC32434_ETH
  1074. + tristate "IDT RC32434 Local Ethernet support"
  1075. + depends on NET_ETHERNET
  1076. + help
  1077. + IDT RC32434 has one local ethernet port. Say Y here to enable it.
  1078. + To compile this driver as a module, choose M here.
  1079. +
  1080. config MACE
  1081. tristate "MACE (Power Mac ethernet) support"
  1082. depends on PPC_PMAC && PPC32
  1083. --- a/drivers/net/Makefile
  1084. +++ b/drivers/net/Makefile
  1085. @@ -53,6 +53,7 @@
  1086. obj-$(CONFIG_MACE) += mace.o
  1087. obj-$(CONFIG_BMAC) += bmac.o
  1088.  
  1089. +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
  1090. obj-$(CONFIG_VORTEX) += 3c59x.o
  1091. obj-$(CONFIG_TYPHOON) += typhoon.o
  1092. obj-$(CONFIG_NE2K_PCI) += ne2k-pci.o 8390.o
  1093. --- a/drivers/net/natsemi.c
  1094. +++ b/drivers/net/natsemi.c
  1095. @@ -648,6 +648,50 @@
  1096. static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
  1097. static const struct ethtool_ops ethtool_ops;
  1098.  
  1099. +#ifdef CONFIG_MACH_ARUBA
  1100. +
  1101. +#include <linux/ctype.h>
  1102. +
  1103. +#ifndef ERR
  1104. +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
  1105. +#endif
  1106. +
  1107. +static int parse_mac_addr(struct net_device *dev, char* macstr)
  1108. +{
  1109. + int i, j;
  1110. + unsigned char result, value;
  1111. +
  1112. + for (i=0; i<6; i++) {
  1113. + result = 0;
  1114. + if (i != 5 && *(macstr+2) != ':') {
  1115. + ERR("invalid mac address format: %d %c\n",
  1116. + i, *(macstr+2));
  1117. + return -EINVAL;
  1118. + }
  1119. + for (j=0; j<2; j++) {
  1120. + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
  1121. + toupper(*macstr)-'A'+10) < 16) {
  1122. + result = result*16 + value;
  1123. + macstr++;
  1124. + }
  1125. + else {
  1126. + ERR("invalid mac address "
  1127. + "character: %c\n", *macstr);
  1128. + return -EINVAL;
  1129. + }
  1130. + }
  1131. +
  1132. + macstr++;
  1133. + dev->dev_addr[i] = result;
  1134. + }
  1135. +
  1136. + dev->dev_addr[5]++;
  1137. + return 0;
  1138. +}
  1139. +
  1140. +#endif
  1141. +
  1142. +
  1143. #define NATSEMI_ATTR(_name) \
  1144. static ssize_t natsemi_show_##_name(struct device *dev, \
  1145. struct device_attribute *attr, char *buf); \
  1146. @@ -851,7 +851,7 @@
  1147. i = -ENOMEM;
  1148. goto err_ioremap;
  1149. }
  1150. -
  1151. + #ifndef CONFIG_MACH_ARUBA
  1152. /* Work around the dropped serial bit. */
  1153. prev_eedata = eeprom_read(ioaddr, 6);
  1154. for (i = 0; i < 3; i++) {
  1155. @@ -860,10 +860,21 @@
  1156. dev->dev_addr[i*2+1] = eedata >> 7;
  1157. prev_eedata = eedata;
  1158. }
  1159. -
  1160. + #else
  1161. + {
  1162. + char mac[32];
  1163. + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
  1164. + extern char *getenv(char *e);
  1165. + memset(mac, 0, 32);
  1166. + memcpy(mac, getenv("ethaddr"), 17);
  1167. + if (parse_mac_addr(dev, mac)){
  1168. + printk("%s: MAC address not found\n", __func__);
  1169. + memcpy(dev->dev_addr, def_mac, 6);
  1170. + }
  1171. + }
  1172. + #endif
  1173. dev->base_addr = (unsigned long __force) ioaddr;
  1174. dev->irq = irq;
  1175. -
  1176. np = netdev_priv(dev);
  1177. netif_napi_add(dev, &np->napi, natsemi_poll, 64);
  1178. np->dev = dev;
  1179. --- linux-2.6.21.5-pristine/drivers/net/rc32434_eth.c 1969-12-31 19:00:00.000000000 -0500
  1180. +++ linux-2.6.21.5/drivers/net/rc32434_eth.c 2007-09-20 00:16:52.000000000 -0400
  1181. @@ -0,0 +1,1273 @@
  1182. +/**************************************************************************
  1183. + *
  1184. + * BRIEF MODULE DESCRIPTION
  1185. + * Driver for the IDT RC32434 on-chip ethernet controller.
  1186. + *
  1187. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  1188. + *
  1189. + * This program is free software; you can redistribute it and/or modify it
  1190. + * under the terms of the GNU General Public License as published by the
  1191. + * Free Software Foundation; either version 2 of the License, or (at your
  1192. + * option) any later version.
  1193. + *
  1194. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  1195. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  1196. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  1197. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  1198. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  1199. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  1200. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  1201. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  1202. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  1203. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  1204. + *
  1205. + * You should have received a copy of the GNU General Public License along
  1206. + * with this program; if not, write to the Free Software Foundation, Inc.,
  1207. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  1208. + *
  1209. + *
  1210. + **************************************************************************
  1211. + * May 2004 rkt, neb
  1212. + *
  1213. + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
  1214. + *
  1215. + * Aug 2004 Sadik
  1216. + *
  1217. + * Added NAPI
  1218. + *
  1219. + **************************************************************************
  1220. + */
  1221. +
  1222. +#include <linux/autoconf.h>
  1223. +#include <linux/version.h>
  1224. +#include <linux/module.h>
  1225. +#include <linux/kernel.h>
  1226. +#include <linux/moduleparam.h>
  1227. +#include <linux/sched.h>
  1228. +#include <linux/ctype.h>
  1229. +#include <linux/types.h>
  1230. +#include <linux/fcntl.h>
  1231. +#include <linux/interrupt.h>
  1232. +#include <linux/ptrace.h>
  1233. +#include <linux/init.h>
  1234. +#include <linux/ioport.h>
  1235. +#include <linux/proc_fs.h>
  1236. +#include <linux/in.h>
  1237. +#include <linux/slab.h>
  1238. +#include <linux/string.h>
  1239. +#include <linux/delay.h>
  1240. +#include <linux/netdevice.h>
  1241. +#include <linux/etherdevice.h>
  1242. +#include <linux/skbuff.h>
  1243. +#include <linux/errno.h>
  1244. +#include <asm/bootinfo.h>
  1245. +#include <asm/system.h>
  1246. +#include <asm/bitops.h>
  1247. +#include <asm/pgtable.h>
  1248. +#include <asm/segment.h>
  1249. +#include <asm/io.h>
  1250. +#include <asm/dma.h>
  1251. +
  1252. +#include "rc32434_eth.h"
  1253. +
  1254. +#define DRIVER_VERSION "(mar2904)"
  1255. +
  1256. +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
  1257. +
  1258. +
  1259. +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
  1260. + ((dev)->dev_addr[1]))
  1261. +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
  1262. + ((dev)->dev_addr[3] << 16) | \
  1263. + ((dev)->dev_addr[4] << 8) | \
  1264. + ((dev)->dev_addr[5]))
  1265. +
  1266. +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
  1267. +static char mac0[18] = "08:00:06:05:40:01";
  1268. +
  1269. +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52)
  1270. +module_param_string(mac0, mac0, 18, 0);
  1271. +#else
  1272. +MODULE_PARM(mac0, "c18");
  1273. +#endif
  1274. +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
  1275. +
  1276. +static struct rc32434_if_t {
  1277. + char *name;
  1278. + struct net_device *dev;
  1279. + char* mac_str;
  1280. + int weight;
  1281. + u32 iobase;
  1282. + u32 rxdmabase;
  1283. + u32 txdmabase;
  1284. + int rx_dma_irq;
  1285. + int tx_dma_irq;
  1286. + int rx_ovr_irq;
  1287. + int tx_und_irq;
  1288. +} rc32434_iflist[] =
  1289. +{
  1290. + {
  1291. + "rc32434_eth0", NULL, mac0,
  1292. + 64,
  1293. + ETH0_PhysicalAddress,
  1294. + ETH0_RX_DMA_ADDR,
  1295. + ETH0_TX_DMA_ADDR,
  1296. + ETH0_DMA_RX_IRQ,
  1297. + ETH0_DMA_TX_IRQ,
  1298. + ETH0_RX_OVR_IRQ,
  1299. + ETH0_TX_UND_IRQ
  1300. + }
  1301. +};
  1302. +
  1303. +
  1304. +static int parse_mac_addr(struct net_device *dev, char* macstr)
  1305. +{
  1306. + int i, j;
  1307. + unsigned char result, value;
  1308. +
  1309. + for (i=0; i<6; i++) {
  1310. + result = 0;
  1311. + if (i != 5 && *(macstr+2) != ':') {
  1312. + ERR("invalid mac address format: %d %c\n",
  1313. + i, *(macstr+2));
  1314. + return -EINVAL;
  1315. + }
  1316. + for (j=0; j<2; j++) {
  1317. + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
  1318. + toupper(*macstr)-'A'+10) < 16) {
  1319. + result = result*16 + value;
  1320. + macstr++;
  1321. + }
  1322. + else {
  1323. + ERR("invalid mac address "
  1324. + "character: %c\n", *macstr);
  1325. + return -EINVAL;
  1326. + }
  1327. + }
  1328. +
  1329. + macstr++;
  1330. + dev->dev_addr[i] = result;
  1331. + }
  1332. +
  1333. + return 0;
  1334. +}
  1335. +
  1336. +
  1337. +
  1338. +static inline void rc32434_abort_tx(struct net_device *dev)
  1339. +{
  1340. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  1341. + rc32434_abort_dma(dev, lp->tx_dma_regs);
  1342. +
  1343. +}
  1344. +
  1345. +static inline void rc32434_abort_rx(struct net_device *dev)
  1346. +{
  1347. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  1348. + rc32434_abort_dma(dev, lp->rx_dma_regs);
  1349. +
  1350. +}
  1351. +
  1352. +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
  1353. +{
  1354. + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
  1355. +}
  1356. +
  1357. +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
  1358. +{
  1359. + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
  1360. +}
  1361. +
  1362. +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
  1363. +{
  1364. + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
  1365. +}
  1366. +
  1367. +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
  1368. +{
  1369. + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
  1370. +}
  1371. +
  1372. +#ifdef RC32434_PROC_DEBUG
  1373. +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
  1374. + int length, int *eof, void *data)
  1375. +{
  1376. + struct net_device *dev = (struct net_device *)data;
  1377. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  1378. + int len = 0;
  1379. +
  1380. + /* print out header */
  1381. + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
  1382. + len += sprintf (buf + len,
  1383. + "DMA halt count = %10d, DMA run count = %10d\n",
  1384. + lp->dma_halt_cnt, lp->dma_run_cnt);
  1385. +
  1386. + if (fpos >= len) {
  1387. + *start = buf;
  1388. + *eof = 1;
  1389. + return 0;
  1390. + }
  1391. + *start = buf + fpos;
  1392. +
  1393. + if ((len -= fpos) > length)
  1394. + return length;
  1395. + *eof = 1;
  1396. +
  1397. + return len;
  1398. +
  1399. +}
  1400. +#endif
  1401. +
  1402. +
  1403. +/*
  1404. + * Restart the RC32434 ethernet controller.
  1405. + */
  1406. +static int rc32434_restart(struct net_device *dev)
  1407. +{
  1408. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  1409. +
  1410. + /*
  1411. + * Disable interrupts
  1412. + */
  1413. + disable_irq(lp->rx_irq);
  1414. + disable_irq(lp->tx_irq);
  1415. +#ifdef RC32434_REVISION
  1416. + disable_irq(lp->ovr_irq);
  1417. +#endif
  1418. + disable_irq(lp->und_irq);
  1419. +
  1420. + /* Mask F E bit in Tx DMA */
  1421. + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
  1422. + /* Mask D H E bit in Rx DMA */
  1423. + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
  1424. +
  1425. + rc32434_init(dev);
  1426. + rc32434_multicast_list(dev);
  1427. +
  1428. + enable_irq(lp->und_irq);
  1429. +#ifdef RC32434_REVISION
  1430. + enable_irq(lp->ovr_irq);
  1431. +#endif
  1432. + enable_irq(lp->tx_irq);
  1433. + enable_irq(lp->rx_irq);
  1434. +
  1435. + return 0;
  1436. +}
  1437. +
  1438. +int rc32434_init_module(void)
  1439. +{
  1440. +#ifdef CONFIG_MACH_ARUBA
  1441. + if (mips_machtype != MACH_ARUBA_AP70)
  1442. + return 1;
  1443. +#endif
  1444. +
  1445. + printk(KERN_INFO DRIVER_NAME " \n");
  1446. + return rc32434_probe(0);
  1447. +}
  1448. +
  1449. +static int rc32434_probe(int port_num)
  1450. +{
  1451. + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
  1452. + struct rc32434_local *lp = NULL;
  1453. + struct net_device *dev = NULL;
  1454. + int i, retval,err;
  1455. +
  1456. + dev = alloc_etherdev(sizeof(struct rc32434_local));
  1457. + if(!dev) {
  1458. + ERR("rc32434_eth: alloc_etherdev failed\n");
  1459. + return -1;
  1460. + }
  1461. +
  1462. + SET_MODULE_OWNER(dev);
  1463. + bif->dev = dev;
  1464. +
  1465. +#ifdef CONFIG_MACH_ARUBA
  1466. + {
  1467. + extern char * getenv(char *e);
  1468. + memcpy(bif->mac_str, getenv("ethaddr"), 17);
  1469. + }
  1470. +#endif
  1471. +
  1472. + printk("mac: %s\n", bif->mac_str);
  1473. + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
  1474. + ERR("MAC address parse failed\n");
  1475. + free_netdev(dev);
  1476. + return -1;
  1477. + }
  1478. +
  1479. +
  1480. + /* Initialize the device structure. */
  1481. + if (dev->priv == NULL) {
  1482. + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
  1483. + memset(lp, 0, sizeof(struct rc32434_local));
  1484. + }
  1485. + else {
  1486. + lp = (struct rc32434_local *)dev->priv;
  1487. + }
  1488. +
  1489. + lp->rx_irq = bif->rx_dma_irq;
  1490. + lp->tx_irq = bif->tx_dma_irq;
  1491. + lp->ovr_irq = bif->rx_ovr_irq;
  1492. + lp->und_irq = bif->tx_und_irq;
  1493. +
  1494. + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
  1495. +
  1496. + if (!lp->eth_regs) {
  1497. + ERR("Can't remap eth registers\n");
  1498. + retval = -ENXIO;
  1499. + goto probe_err_out;
  1500. + }
  1501. +
  1502. + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
  1503. +
  1504. + if (!lp->rx_dma_regs) {
  1505. + ERR("Can't remap Rx DMA registers\n");
  1506. + retval = -ENXIO;
  1507. + goto probe_err_out;
  1508. + }
  1509. + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
  1510. +
  1511. + if (!lp->tx_dma_regs) {
  1512. + ERR("Can't remap Tx DMA registers\n");
  1513. + retval = -ENXIO;
  1514. + goto probe_err_out;
  1515. + }
  1516. +
  1517. +#ifdef RC32434_PROC_DEBUG
  1518. + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
  1519. + rc32434_read_proc, dev);
  1520. +#endif
  1521. +
  1522. + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
  1523. + if (!lp->td_ring) {
  1524. + ERR("Can't allocate descriptors\n");
  1525. + retval = -ENOMEM;
  1526. + goto probe_err_out;
  1527. + }
  1528. +
  1529. + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
  1530. +
  1531. + /* now convert TD_RING pointer to KSEG1 */
  1532. + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
  1533. + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
  1534. +
  1535. +
  1536. + spin_lock_init(&lp->lock);
  1537. +
  1538. + dev->base_addr = bif->iobase;
  1539. + /* just use the rx dma irq */
  1540. + dev->irq = bif->rx_dma_irq;
  1541. +
  1542. + dev->priv = lp;
  1543. +
  1544. + dev->open = rc32434_open;
  1545. + dev->stop = rc32434_close;
  1546. + dev->hard_start_xmit = rc32434_send_packet;
  1547. + dev->get_stats = rc32434_get_stats;
  1548. + dev->set_multicast_list = &rc32434_multicast_list;
  1549. + dev->tx_timeout = rc32434_tx_timeout;
  1550. + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
  1551. +
  1552. +#ifdef CONFIG_IDT_USE_NAPI
  1553. + dev->poll = rc32434_poll;
  1554. + dev->weight = bif->weight;
  1555. + printk("Using NAPI with weight %d\n",dev->weight);
  1556. +#else
  1557. + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
  1558. + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
  1559. +#endif
  1560. + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
  1561. + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
  1562. +
  1563. + if ((err = register_netdev(dev))) {
  1564. + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
  1565. + free_netdev(dev);
  1566. + retval = -EINVAL;
  1567. + goto probe_err_out;
  1568. + }
  1569. +
  1570. + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
  1571. + for (i = 0; i < 6; i++) {
  1572. + printk("%2.2x", dev->dev_addr[i]);
  1573. + if (i<5)
  1574. + printk(":");
  1575. + }
  1576. + printk("\n");
  1577. +
  1578. + return 0;
  1579. +
  1580. + probe_err_out:
  1581. + rc32434_cleanup_module();
  1582. + ERR(" failed. Returns %d\n", retval);
  1583. + return retval;
  1584. +
  1585. +}
  1586. +
  1587. +
  1588. +static void rc32434_cleanup_module(void)
  1589. +{
  1590. + int i;
  1591. +
  1592. + for (i = 0; rc32434_iflist[i].iobase; i++) {
  1593. + struct rc32434_if_t * bif = &rc32434_iflist[i];
  1594. + if (bif->dev != NULL) {
  1595. + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
  1596. + if (lp != NULL) {
  1597. + if (lp->eth_regs)
  1598. + iounmap((void*)lp->eth_regs);
  1599. + if (lp->rx_dma_regs)
  1600. + iounmap((void*)lp->rx_dma_regs);
  1601. + if (lp->tx_dma_regs)
  1602. + iounmap((void*)lp->tx_dma_regs);
  1603. + if (lp->td_ring)
  1604. + kfree((void*)KSEG0ADDR(lp->td_ring));
  1605. +
  1606. +#ifdef RC32434_PROC_DEBUG
  1607. + if (lp->ps) {
  1608. + remove_proc_entry(bif->name, proc_net);
  1609. + }
  1610. +#endif
  1611. + kfree(lp);
  1612. + }
  1613. +
  1614. + unregister_netdev(bif->dev);
  1615. + free_netdev(bif->dev);
  1616. + kfree(bif->dev);
  1617. + }
  1618. + }
  1619. +}
  1620. +
  1621. +
  1622. +
  1623. +static int rc32434_open(struct net_device *dev)
  1624. +{
  1625. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  1626. +
  1627. + /* Initialize */
  1628. + if (rc32434_init(dev)) {
  1629. + ERR("Error: cannot open the Ethernet device\n");
  1630. + return -EAGAIN;
  1631. + }
  1632. +
  1633. + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
  1634. + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
  1635. + SA_SHIRQ | SA_INTERRUPT,
  1636. + "rc32434 ethernet Rx", dev)) {
  1637. + ERR(": unable to get Rx DMA IRQ %d\n",
  1638. + lp->rx_irq);
  1639. + return -EAGAIN;
  1640. + }
  1641. + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
  1642. + SA_SHIRQ | SA_INTERRUPT,
  1643. + "rc32434 ethernet Tx", dev)) {
  1644. + ERR(": unable to get Tx DMA IRQ %d\n",
  1645. + lp->tx_irq);
  1646. + free_irq(lp->rx_irq, dev);
  1647. + return -EAGAIN;
  1648. + }
  1649. +
  1650. +#ifdef RC32434_REVISION
  1651. + /* Install handler for overrun error. */
  1652. + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
  1653. + SA_SHIRQ | SA_INTERRUPT,
  1654. + "Ethernet Overflow", dev)) {
  1655. + ERR(": unable to get OVR IRQ %d\n",
  1656. + lp->ovr_irq);
  1657. + free_irq(lp->rx_irq, dev);
  1658. + free_irq(lp->tx_irq, dev);
  1659. + return -EAGAIN;
  1660. + }
  1661. +#endif
  1662. +
  1663. + /* Install handler for underflow error. */
  1664. + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
  1665. + SA_SHIRQ | SA_INTERRUPT,
  1666. + "Ethernet Underflow", dev)) {
  1667. + ERR(": unable to get UND IRQ %d\n",
  1668. + lp->und_irq);
  1669. + free_irq(lp->rx_irq, dev);
  1670. + free_irq(lp->tx_irq, dev);
  1671. +#ifdef RC32434_REVISION
  1672. + free_irq(lp->ovr_irq, dev);
  1673. +#endif
  1674. + return -EAGAIN;
  1675. + }
  1676. +
  1677. +
  1678. + return 0;
  1679. +}
  1680. +
  1681. +
  1682. +
  1683. +
  1684. +static int rc32434_close(struct net_device *dev)
  1685. +{
  1686. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  1687. + u32 tmp;
  1688. +
  1689. + /* Disable interrupts */
  1690. + disable_irq(lp->rx_irq);
  1691. + disable_irq(lp->tx_irq);
  1692. +#ifdef RC32434_REVISION
  1693. + disable_irq(lp->ovr_irq);
  1694. +#endif
  1695. + disable_irq(lp->und_irq);
  1696. +
  1697. + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
  1698. + tmp = tmp | DMASM_f_m | DMASM_e_m;
  1699. + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
  1700. +
  1701. + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
  1702. + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
  1703. + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
  1704. +
  1705. + free_irq(lp->rx_irq, dev);
  1706. + free_irq(lp->tx_irq, dev);
  1707. +#ifdef RC32434_REVISION
  1708. + free_irq(lp->ovr_irq, dev);
  1709. +#endif
  1710. + free_irq(lp->und_irq, dev);
  1711. + return 0;
  1712. +}
  1713. +
  1714. +
  1715. +/* transmit packet */
  1716. +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
  1717. +{
  1718. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  1719. + unsigned long flags;
  1720. + u32 length;
  1721. + DMAD_t td;
  1722. +
  1723. +
  1724. + spin_lock_irqsave(&lp->lock, flags);
  1725. +
  1726. + td = &lp->td_ring[lp->tx_chain_tail];
  1727. +
  1728. + /* stop queue when full, drop pkts if queue already full */
  1729. + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
  1730. + lp->tx_full = 1;
  1731. +
  1732. + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
  1733. + netif_stop_queue(dev);
  1734. + }
  1735. + else {
  1736. + lp->stats.tx_dropped++;
  1737. + dev_kfree_skb_any(skb);
  1738. + spin_unlock_irqrestore(&lp->lock, flags);
  1739. + return 1;
  1740. + }
  1741. + }
  1742. +
  1743. + lp->tx_count ++;
  1744. +
  1745. + lp->tx_skb[lp->tx_chain_tail] = skb;
  1746. +
  1747. + length = skb->len;
  1748. +
  1749. + /* Setup the transmit descriptor. */
  1750. + td->ca = CPHYSADDR(skb->data);
  1751. +
  1752. + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
  1753. + if( lp->tx_chain_status == empty ) {
  1754. + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
  1755. + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
  1756. + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
  1757. + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
  1758. + }
  1759. + else {
  1760. + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
  1761. + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
  1762. + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
  1763. + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
  1764. + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
  1765. + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
  1766. + lp->tx_chain_status = empty;
  1767. + }
  1768. + }
  1769. + else {
  1770. + if( lp->tx_chain_status == empty ) {
  1771. + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
  1772. + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
  1773. + lp->tx_chain_status = filled;
  1774. + }
  1775. + else {
  1776. + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
  1777. + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
  1778. + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
  1779. + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
  1780. + }
  1781. + }
  1782. +
  1783. + dev->trans_start = jiffies;
  1784. +
  1785. + spin_unlock_irqrestore(&lp->lock, flags);
  1786. +
  1787. + return 0;
  1788. +}
  1789. +
  1790. +
  1791. +/* Ethernet MII-PHY Handler */
  1792. +static void rc32434_mii_handler(unsigned long data)
  1793. +{
  1794. + struct net_device *dev = (struct net_device *)data;
  1795. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  1796. + unsigned long flags;
  1797. + unsigned long duplex_status;
  1798. + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
  1799. +
  1800. + spin_lock_irqsave(&lp->lock, flags);
  1801. +
  1802. + /* Two ports are using the same MII, the difference is the PHY address */
  1803. + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
  1804. + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
  1805. + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
  1806. + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
  1807. + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
  1808. +
  1809. + ERR("irq:%x port_addr:%x RDD:%x\n",
  1810. + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
  1811. + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
  1812. + if(duplex_status != lp->duplex_mode) {
  1813. + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
  1814. + lp->duplex_mode = duplex_status;
  1815. + rc32434_restart(dev);
  1816. + }
  1817. +
  1818. + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
  1819. + add_timer(&lp->mii_phy_timer);
  1820. +
  1821. + spin_unlock_irqrestore(&lp->lock, flags);
  1822. +
  1823. +}
  1824. +
  1825. +#ifdef RC32434_REVISION
  1826. +/* Ethernet Rx Overflow interrupt */
  1827. +static irqreturn_t
  1828. +rc32434_ovr_interrupt(int irq, void *dev_id)
  1829. +{
  1830. + struct net_device *dev = (struct net_device *)dev_id;
  1831. + struct rc32434_local *lp;
  1832. + unsigned int ovr;
  1833. + irqreturn_t retval = IRQ_NONE;
  1834. +
  1835. + ASSERT(dev != NULL);
  1836. +
  1837. + lp = (struct rc32434_local *)dev->priv;
  1838. + spin_lock(&lp->lock);
  1839. + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
  1840. +
  1841. + if(ovr & ETHINTFC_ovr_m) {
  1842. + netif_stop_queue(dev);
  1843. +
  1844. + /* clear OVR bit */
  1845. + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
  1846. +
  1847. + /* Restart interface */
  1848. + rc32434_restart(dev);
  1849. + retval = IRQ_HANDLED;
  1850. + }
  1851. + spin_unlock(&lp->lock);
  1852. +
  1853. + return retval;
  1854. +}
  1855. +
  1856. +#endif
  1857. +
  1858. +
  1859. +/* Ethernet Tx Underflow interrupt */
  1860. +static irqreturn_t
  1861. +rc32434_und_interrupt(int irq, void *dev_id)
  1862. +{
  1863. + struct net_device *dev = (struct net_device *)dev_id;
  1864. + struct rc32434_local *lp;
  1865. + unsigned int und;
  1866. + irqreturn_t retval = IRQ_NONE;
  1867. +
  1868. + ASSERT(dev != NULL);
  1869. +
  1870. + lp = (struct rc32434_local *)dev->priv;
  1871. +
  1872. + spin_lock(&lp->lock);
  1873. +
  1874. + und = rc32434_readl(&lp->eth_regs->ethintfc);
  1875. +
  1876. + if(und & ETHINTFC_und_m) {
  1877. + netif_stop_queue(dev);
  1878. +
  1879. + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
  1880. +
  1881. + /* Restart interface */
  1882. + rc32434_restart(dev);
  1883. + retval = IRQ_HANDLED;
  1884. + }
  1885. +
  1886. + spin_unlock(&lp->lock);
  1887. +
  1888. + return retval;
  1889. +}
  1890. +
  1891. +
  1892. +/* Ethernet Rx DMA interrupt */
  1893. +static irqreturn_t
  1894. +rc32434_rx_dma_interrupt(int irq, void *dev_id)
  1895. +{
  1896. + struct net_device *dev = (struct net_device *)dev_id;
  1897. + struct rc32434_local* lp;
  1898. + volatile u32 dmas,dmasm;
  1899. + irqreturn_t retval;
  1900. +
  1901. + ASSERT(dev != NULL);
  1902. +
  1903. + lp = (struct rc32434_local *)dev->priv;
  1904. +
  1905. + spin_lock(&lp->lock);
  1906. + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
  1907. + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
  1908. + /* Mask D H E bit in Rx DMA */
  1909. + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
  1910. + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
  1911. +#ifdef CONFIG_IDT_USE_NAPI
  1912. + if(netif_rx_schedule_prep(dev))
  1913. + __netif_rx_schedule(dev);
  1914. +#else
  1915. + tasklet_hi_schedule(lp->rx_tasklet);
  1916. +#endif
  1917. +
  1918. + if (dmas & DMAS_e_m)
  1919. + ERR(": DMA error\n");
  1920. +
  1921. + retval = IRQ_HANDLED;
  1922. + }
  1923. + else
  1924. + retval = IRQ_NONE;
  1925. +
  1926. + spin_unlock(&lp->lock);
  1927. + return retval;
  1928. +}
  1929. +
  1930. +#ifdef CONFIG_IDT_USE_NAPI
  1931. +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
  1932. +#else
  1933. +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
  1934. +#endif
  1935. +{
  1936. + struct net_device *dev = (struct net_device *)rx_data_dev;
  1937. + struct rc32434_local* lp = netdev_priv(dev);
  1938. + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
  1939. + struct sk_buff *skb, *skb_new;
  1940. + u8* pkt_buf;
  1941. + u32 devcs, count, pkt_len, pktuncrc_len;
  1942. + volatile u32 dmas;
  1943. +#ifdef CONFIG_IDT_USE_NAPI
  1944. + u32 received = 0;
  1945. + int rx_work_limit = min(*budget,dev->quota);
  1946. +#else
  1947. + unsigned long flags;
  1948. + spin_lock_irqsave(&lp->lock, flags);
  1949. +#endif
  1950. +
  1951. + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
  1952. +#ifdef CONFIG_IDT_USE_NAPI
  1953. + if(--rx_work_limit <0)
  1954. + {
  1955. + break;
  1956. + }
  1957. +#endif
  1958. + /* init the var. used for the later operations within the while loop */
  1959. + skb_new = NULL;
  1960. + devcs = rd->devcs;
  1961. + pkt_len = RCVPKT_LENGTH(devcs);
  1962. + skb = lp->rx_skb[lp->rx_next_done];
  1963. +
  1964. + if (count < 64) {
  1965. + lp->stats.rx_errors++;
  1966. + lp->stats.rx_dropped++;
  1967. + }
  1968. + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
  1969. + /* check that this is a whole packet */
  1970. + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
  1971. + lp->stats.rx_errors++;
  1972. + lp->stats.rx_dropped++;
  1973. + }
  1974. + else if ( (devcs & ETHRX_rok_m) ) {
  1975. +
  1976. + {
  1977. + /* must be the (first and) last descriptor then */
  1978. + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
  1979. +
  1980. + pktuncrc_len = pkt_len - 4;
  1981. + /* invalidate the cache */
  1982. + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
  1983. +
  1984. + /* Malloc up new buffer. */
  1985. + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
  1986. +
  1987. + if (skb_new != NULL){
  1988. + /* Make room */
  1989. + skb_put(skb, pktuncrc_len);
  1990. +
  1991. + skb->protocol = eth_type_trans(skb, dev);
  1992. +
  1993. + /* pass the packet to upper layers */
  1994. +#ifdef CONFIG_IDT_USE_NAPI
  1995. + netif_receive_skb(skb);
  1996. +#else
  1997. + netif_rx(skb);
  1998. +#endif
  1999. +
  2000. + dev->last_rx = jiffies;
  2001. + lp->stats.rx_packets++;
  2002. + lp->stats.rx_bytes += pktuncrc_len;
  2003. +
  2004. + if (IS_RCV_MP(devcs))
  2005. + lp->stats.multicast++;
  2006. +
  2007. + /* 16 bit align */
  2008. + skb_reserve(skb_new, 2);
  2009. +
  2010. + skb_new->dev = dev;
  2011. + lp->rx_skb[lp->rx_next_done] = skb_new;
  2012. + }
  2013. + else {
  2014. + ERR("no memory, dropping rx packet.\n");
  2015. + lp->stats.rx_errors++;
  2016. + lp->stats.rx_dropped++;
  2017. + }
  2018. + }
  2019. +
  2020. + }
  2021. + else {
  2022. + /* This should only happen if we enable accepting broken packets */
  2023. + lp->stats.rx_errors++;
  2024. + lp->stats.rx_dropped++;
  2025. +
  2026. + /* add statistics counters */
  2027. + if (IS_RCV_CRC_ERR(devcs)) {
  2028. + DBG(2, "RX CRC error\n");
  2029. + lp->stats.rx_crc_errors++;
  2030. + }
  2031. + else if (IS_RCV_LOR_ERR(devcs)) {
  2032. + DBG(2, "RX LOR error\n");
  2033. + lp->stats.rx_length_errors++;
  2034. + }
  2035. + else if (IS_RCV_LE_ERR(devcs)) {
  2036. + DBG(2, "RX LE error\n");
  2037. + lp->stats.rx_length_errors++;
  2038. + }
  2039. + else if (IS_RCV_OVR_ERR(devcs)) {
  2040. + lp->stats.rx_over_errors++;
  2041. + }
  2042. + else if (IS_RCV_CV_ERR(devcs)) {
  2043. + /* code violation */
  2044. + DBG(2, "RX CV error\n");
  2045. + lp->stats.rx_frame_errors++;
  2046. + }
  2047. + else if (IS_RCV_CES_ERR(devcs)) {
  2048. + DBG(2, "RX Preamble error\n");
  2049. + }
  2050. + }
  2051. +
  2052. + rd->devcs = 0;
  2053. +
  2054. + /* restore descriptor's curr_addr */
  2055. + if(skb_new)
  2056. + rd->ca = CPHYSADDR(skb_new->data);
  2057. + else
  2058. + rd->ca = CPHYSADDR(skb->data);
  2059. +
  2060. + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
  2061. + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
  2062. +
  2063. + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
  2064. + rd = &lp->rd_ring[lp->rx_next_done];
  2065. + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
  2066. + }
  2067. +#ifdef CONFIG_IDT_USE_NAPI
  2068. + dev->quota -= received;
  2069. + *budget =- received;
  2070. + if(rx_work_limit < 0)
  2071. + goto not_done;
  2072. +#endif
  2073. +
  2074. + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
  2075. +
  2076. + if(dmas & DMAS_h_m) {
  2077. + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
  2078. +#ifdef RC32434_PROC_DEBUG
  2079. + lp->dma_halt_cnt++;
  2080. +#endif
  2081. + rd->devcs = 0;
  2082. + skb = lp->rx_skb[lp->rx_next_done];
  2083. + rd->ca = CPHYSADDR(skb->data);
  2084. + rc32434_chain_rx(lp,rd);
  2085. + }
  2086. +
  2087. +#ifdef CONFIG_IDT_USE_NAPI
  2088. + netif_rx_complete(dev);
  2089. +#endif
  2090. + /* Enable D H E bit in Rx DMA */
  2091. + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
  2092. +#ifdef CONFIG_IDT_USE_NAPI
  2093. + return 0;
  2094. + not_done:
  2095. + return 1;
  2096. +#else
  2097. + spin_unlock_irqrestore(&lp->lock, flags);
  2098. + return;
  2099. +#endif
  2100. +
  2101. +
  2102. +}
  2103. +
  2104. +
  2105. +
  2106. +/* Ethernet Tx DMA interrupt */
  2107. +static irqreturn_t
  2108. +rc32434_tx_dma_interrupt(int irq, void *dev_id)
  2109. +{
  2110. + struct net_device *dev = (struct net_device *)dev_id;
  2111. + struct rc32434_local *lp;
  2112. + volatile u32 dmas,dmasm;
  2113. + irqreturn_t retval;
  2114. +
  2115. + ASSERT(dev != NULL);
  2116. +
  2117. + lp = (struct rc32434_local *)dev->priv;
  2118. +
  2119. + spin_lock(&lp->lock);
  2120. +
  2121. + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
  2122. +
  2123. + if (dmas & (DMAS_f_m | DMAS_e_m)) {
  2124. + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
  2125. + /* Mask F E bit in Tx DMA */
  2126. + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
  2127. +
  2128. + tasklet_hi_schedule(lp->tx_tasklet);
  2129. +
  2130. + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
  2131. + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
  2132. + lp->tx_chain_status = empty;
  2133. + lp->tx_chain_head = lp->tx_chain_tail;
  2134. + dev->trans_start = jiffies;
  2135. + }
  2136. +
  2137. + if (dmas & DMAS_e_m)
  2138. + ERR(": DMA error\n");
  2139. +
  2140. + retval = IRQ_HANDLED;
  2141. + }
  2142. + else
  2143. + retval = IRQ_NONE;
  2144. +
  2145. + spin_unlock(&lp->lock);
  2146. +
  2147. + return retval;
  2148. +}
  2149. +
  2150. +
  2151. +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
  2152. +{
  2153. + struct net_device *dev = (struct net_device *)tx_data_dev;
  2154. + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
  2155. + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
  2156. + u32 devcs;
  2157. + unsigned long flags;
  2158. + volatile u32 dmas;
  2159. +
  2160. + spin_lock_irqsave(&lp->lock, flags);
  2161. +
  2162. + /* process all desc that are done */
  2163. + while(IS_DMA_FINISHED(td->control)) {
  2164. + if(lp->tx_full == 1) {
  2165. + netif_wake_queue(dev);
  2166. + lp->tx_full = 0;
  2167. + }
  2168. +
  2169. + devcs = lp->td_ring[lp->tx_next_done].devcs;
  2170. + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
  2171. + lp->stats.tx_errors++;
  2172. + lp->stats.tx_dropped++;
  2173. +
  2174. + /* should never happen */
  2175. + DBG(1, __FUNCTION__ ": split tx ignored\n");
  2176. + }
  2177. + else if (IS_TX_TOK(devcs)) {
  2178. + lp->stats.tx_packets++;
  2179. + }
  2180. + else {
  2181. + lp->stats.tx_errors++;
  2182. + lp->stats.tx_dropped++;
  2183. +
  2184. + /* underflow */
  2185. + if (IS_TX_UND_ERR(devcs))
  2186. + lp->stats.tx_fifo_errors++;
  2187. +
  2188. + /* oversized frame */
  2189. + if (IS_TX_OF_ERR(devcs))
  2190. + lp->stats.tx_aborted_errors++;
  2191. +
  2192. + /* excessive deferrals */
  2193. + if (IS_TX_ED_ERR(devcs))
  2194. + lp->stats.tx_carrier_errors++;
  2195. +
  2196. + /* collisions: medium busy */
  2197. + if (IS_TX_EC_ERR(devcs))
  2198. + lp->stats.collisions++;
  2199. +
  2200. + /* late collision */
  2201. + if (IS_TX_LC_ERR(devcs))
  2202. + lp->stats.tx_window_errors++;
  2203. +
  2204. + }
  2205. +
  2206. + /* We must always free the original skb */
  2207. + if (lp->tx_skb[lp->tx_next_done] != NULL) {
  2208. + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
  2209. + lp->tx_skb[lp->tx_next_done] = NULL;
  2210. + }
  2211. +
  2212. + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
  2213. + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
  2214. + lp->td_ring[lp->tx_next_done].link = 0;
  2215. + lp->td_ring[lp->tx_next_done].ca = 0;
  2216. + lp->tx_count --;
  2217. +
  2218. + /* go on to next transmission */
  2219. + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
  2220. + td = &lp->td_ring[lp->tx_next_done];
  2221. +
  2222. + }
  2223. +
  2224. + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
  2225. + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
  2226. +
  2227. + /* Enable F E bit in Tx DMA */
  2228. + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
  2229. + spin_unlock_irqrestore(&lp->lock, flags);
  2230. +
  2231. +}
  2232. +
  2233. +
  2234. +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
  2235. +{
  2236. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  2237. + return &lp->stats;
  2238. +}
  2239. +
  2240. +
  2241. +/*
  2242. + * Set or clear the multicast filter for this adaptor.
  2243. + */
  2244. +static void rc32434_multicast_list(struct net_device *dev)
  2245. +{
  2246. + /* listen to broadcasts always and to treat */
  2247. + /* IFF bits independantly */
  2248. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  2249. + unsigned long flags;
  2250. + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
  2251. +
  2252. + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
  2253. + recognise |= ETHARC_pro_m;
  2254. +
  2255. + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
  2256. + recognise |= ETHARC_am_m; /* all multicast & bcast */
  2257. + else if (dev->mc_count > 0) {
  2258. + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
  2259. + recognise |= ETHARC_am_m; /* for the time being */
  2260. + }
  2261. +
  2262. + spin_lock_irqsave(&lp->lock, flags);
  2263. + rc32434_writel(recognise, &lp->eth_regs->etharc);
  2264. + spin_unlock_irqrestore(&lp->lock, flags);
  2265. +}
  2266. +
  2267. +
  2268. +static void rc32434_tx_timeout(struct net_device *dev)
  2269. +{
  2270. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  2271. + unsigned long flags;
  2272. +
  2273. + spin_lock_irqsave(&lp->lock, flags);
  2274. + rc32434_restart(dev);
  2275. + spin_unlock_irqrestore(&lp->lock, flags);
  2276. +
  2277. +}
  2278. +
  2279. +
  2280. +/*
  2281. + * Initialize the RC32434 ethernet controller.
  2282. + */
  2283. +static int rc32434_init(struct net_device *dev)
  2284. +{
  2285. + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  2286. + int i, j;
  2287. +
  2288. + /* Disable DMA */
  2289. + rc32434_abort_tx(dev);
  2290. + rc32434_abort_rx(dev);
  2291. +
  2292. + /* reset ethernet logic */
  2293. + rc32434_writel(0, &lp->eth_regs->ethintfc);
  2294. + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
  2295. + dev->trans_start = jiffies;
  2296. +
  2297. + /* Enable Ethernet Interface */
  2298. + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
  2299. +
  2300. +#ifndef CONFIG_IDT_USE_NAPI
  2301. + tasklet_disable(lp->rx_tasklet);
  2302. +#endif
  2303. + tasklet_disable(lp->tx_tasklet);
  2304. +
  2305. + /* Initialize the transmit Descriptors */
  2306. + for (i = 0; i < RC32434_NUM_TDS; i++) {
  2307. + lp->td_ring[i].control = DMAD_iof_m;
  2308. + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
  2309. + lp->td_ring[i].ca = 0;
  2310. + lp->td_ring[i].link = 0;
  2311. + if (lp->tx_skb[i] != NULL) {
  2312. + dev_kfree_skb_any(lp->tx_skb[i]);
  2313. + lp->tx_skb[i] = NULL;
  2314. + }
  2315. + }
  2316. + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
  2317. + lp-> tx_chain_status = empty;
  2318. +
  2319. + /*
  2320. + * Initialize the receive descriptors so that they
  2321. + * become a circular linked list, ie. let the last
  2322. + * descriptor point to the first again.
  2323. + */
  2324. + for (i=0; i<RC32434_NUM_RDS; i++) {
  2325. + struct sk_buff *skb = lp->rx_skb[i];
  2326. +
  2327. + if (lp->rx_skb[i] == NULL) {
  2328. + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
  2329. + if (skb == NULL) {
  2330. + ERR("No memory in the system\n");
  2331. + for (j = 0; j < RC32434_NUM_RDS; j ++)
  2332. + if (lp->rx_skb[j] != NULL)
  2333. + dev_kfree_skb_any(lp->rx_skb[j]);
  2334. +
  2335. + return 1;
  2336. + }
  2337. + else {
  2338. + skb->dev = dev;
  2339. + skb_reserve(skb, 2);
  2340. + lp->rx_skb[i] = skb;
  2341. + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
  2342. +
  2343. + }
  2344. + }
  2345. + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
  2346. + lp->rd_ring[i].devcs = 0;
  2347. + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
  2348. + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
  2349. +
  2350. + }
  2351. + /* loop back */
  2352. + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
  2353. + lp->rx_next_done = 0;
  2354. +
  2355. + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
  2356. + lp->rx_chain_head = 0;
  2357. + lp->rx_chain_tail = 0;
  2358. + lp->rx_chain_status = empty;
  2359. +
  2360. + rc32434_writel(0, &lp->rx_dma_regs->dmas);
  2361. + /* Start Rx DMA */
  2362. + rc32434_start_rx(lp, &lp->rd_ring[0]);
  2363. +
  2364. + /* Enable F E bit in Tx DMA */
  2365. + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
  2366. + /* Enable D H E bit in Rx DMA */
  2367. + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
  2368. +
  2369. + /* Accept only packets destined for this Ethernet device address */
  2370. + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
  2371. +
  2372. + /* Set all Ether station address registers to their initial values */
  2373. + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
  2374. + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
  2375. +
  2376. + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
  2377. + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
  2378. +
  2379. + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
  2380. + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
  2381. +
  2382. + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
  2383. + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
  2384. +
  2385. +
  2386. + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
  2387. + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
  2388. + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
  2389. +
  2390. + /* Back to back inter-packet-gap */
  2391. + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
  2392. + /* Non - Back to back inter-packet-gap */
  2393. + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
  2394. +
  2395. + /* Management Clock Prescaler Divisor */
  2396. + /* Clock independent setting */
  2397. + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
  2398. + &lp->eth_regs->ethmcp);
  2399. +
  2400. + /* don't transmit until fifo contains 48b */
  2401. + rc32434_writel(48, &lp->eth_regs->ethfifott);
  2402. +
  2403. + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
  2404. +
  2405. +#ifndef CONFIG_IDT_USE_NAPI
  2406. + tasklet_enable(lp->rx_tasklet);
  2407. +#endif
  2408. + tasklet_enable(lp->tx_tasklet);
  2409. +
  2410. + netif_start_queue(dev);
  2411. +
  2412. +
  2413. + return 0;
  2414. +
  2415. +}
  2416. +
  2417. +
  2418. +#ifndef MODULE
  2419. +
  2420. +static int __init rc32434_setup(char *options)
  2421. +{
  2422. + /* no options yet */
  2423. + return 1;
  2424. +}
  2425. +
  2426. +static int __init rc32434_setup_ethaddr0(char *options)
  2427. +{
  2428. + memcpy(mac0, options, 17);
  2429. + mac0[17]= '\0';
  2430. + return 1;
  2431. +}
  2432. +
  2433. +__setup("rc32434eth=", rc32434_setup);
  2434. +__setup("ethaddr0=", rc32434_setup_ethaddr0);
  2435. +
  2436. +
  2437. +#endif /* MODULE */
  2438. +
  2439. +module_init(rc32434_init_module);
  2440. +module_exit(rc32434_cleanup_module);
  2441. +
  2442. +
  2443. +
  2444. +
  2445. +
  2446. +
  2447. +
  2448. +
  2449. +
  2450. +
  2451. +
  2452. +
  2453. +
  2454. +
  2455. diff -Nur linux-2.6.21.5-pristine/drivers/net/rc32434_eth.h linux-2.6.21.5/drivers/net/rc32434_eth.h
  2456. --- linux-2.6.21.5-pristine/drivers/net/rc32434_eth.h 1969-12-31 19:00:00.000000000 -0500
  2457. +++ linux-2.6.21.5/drivers/net/rc32434_eth.h 2007-09-20 00:16:52.000000000 -0400
  2458. @@ -0,0 +1,187 @@
  2459. +/**************************************************************************
  2460. + *
  2461. + * BRIEF MODULE DESCRIPTION
  2462. + * Definitions for IDT RC32434 on-chip ethernet controller.
  2463. + *
  2464. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  2465. + *
  2466. + * This program is free software; you can redistribute it and/or modify it
  2467. + * under the terms of the GNU General Public License as published by the
  2468. + * Free Software Foundation; either version 2 of the License, or (at your
  2469. + * option) any later version.
  2470. + *
  2471. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  2472. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  2473. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  2474. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  2475. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  2476. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  2477. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  2478. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  2479. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  2480. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  2481. + *
  2482. + * You should have received a copy of the GNU General Public License along
  2483. + * with this program; if not, write to the Free Software Foundation, Inc.,
  2484. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  2485. + *
  2486. + *
  2487. + **************************************************************************
  2488. + * May 2004 rkt, neb
  2489. + *
  2490. + * Initial Release
  2491. + *
  2492. + * Aug 2004
  2493. + *
  2494. + * Added NAPI
  2495. + *
  2496. + **************************************************************************
  2497. + */
  2498. +
  2499. +
  2500. +#include <asm/idt-boards/rc32434/rc32434.h>
  2501. +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
  2502. +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
  2503. +
  2504. +#define RC32434_DEBUG 2
  2505. +//#define RC32434_PROC_DEBUG
  2506. +#undef RC32434_DEBUG
  2507. +
  2508. +#ifdef RC32434_DEBUG
  2509. +
  2510. +/* use 0 for production, 1 for verification, >2 for debug */
  2511. +static int rc32434_debug = RC32434_DEBUG;
  2512. +#define ASSERT(expr) \
  2513. + if(!(expr)) { \
  2514. + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  2515. + #expr,__FILE__,__FUNCTION__,__LINE__); }
  2516. +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
  2517. +#else
  2518. +#define ASSERT(expr) do {} while (0)
  2519. +#define DBG(lvl, format, arg...) do {} while (0)
  2520. +#endif
  2521. +
  2522. +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
  2523. +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
  2524. +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
  2525. +
  2526. +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
  2527. +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
  2528. +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
  2529. +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
  2530. +
  2531. +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
  2532. +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
  2533. +
  2534. +/* the following must be powers of two */
  2535. +#ifdef CONFIG_IDT_USE_NAPI
  2536. +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
  2537. +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
  2538. +#else
  2539. +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
  2540. +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
  2541. +#endif
  2542. +
  2543. +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
  2544. +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
  2545. +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
  2546. +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
  2547. +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
  2548. +
  2549. +#define RC32434_TX_TIMEOUT HZ * 100
  2550. +
  2551. +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
  2552. +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
  2553. +
  2554. +enum status { filled, empty};
  2555. +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
  2556. +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
  2557. +
  2558. +
  2559. +/* Information that need to be kept for each board. */
  2560. +struct rc32434_local {
  2561. + ETH_t eth_regs;
  2562. + DMA_Chan_t rx_dma_regs;
  2563. + DMA_Chan_t tx_dma_regs;
  2564. + volatile DMAD_t td_ring; /* transmit descriptor ring */
  2565. + volatile DMAD_t rd_ring; /* receive descriptor ring */
  2566. +
  2567. + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
  2568. + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
  2569. +
  2570. +#ifndef CONFIG_IDT_USE_NAPI
  2571. + struct tasklet_struct * rx_tasklet;
  2572. +#endif
  2573. + struct tasklet_struct * tx_tasklet;
  2574. +
  2575. + int rx_next_done;
  2576. + int rx_chain_head;
  2577. + int rx_chain_tail;
  2578. + enum status rx_chain_status;
  2579. +
  2580. + int tx_next_done;
  2581. + int tx_chain_head;
  2582. + int tx_chain_tail;
  2583. + enum status tx_chain_status;
  2584. + int tx_count;
  2585. + int tx_full;
  2586. +
  2587. + struct timer_list mii_phy_timer;
  2588. + unsigned long duplex_mode;
  2589. +
  2590. + int rx_irq;
  2591. + int tx_irq;
  2592. + int ovr_irq;
  2593. + int und_irq;
  2594. +
  2595. + struct net_device_stats stats;
  2596. + spinlock_t lock;
  2597. +
  2598. + /* debug /proc entry */
  2599. + struct proc_dir_entry *ps;
  2600. + int dma_halt_cnt; int dma_run_cnt;
  2601. +};
  2602. +
  2603. +extern unsigned int idt_cpu_freq;
  2604. +
  2605. +/* Index to functions, as function prototypes. */
  2606. +static int rc32434_open(struct net_device *dev);
  2607. +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
  2608. +static void rc32434_mii_handler(unsigned long data);
  2609. +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id);
  2610. +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id);
  2611. +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id);
  2612. +#ifdef RC32434_REVISION
  2613. +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id);
  2614. +#endif
  2615. +static int rc32434_close(struct net_device *dev);
  2616. +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
  2617. +static void rc32434_multicast_list(struct net_device *dev);
  2618. +static int rc32434_init(struct net_device *dev);
  2619. +static void rc32434_tx_timeout(struct net_device *dev);
  2620. +
  2621. +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
  2622. +#ifdef CONFIG_IDT_USE_NAPI
  2623. +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
  2624. +#else
  2625. +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
  2626. +#endif
  2627. +static void rc32434_cleanup_module(void);
  2628. +static int rc32434_probe(int port_num);
  2629. +int rc32434_init_module(void);
  2630. +
  2631. +
  2632. +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
  2633. +{
  2634. + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
  2635. + rc32434_writel(0x10, &ch->dmac);
  2636. +
  2637. + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
  2638. + dev->trans_start = jiffies;
  2639. +
  2640. + rc32434_writel(0, &ch->dmas);
  2641. + }
  2642. +
  2643. + rc32434_writel(0, &ch->dmadptr);
  2644. + rc32434_writel(0, &ch->dmandptr);
  2645. +}
  2646. --- a/arch/mips/include/asm/bootinfo.h
  2647. +++ b/arch/mips/include/asm/bootinfo.h
  2648. @@ -57,6 +57,16 @@
  2649. #define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
  2650. #define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
  2651.  
  2652. +/*
  2653. + * Valid machtype for group ARUBA
  2654. + */
  2655. +#define MACH_GROUP_ARUBA 23
  2656. +#define MACH_ARUBA_UNKNOWN 0
  2657. +#define MACH_ARUBA_AP60 1
  2658. +#define MACH_ARUBA_AP65 2
  2659. +#define MACH_ARUBA_AP70 3
  2660. +#define MACH_ARUBA_AP40 4
  2661. +
  2662. #define CL_SIZE COMMAND_LINE_SIZE
  2663.  
  2664. extern char *system_type;
  2665. --- a/arch/mips/include/asm/cpu.h
  2666. +++ b/arch/mips/include/asm/cpu.h
  2667. @@ -55,6 +55,9 @@
  2668. #define PRID_IMP_R14000 0x0f00
  2669. #define PRID_IMP_R8000 0x1000
  2670. #define PRID_IMP_PR4450 0x1200
  2671. +#define PRID_IMP_RC32334 0x1800
  2672. +#define PRID_IMP_RC32355 0x1900
  2673. +#define PRID_IMP_RC32365 0x1900
  2674. #define PRID_IMP_R4600 0x2000
  2675. #define PRID_IMP_R4700 0x2100
  2676. #define PRID_IMP_TX39 0x2200
  2677. @@ -211,12 +214,14 @@
  2678. CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
  2679. CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
  2680.  
  2681. + CPU_RC32300,
  2682. +
  2683. /*
  2684. * MIPS64 class processors
  2685. */
  2686. CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
  2687. CPU_CAVIUM_OCTEON,
  2688. -
  2689. +
  2690. CPU_LAST
  2691. };
  2692.  
  2693. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32300.h 1969-12-31 19:00:00.000000000 -0500
  2694. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32300.h 2007-09-20 00:16:52.000000000 -0400
  2695. @@ -0,0 +1,142 @@
  2696. +/**************************************************************************
  2697. + *
  2698. + * BRIEF MODULE DESCRIPTION
  2699. + * RC32300 helper routines
  2700. + *
  2701. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  2702. + *
  2703. + * This program is free software; you can redistribute it and/or modify it
  2704. + * under the terms of the GNU General Public License as published by the
  2705. + * Free Software Foundation; either version 2 of the License, or (at your
  2706. + * option) any later version.
  2707. + *
  2708. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  2709. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  2710. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  2711. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  2712. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  2713. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  2714. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  2715. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  2716. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  2717. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  2718. + *
  2719. + * You should have received a copy of the GNU General Public License along
  2720. + * with this program; if not, write to the Free Software Foundation, Inc.,
  2721. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  2722. + *
  2723. + *
  2724. + **************************************************************************
  2725. + * May 2004 P. Sadik.
  2726. + *
  2727. + * Initial Release
  2728. + *
  2729. + *
  2730. + *
  2731. + **************************************************************************
  2732. + */
  2733. +
  2734. +#ifndef __IDT_RC32300_H__
  2735. +#define __IDT_RC32300_H__
  2736. +
  2737. +#include <linux/delay.h>
  2738. +#include <asm/io.h>
  2739. +
  2740. +
  2741. +/* cpu pipeline flush */
  2742. +static inline void rc32300_sync(void)
  2743. +{
  2744. + __asm__ volatile ("sync");
  2745. +}
  2746. +
  2747. +static inline void rc32300_sync_udelay(int us)
  2748. +{
  2749. + __asm__ volatile ("sync");
  2750. + udelay(us);
  2751. +}
  2752. +
  2753. +static inline void rc32300_sync_delay(int ms)
  2754. +{
  2755. + __asm__ volatile ("sync");
  2756. + mdelay(ms);
  2757. +}
  2758. +
  2759. +/*
  2760. + * Macros to access internal RC32300 registers. No byte
  2761. + * swapping should be done when accessing the internal
  2762. + * registers.
  2763. + */
  2764. +
  2765. +static inline u8 rc32300_readb(unsigned long pa)
  2766. +{
  2767. + return *((volatile u8 *)KSEG1ADDR(pa));
  2768. +}
  2769. +static inline u16 rc32300_readw(unsigned long pa)
  2770. +{
  2771. + return *((volatile u16 *)KSEG1ADDR(pa));
  2772. +}
  2773. +static inline u32 rc32300_readl(unsigned long pa)
  2774. +{
  2775. + return *((volatile u32 *)KSEG1ADDR(pa));
  2776. +}
  2777. +static inline void rc32300_writeb(u8 val, unsigned long pa)
  2778. +{
  2779. + *((volatile u8 *)KSEG1ADDR(pa)) = val;
  2780. +}
  2781. +static inline void rc32300_writew(u16 val, unsigned long pa)
  2782. +{
  2783. + *((volatile u16 *)KSEG1ADDR(pa)) = val;
  2784. +}
  2785. +static inline void rc32300_writel(u32 val, unsigned long pa)
  2786. +{
  2787. + *((volatile u32 *)KSEG1ADDR(pa)) = val;
  2788. +}
  2789. +
  2790. +
  2791. +#define local_readb __raw_readb
  2792. +#define local_readw __raw_readw
  2793. +#define local_readl __raw_readl
  2794. +
  2795. +#define local_writeb __raw_writeb
  2796. +#define local_writew __raw_writew
  2797. +#define local_writel __raw_writel
  2798. +
  2799. +
  2800. +/*
  2801. + * C access to CLZ and CLO instructions
  2802. + * (count leading zeroes/ones).
  2803. + */
  2804. +static inline int rc32300_clz(unsigned long val)
  2805. +{
  2806. + int ret;
  2807. + __asm__ volatile (
  2808. + ".set\tnoreorder\n\t"
  2809. + ".set\tnoat\n\t"
  2810. + ".set\tmips32\n\t"
  2811. + "clz\t%0,%1\n\t"
  2812. + ".set\tmips0\n\t"
  2813. + ".set\tat\n\t"
  2814. + ".set\treorder"
  2815. + : "=r" (ret)
  2816. + : "r" (val));
  2817. +
  2818. + return ret;
  2819. +}
  2820. +static inline int rc32300_clo(unsigned long val)
  2821. +{
  2822. + int ret;
  2823. + __asm__ volatile (
  2824. + ".set\tnoreorder\n\t"
  2825. + ".set\tnoat\n\t"
  2826. + ".set\tmips32\n\t"
  2827. + "clo\t%0,%1\n\t"
  2828. + ".set\tmips0\n\t"
  2829. + ".set\tat\n\t"
  2830. + ".set\treorder"
  2831. + : "=r" (ret)
  2832. + : "r" (val));
  2833. +
  2834. + return ret;
  2835. +}
  2836. +
  2837. +#endif // __IDT_RC32300_H__
  2838. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32334.h
  2839. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32334.h 1969-12-31 19:00:00.000000000 -0500
  2840. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32334.h 2007-09-20 00:16:52.000000000 -0400
  2841. @@ -0,0 +1,207 @@
  2842. +/**************************************************************************
  2843. + *
  2844. + * BRIEF MODULE DESCRIPTION
  2845. + * Definitions for IDT RC32334 CPU.
  2846. + *
  2847. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  2848. + *
  2849. + * This program is free software; you can redistribute it and/or modify it
  2850. + * under the terms of the GNU General Public License as published by the
  2851. + * Free Software Foundation; either version 2 of the License, or (at your
  2852. + * option) any later version.
  2853. + *
  2854. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  2855. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  2856. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  2857. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  2858. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  2859. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  2860. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  2861. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  2862. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  2863. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  2864. + *
  2865. + * You should have received a copy of the GNU General Public License along
  2866. + * with this program; if not, write to the Free Software Foundation, Inc.,
  2867. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  2868. + *
  2869. + *
  2870. + **************************************************************************
  2871. + * May 2004 P. Sadik.
  2872. + *
  2873. + * Initial Release
  2874. + *
  2875. + *
  2876. + *
  2877. + **************************************************************************
  2878. + */
  2879. +
  2880. +
  2881. +#ifndef __IDT_RC32334_H__
  2882. +#define __IDT_RC32334_H__
  2883. +
  2884. +#include <linux/delay.h>
  2885. +#include <asm/io.h>
  2886. +
  2887. +/* Base address of internal registers */
  2888. +#define RC32334_REG_BASE 0x18000000
  2889. +
  2890. +/* CPU and IP Bus Control */
  2891. +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
  2892. +#define CPU_BTA 0xffffe204 // virtual!
  2893. +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
  2894. +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
  2895. +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
  2896. +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
  2897. +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
  2898. +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
  2899. +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
  2900. +
  2901. +/* Memory Controller */
  2902. +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
  2903. +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
  2904. +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
  2905. +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
  2906. +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
  2907. +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
  2908. +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
  2909. +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
  2910. +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
  2911. +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
  2912. +
  2913. +/* PCI Controller */
  2914. +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
  2915. +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
  2916. +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
  2917. +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
  2918. +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
  2919. +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
  2920. +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
  2921. +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
  2922. +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
  2923. +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
  2924. +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
  2925. +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
  2926. +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
  2927. +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
  2928. +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
  2929. +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
  2930. +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
  2931. +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
  2932. +
  2933. +/* Timers */
  2934. +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
  2935. +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
  2936. +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
  2937. +#define TIMER_REG_OFFSET 0x10
  2938. +
  2939. +/* Programmable I/O */
  2940. +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
  2941. +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
  2942. +
  2943. +/*
  2944. + * DMA
  2945. + *
  2946. + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
  2947. + *
  2948. + * DMA0: 18001400
  2949. + * DMA1: 18001440
  2950. + * DMA2: 18001900
  2951. + * DMA3: 18001940
  2952. + * NB: dma number must be immediate value or variable.
  2953. + * It MUST NOT be a function since it would get called twice!
  2954. + */
  2955. +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
  2956. +
  2957. +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
  2958. +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
  2959. +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
  2960. +
  2961. +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
  2962. +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
  2963. +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
  2964. +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
  2965. +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
  2966. +
  2967. +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
  2968. +
  2969. +/* Expansion Interrupt Controller */
  2970. +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
  2971. +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
  2972. +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
  2973. +#define IC_GROUP_OFFSET 0x10
  2974. +
  2975. +#define NUM_INTR_GROUPS 15
  2976. +/*
  2977. + * The IRQ mapping is as follows:
  2978. + *
  2979. + * IRQ Mapped To
  2980. + * --- -------------------
  2981. + * 0 SW0 (IP0) SW0 intr
  2982. + * 1 SW1 (IP1) SW1 intr
  2983. + * 2 Int0 (IP2) board-specific
  2984. + * 3 Int1 (IP3) board-specific
  2985. + * 4 Int2 (IP4) board-specific
  2986. + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
  2987. + * 6 Int4 (IP6) board-specific
  2988. + * 7 Int5 (IP7) CP0 Timer
  2989. + *
  2990. + * IRQ's 8 and up are all mapped to Int3 (IP5), which
  2991. + * internally on the RC32334 is routed to the Expansion
  2992. + * Interrupt Controller.
  2993. + */
  2994. +#define MIPS_CPU_TIMER_IRQ 7
  2995. +
  2996. +#define GROUP1_IRQ_BASE 8 // bus error
  2997. +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
  2998. +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
  2999. +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
  3000. +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
  3001. +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
  3002. +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
  3003. +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
  3004. +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
  3005. +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
  3006. +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
  3007. +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
  3008. +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
  3009. +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
  3010. +
  3011. +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
  3012. +
  3013. +/* 16550 UARTs */
  3014. +#ifdef __MIPSEB__
  3015. +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
  3016. +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
  3017. +#else
  3018. +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
  3019. +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
  3020. +#endif
  3021. +
  3022. +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
  3023. +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
  3024. +
  3025. +#define IDT_CLOCK_MULT 2
  3026. +
  3027. +/* NVRAM */
  3028. +#define NVRAM_BASE 0x12000000
  3029. +#define NVRAM_ENVSIZE_OFF 4
  3030. +#define NVRAM_ENVSTART_OFF 0x40
  3031. +
  3032. +/* LCD 4-digit display */
  3033. +#define LCD_CLEAR 0x14000400
  3034. +#define LCD_DIGIT0 0x1400000f
  3035. +#define LCD_DIGIT1 0x14000008
  3036. +#define LCD_DIGIT2 0x14000007
  3037. +#define LCD_DIGIT3 0x14000003
  3038. +
  3039. +/* Interrupts routed on 79S334A board (see rc32334.h) */
  3040. +#define RC32334_SCC8530_IRQ 2
  3041. +#define RC32334_PCI_INTA_IRQ 3
  3042. +#define RC32334_PCI_INTB_IRQ 4
  3043. +#define RC32334_PCI_INTC_IRQ 6
  3044. +#define RC32334_PCI_INTD_IRQ 7
  3045. +
  3046. +#define RAM_SIZE (32*1024*1024)
  3047. +
  3048. +#endif // __IDT_RC32334_H__
  3049. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32355.h
  3050. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32355.h 1969-12-31 19:00:00.000000000 -0500
  3051. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32355.h 2007-09-20 00:16:52.000000000 -0400
  3052. @@ -0,0 +1,177 @@
  3053. +/**************************************************************************
  3054. + *
  3055. + * BRIEF MODULE DESCRIPTION
  3056. + * Definitions for IDT RC32355 CPU.
  3057. + *
  3058. + * Copyright 2004 IDT Inc.
  3059. + * Author: Integrated Device Technology Inc. rischelp@idt.com
  3060. + *
  3061. + *
  3062. + * This program is free software; you can redistribute it and/or modify it
  3063. + * under the terms of the GNU General Public License as published by the
  3064. + * Free Software Foundation; either version 2 of the License, or (at your
  3065. + * option) any later version.
  3066. + *
  3067. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  3068. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  3069. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  3070. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  3071. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  3072. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  3073. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  3074. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  3075. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  3076. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  3077. + *
  3078. + * You should have received a copy of the GNU General Public License along
  3079. + * with this program; if not, write to the Free Software Foundation, Inc.,
  3080. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  3081. + *
  3082. + *
  3083. + * May 2004 rkt
  3084. + * Initial Release
  3085. + *
  3086. + **************************************************************************
  3087. + */
  3088. +
  3089. +
  3090. +#ifndef _RC32355_H_
  3091. +#define _RC32355_H_
  3092. +
  3093. +#include <linux/delay.h>
  3094. +#include <asm/io.h>
  3095. +
  3096. +/* Base address of internal registers */
  3097. +#define RC32355_REG_BASE 0x18000000
  3098. +
  3099. +/* System ID Registers */
  3100. +#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
  3101. +#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
  3102. +#define CPU_REV (RC32355_REG_BASE + 0x0002c)
  3103. +
  3104. +/* Reset Controller */
  3105. +#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
  3106. +
  3107. +/* Device Controller */
  3108. +#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
  3109. +#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
  3110. +#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
  3111. +#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
  3112. +#define DEV_REG_OFFSET 0x10
  3113. +
  3114. +/* SDRAM Controller */
  3115. +#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
  3116. +#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
  3117. +#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
  3118. +#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
  3119. +#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
  3120. +
  3121. +/* Bus Arbiter */
  3122. +#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
  3123. +#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
  3124. +
  3125. +/* Counters/Timers */
  3126. +#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
  3127. +#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
  3128. +#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
  3129. +#define TIMER_REG_OFFSET 0x0C
  3130. +
  3131. +/* System Integrity */
  3132. +
  3133. +/* Interrupt Controller */
  3134. +#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
  3135. +#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
  3136. +#define IC_GROUP_OFFSET 0x08
  3137. +
  3138. +#define NUM_INTR_GROUPS 5
  3139. +/*
  3140. + * The IRQ mapping is as follows:
  3141. + *
  3142. + * IRQ Mapped To
  3143. + * --- -------------------
  3144. + * 0 SW0 (IP0) SW0 intr
  3145. + * 1 SW1 (IP1) SW1 intr
  3146. + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
  3147. + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
  3148. + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
  3149. + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
  3150. + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
  3151. + * 7 Int5 (IP7) CP0 Timer
  3152. + *
  3153. + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
  3154. + * internally on the RC32355 is routed to the Expansion
  3155. + * Interrupt Controller.
  3156. + */
  3157. +#define MIPS_CPU_TIMER_IRQ 7
  3158. +
  3159. +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
  3160. +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
  3161. +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
  3162. +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
  3163. +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
  3164. +
  3165. +#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
  3166. +
  3167. +/* DMA - see rc32355_dma.h for full list of registers */
  3168. +
  3169. +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
  3170. +#define DMA_CHAN_OFFSET 0x14
  3171. +
  3172. +/* GPIO Controller */
  3173. +
  3174. +/* TDM Bus */
  3175. +
  3176. +/* 16550 UARTs */
  3177. +#ifdef __MIPSEB__
  3178. +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
  3179. +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
  3180. +#else
  3181. +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
  3182. +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
  3183. +#endif
  3184. +
  3185. +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
  3186. +#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
  3187. +
  3188. +/* ATM */
  3189. +
  3190. +/* Ethernet - see rc32355_eth.h for full list of registers */
  3191. +
  3192. +#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
  3193. +
  3194. +
  3195. +#define IDT_CLOCK_MULT 2
  3196. +
  3197. +/* Memory map of 79EB355 board */
  3198. +
  3199. +/* DRAM */
  3200. +#define RAM_BASE 0x00000000
  3201. +#define RAM_SIZE (32*1024*1024)
  3202. +
  3203. +/* SRAM (device 1) */
  3204. +#define SRAM_BASE 0x02000000
  3205. +#define SRAM_SIZE 0x00100000
  3206. +
  3207. +/* FLASH (device 2) */
  3208. +#define FLASH_BASE 0x0C000000
  3209. +#define FLASH_SIZE 0x00C00000
  3210. +
  3211. +/* ATM PHY (device 4) */
  3212. +#define ATM_PHY_BASE 0x14000000
  3213. +
  3214. +/* TDM switch (device 3) */
  3215. +#define TDM_BASE 0x1A000000
  3216. +
  3217. +/* LCD panel (device 3) */
  3218. +#define LCD_BASE 0x1A002000
  3219. +
  3220. +/* RTC (DS1511W) (device 3) */
  3221. +#define RTC_BASE 0x1A004000
  3222. +
  3223. +/* NVRAM (256 bytes internal to the DS1511 RTC) */
  3224. +#define NVRAM_ADDR RTC_BASE + 0x10
  3225. +#define NVRAM_DATA RTC_BASE + 0x13
  3226. +#define NVRAM_ENVSIZE_OFF 4
  3227. +#define NVRAM_ENVSTART_OFF 32
  3228. +
  3229. +#endif /* _RC32355_H_ */
  3230. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
  3231. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1969-12-31 19:00:00.000000000 -0500
  3232. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2007-09-20 00:16:52.000000000 -0400
  3233. @@ -0,0 +1,206 @@
  3234. +/**************************************************************************
  3235. + *
  3236. + * BRIEF MODULE DESCRIPTION
  3237. + * DMA controller defines on IDT RC32355
  3238. + *
  3239. + * Copyright 2004 IDT Inc.
  3240. + * Author: Integrated Device Technology Inc. rischelp@idt.com
  3241. + *
  3242. + *
  3243. + * This program is free software; you can redistribute it and/or modify it
  3244. + * under the terms of the GNU General Public License as published by the
  3245. + * Free Software Foundation; either version 2 of the License, or (at your
  3246. + * option) any later version.
  3247. + *
  3248. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  3249. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  3250. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  3251. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  3252. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  3253. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  3254. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  3255. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  3256. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  3257. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  3258. + *
  3259. + * You should have received a copy of the GNU General Public License along
  3260. + * with this program; if not, write to the Free Software Foundation, Inc.,
  3261. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  3262. + *
  3263. + *
  3264. + * May 2004 rkt
  3265. + * Initial Release
  3266. + *
  3267. + **************************************************************************
  3268. + */
  3269. +
  3270. +#ifndef BANYAN_DMA_H
  3271. +#define BANYAN_DMA_H
  3272. +#include <asm/idt-boards/rc32300/rc32300.h>
  3273. +
  3274. +/*
  3275. + * An image of one RC32355 dma channel registers
  3276. + */
  3277. +typedef struct {
  3278. + u32 dmac;
  3279. + u32 dmas;
  3280. + u32 dmasm;
  3281. + u32 dmadptr;
  3282. + u32 dmandptr;
  3283. +} rc32355_dma_ch_t;
  3284. +
  3285. +/*
  3286. + * An image of all RC32355 dma channel registers
  3287. + */
  3288. +typedef struct {
  3289. + rc32355_dma_ch_t ch[16];
  3290. +} rc32355_dma_regs_t;
  3291. +
  3292. +
  3293. +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
  3294. +
  3295. +
  3296. +/* DMAC register layout */
  3297. +
  3298. +#define DMAC_RUN 0x1 /* Halts processing when cleared */
  3299. +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
  3300. +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
  3301. +
  3302. +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
  3303. +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
  3304. +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
  3305. +
  3306. +/* DMAS and DMASM register layout */
  3307. +
  3308. +#define DMAS_F 0x01 /* Finished */
  3309. +#define DMAS_D 0x02 /* Done */
  3310. +#define DMAS_C 0x04 /* Chain */
  3311. +#define DMAS_E 0x08 /* Error */
  3312. +#define DMAS_H 0x10 /* Halt */
  3313. +
  3314. +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
  3315. +#define DMA_HALT_TIMEOUT 500
  3316. +
  3317. +
  3318. +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
  3319. +{
  3320. + int timeout=1;
  3321. +
  3322. + if (local_readl(&ch->dmac) & DMAC_RUN) {
  3323. + local_writel(0, &ch->dmac);
  3324. + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
  3325. + if (local_readl(&ch->dmas) & DMAS_H) {
  3326. + local_writel(0, &ch->dmas);
  3327. + break;
  3328. + }
  3329. + }
  3330. + }
  3331. +
  3332. + return timeout ? 0 : 1;
  3333. +}
  3334. +
  3335. +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
  3336. +{
  3337. + local_writel(0, &ch->dmandptr);
  3338. + local_writel(dma_addr, &ch->dmadptr);
  3339. +}
  3340. +
  3341. +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
  3342. +{
  3343. + local_writel(dma_addr, &ch->dmandptr);
  3344. +}
  3345. +
  3346. +
  3347. +/* The following can be used to describe DMA channels 0 to 15, and the */
  3348. +/* sub device's needed to select them in the DMADESC_DS_MASK field */
  3349. +
  3350. +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
  3351. +
  3352. +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
  3353. +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
  3354. +
  3355. +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
  3356. +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
  3357. +
  3358. +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
  3359. +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
  3360. +
  3361. +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
  3362. +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
  3363. +
  3364. +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
  3365. +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
  3366. +#define DMA_DEV_ATMVCC(entry) 0
  3367. +
  3368. +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
  3369. +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
  3370. +
  3371. +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
  3372. +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
  3373. +
  3374. +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
  3375. +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
  3376. +
  3377. +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
  3378. +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
  3379. +
  3380. +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
  3381. +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
  3382. +
  3383. +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
  3384. +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
  3385. +
  3386. +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
  3387. +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
  3388. +
  3389. +#define DMA_CHAN_USBIN 13 /* USB input */
  3390. +#define DMA_DEV_USBIN 0 /* USB input */
  3391. +
  3392. +#define DMA_CHAN_USBOUT 14 /* USB output */
  3393. +#define DMA_DEV_USBOUT 0 /* USB output */
  3394. +
  3395. +#define DMA_CHAN_EXTERN 15 /* External DMA */
  3396. +#define DMA_DEV_EXTERN 0 /* External DMA */
  3397. +
  3398. +/*
  3399. + * An RC32355 dma descriptor in system memory
  3400. + */
  3401. +typedef struct {
  3402. + u32 cmdstat; /* control and status */
  3403. + u32 curr_addr; /* current address of data */
  3404. + u32 devcs; /* peripheral-specific control and status */
  3405. + u32 link; /* link to next descriptor */
  3406. +} rc32355_dma_desc_t;
  3407. +
  3408. +/* Values for the descriptor cmdstat word */
  3409. +
  3410. +#define DMADESC_F 0x80000000u /* Finished bit */
  3411. +#define DMADESC_D 0x40000000u /* Done bit */
  3412. +#define DMADESC_T 0x20000000u /* Terminated bit */
  3413. +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
  3414. +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
  3415. +#define DMADESC_COD 0x04000000u /* Chain On Done */
  3416. +#define DMADESC_COF 0x02000000u /* Chain On Finished */
  3417. +
  3418. +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
  3419. +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
  3420. +
  3421. +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
  3422. +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
  3423. +
  3424. +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
  3425. +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
  3426. +
  3427. +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
  3428. +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
  3429. +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
  3430. +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
  3431. +
  3432. +#define DMA_DEVCMD(devcmd) \
  3433. + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
  3434. +#define DMA_DS(ds) \
  3435. + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
  3436. +#define DMA_COUNT(count) \
  3437. + ((count) & DMADESC_COUNT_MASK)
  3438. +
  3439. +#endif /* RC32355_DMA_H */
  3440. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
  3441. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1969-12-31 19:00:00.000000000 -0500
  3442. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2007-09-20 00:16:52.000000000 -0400
  3443. @@ -0,0 +1,442 @@
  3444. +/**************************************************************************
  3445. + *
  3446. + * BRIEF MODULE DESCRIPTION
  3447. + * Ethernet registers on IDT RC32355
  3448. + *
  3449. + * Copyright 2004 IDT Inc.
  3450. + * Author: Integrated Device Technology Inc. rischelp@idt.com
  3451. + *
  3452. + *
  3453. + * This program is free software; you can redistribute it and/or modify it
  3454. + * under the terms of the GNU General Public License as published by the
  3455. + * Free Software Foundation; either version 2 of the License, or (at your
  3456. + * option) any later version.
  3457. + *
  3458. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  3459. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  3460. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  3461. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  3462. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  3463. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  3464. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  3465. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  3466. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  3467. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  3468. + *
  3469. + * You should have received a copy of the GNU General Public License along
  3470. + * with this program; if not, write to the Free Software Foundation, Inc.,
  3471. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  3472. + *
  3473. + *
  3474. + * May 2004 rkt
  3475. + * Initial Release
  3476. + *
  3477. + **************************************************************************
  3478. + */
  3479. +
  3480. +
  3481. +#ifndef RC32355_ETHER_H
  3482. +#define RC32355_ETHER_H
  3483. +
  3484. +#include <asm/idt-boards/rc32300/rc32355_dma.h>
  3485. +
  3486. +/*
  3487. + * A partial image of the RC32355 ethernet registers
  3488. + */
  3489. +typedef struct {
  3490. + u32 ethintfc;
  3491. + u32 ethfifott;
  3492. + u32 etharc;
  3493. + u32 ethhash0;
  3494. + u32 ethhash1;
  3495. + u32 ethfifost;
  3496. + u32 ethfifos;
  3497. + u32 ethodeops;
  3498. + u32 ethis;
  3499. + u32 ethos;
  3500. + u32 ethmcp;
  3501. + u32 _u1;
  3502. + u32 ethid;
  3503. + u32 _u2;
  3504. + u32 _u3;
  3505. + u32 _u4;
  3506. + u32 ethod;
  3507. + u32 _u5;
  3508. + u32 _u6;
  3509. + u32 _u7;
  3510. + u32 ethodeop;
  3511. + u32 _u8[43];
  3512. + u32 ethsal0;
  3513. + u32 ethsah0;
  3514. + u32 ethsal1;
  3515. + u32 ethsah1;
  3516. + u32 ethsal2;
  3517. + u32 ethsah2;
  3518. + u32 ethsal3;
  3519. + u32 ethsah3;
  3520. + u32 ethrbc;
  3521. + u32 ethrpc;
  3522. + u32 ethrupc;
  3523. + u32 ethrfc;
  3524. + u32 ethtbc;
  3525. + u32 ethgpf;
  3526. + u32 _u9[50];
  3527. + u32 ethmac1;
  3528. + u32 ethmac2;
  3529. + u32 ethipgt;
  3530. + u32 ethipgr;
  3531. + u32 ethclrt;
  3532. + u32 ethmaxf;
  3533. + u32 _u10;
  3534. + u32 ethmtest;
  3535. + u32 miimcfg;
  3536. + u32 miimcmd;
  3537. + u32 miimaddr;
  3538. + u32 miimwtd;
  3539. + u32 miimrdd;
  3540. + u32 miimind;
  3541. + u32 _u11;
  3542. + u32 _u12;
  3543. + u32 ethcfsa0;
  3544. + u32 ethcfsa1;
  3545. + u32 ethcfsa2;
  3546. +} rc32355_eth_regs_t;
  3547. +
  3548. +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
  3549. +
  3550. +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
  3551. +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
  3552. +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
  3553. +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
  3554. +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
  3555. +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
  3556. +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
  3557. +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
  3558. +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
  3559. +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
  3560. +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
  3561. +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
  3562. +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
  3563. +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
  3564. +
  3565. +/* for n in { 0, 1, 2, 3 } */
  3566. +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
  3567. +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
  3568. +
  3569. +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
  3570. +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
  3571. +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
  3572. +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
  3573. +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
  3574. +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
  3575. +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
  3576. +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
  3577. +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
  3578. +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
  3579. +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
  3580. +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
  3581. +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
  3582. +
  3583. +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
  3584. +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
  3585. +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
  3586. +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
  3587. +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
  3588. +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
  3589. +
  3590. +/* for n in { 0, 1, 2 } */
  3591. +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
  3592. +
  3593. +
  3594. +/*
  3595. + * Register Interpretations follow
  3596. + */
  3597. +
  3598. +/******************************************************************************
  3599. + * ETHINTFC register
  3600. + *****************************************************************************/
  3601. +
  3602. +#define ETHERINTFC_EN (1<<0)
  3603. +#define ETHERINTFC_ITS (1<<1)
  3604. +#define ETHERINTFC_RES (1<<2)
  3605. +#define ETHERINTFC_RIP (1<<2)
  3606. +#define ETHERINTFC_JAM (1<<3)
  3607. +
  3608. +/******************************************************************************
  3609. + * ETHFIFOTT register
  3610. + *****************************************************************************/
  3611. +
  3612. +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
  3613. +
  3614. +/******************************************************************************
  3615. + * ETHARC register
  3616. + *****************************************************************************/
  3617. +
  3618. +#define ETHERARC_PRO (1<<0)
  3619. +#define ETHERARC_AM (1<<1)
  3620. +#define ETHERARC_AFM (1<<2)
  3621. +#define ETHERARC_AB (1<<3)
  3622. +
  3623. +/******************************************************************************
  3624. + * ETHHASH registers
  3625. + *****************************************************************************/
  3626. +
  3627. +#define ETHERHASH0(v) (((v)&0xffff)<<0)
  3628. +#define ETHERHASH1(v) (((v)&0xffff)<<0)
  3629. +
  3630. +/******************************************************************************
  3631. + * ETHSA registers
  3632. + *****************************************************************************/
  3633. +
  3634. +#define ETHERSAL0(v) (((v)&0xffff)<<0)
  3635. +#define ETHERSAL1(v) (((v)&0xffff)<<0)
  3636. +#define ETHERSAL2(v) (((v)&0xffff)<<0)
  3637. +#define ETHERSAL3(v) (((v)&0xffff)<<0)
  3638. +#define ETHERSAH0(v) (((v)&0xff)<<0)
  3639. +#define ETHERSAH1(v) (((v)&0xff)<<0)
  3640. +#define ETHERSAH2(v) (((v)&0xff)<<0)
  3641. +#define ETHERSAH3(v) (((v)&0xff)<<0)
  3642. +
  3643. +/******************************************************************************
  3644. + * ETHFIFOST register
  3645. + *****************************************************************************/
  3646. +
  3647. +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
  3648. +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
  3649. +
  3650. +/******************************************************************************
  3651. + * ETHFIFOS register
  3652. + *****************************************************************************/
  3653. +
  3654. +#define ETHERFIFOS_IR (1<<0)
  3655. +#define ETHERFIFOS_OR (1<<1)
  3656. +#define ETHERFIFOS_OVR (1<<2)
  3657. +#define ETHERFIFOS_UND (1<<3)
  3658. +
  3659. +/******************************************************************************
  3660. + * DATA registers
  3661. + *****************************************************************************/
  3662. +
  3663. +#define ETHERID(v) (((v)&0xffff)<<0)
  3664. +#define ETHEROD(v) (((v)&0xffff)<<0)
  3665. +
  3666. +/******************************************************************************
  3667. + * ETHODEOPS register
  3668. + *****************************************************************************/
  3669. +
  3670. +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
  3671. +
  3672. +/******************************************************************************
  3673. + * ETHODEOP register
  3674. + *****************************************************************************/
  3675. +
  3676. +#define ETHERODEOP(v) (((v)&0xffff)<<0)
  3677. +
  3678. +/******************************************************************************
  3679. + * ETHIS register
  3680. + *****************************************************************************/
  3681. +
  3682. +#define ETHERIS_EOP (1<<0)
  3683. +#define ETHERIS_ROK (1<<2)
  3684. +#define ETHERIS_FM (1<<3)
  3685. +#define ETHERIS_MP (1<<4)
  3686. +#define ETHERIS_BP (1<<5)
  3687. +#define ETHERIS_VLT (1<<6)
  3688. +#define ETHERIS_CF (1<<7)
  3689. +#define ETHERIS_OVR (1<<8)
  3690. +#define ETHERIS_CRC (1<<9)
  3691. +#define ETHERIS_CV (1<<10)
  3692. +#define ETHERIS_DB (1<<11)
  3693. +#define ETHERIS_LE (1<<12)
  3694. +#define ETHERIS_LOR (1<<13)
  3695. +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
  3696. +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
  3697. +
  3698. +/******************************************************************************
  3699. + * ETHOS register
  3700. + *****************************************************************************/
  3701. +
  3702. +#define ETHEROS_T (1<<0)
  3703. +#define ETHEROS_TOK (1<<6)
  3704. +#define ETHEROS_MP (1<<7)
  3705. +#define ETHEROS_BP (1<<8)
  3706. +#define ETHEROS_UND (1<<9)
  3707. +#define ETHEROS_OF (1<<10)
  3708. +#define ETHEROS_ED (1<<11)
  3709. +#define ETHEROS_EC (1<<12)
  3710. +#define ETHEROS_LC (1<<13)
  3711. +#define ETHEROS_TD (1<<14)
  3712. +#define ETHEROS_CRC (1<<15)
  3713. +#define ETHEROS_LE (1<<16)
  3714. +#define ETHEROS_CC(v) (((v)&0xf)<<17)
  3715. +#define ETHEROS_PFD (1<<21)
  3716. +
  3717. +/******************************************************************************
  3718. + * Statistics registers
  3719. + *****************************************************************************/
  3720. +
  3721. +#define ETHERRBC(v) (((v)&0xffff)<<0)
  3722. +#define ETHERRPC(v) (((v)&0xffff)<<0)
  3723. +#define ETHERRUPC(v) (((v)&0xffff)<<0)
  3724. +#define ETHERRFC(v) (((v)&0xffff)<<0)
  3725. +#define ETHERTBC(v) (((v)&0xffff)<<0)
  3726. +
  3727. +/******************************************************************************
  3728. + * ETHGPF register
  3729. + *****************************************************************************/
  3730. +
  3731. +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
  3732. +
  3733. +/******************************************************************************
  3734. + * MAC registers
  3735. + *****************************************************************************/
  3736. +//ETHMAC1
  3737. +#define ETHERMAC1_RE (1<<0)
  3738. +#define ETHERMAC1_PAF (1<<1)
  3739. +#define ETHERMAC1_RFC (1<<2)
  3740. +#define ETHERMAC1_TFC (1<<3)
  3741. +#define ETHERMAC1_LB (1<<4)
  3742. +#define ETHERMAC1_MR (1<<15)
  3743. +
  3744. +//ETHMAC2
  3745. +#define ETHERMAC2_FD (1<<0)
  3746. +#define ETHERMAC2_FLC (1<<1)
  3747. +#define ETHERMAC2_HFE (1<<2)
  3748. +#define ETHERMAC2_DC (1<<3)
  3749. +#define ETHERMAC2_CEN (1<<4)
  3750. +#define ETHERMAC2_PE (1<<5)
  3751. +#define ETHERMAC2_VPE (1<<6)
  3752. +#define ETHERMAC2_APE (1<<7)
  3753. +#define ETHERMAC2_PPE (1<<8)
  3754. +#define ETHERMAC2_LPE (1<<9)
  3755. +#define ETHERMAC2_NB (1<<12)
  3756. +#define ETHERMAC2_BP (1<<13)
  3757. +#define ETHERMAC2_ED (1<<14)
  3758. +
  3759. +//ETHIPGT
  3760. +#define ETHERIPGT(v) (((v)&0x3f)<<0)
  3761. +
  3762. +//ETHIPGR
  3763. +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
  3764. +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
  3765. +
  3766. +//ETHCLRT
  3767. +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
  3768. +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
  3769. +
  3770. +//ETHMAXF
  3771. +#define ETHERMAXF(v) (((v)&0x3f)<<0)
  3772. +
  3773. +//ETHMTEST
  3774. +#define ETHERMTEST_TB (1<<2)
  3775. +
  3776. +//ETHMCP
  3777. +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
  3778. +
  3779. +//MIIMCFG
  3780. +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
  3781. +#define ETHERMIIMCFG_R (1<<15)
  3782. +
  3783. +//MIIMCMD
  3784. +#define ETHERMIIMCMD_RD (1<<0)
  3785. +#define ETHERMIIMCMD_SCN (1<<1)
  3786. +
  3787. +//MIIMADDR
  3788. +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
  3789. +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
  3790. +
  3791. +//MIIMWTD
  3792. +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
  3793. +
  3794. +//MIIMRDD
  3795. +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
  3796. +
  3797. +//MIIMIND
  3798. +#define ETHERMIIMIND_BSY (1<<0)
  3799. +#define ETHERMIIMIND_SCN (1<<1)
  3800. +#define ETHERMIIMIND_NV (1<<2)
  3801. +
  3802. +//DMA DEVCS IN
  3803. +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
  3804. +#define ETHERDMA_IN_CES (1<<14)
  3805. +#define ETHERDMA_IN_LOR (1<<13)
  3806. +#define ETHERDMA_IN_LE (1<<12)
  3807. +#define ETHERDMA_IN_DB (1<<11)
  3808. +#define ETHERDMA_IN_CV (1<<10)
  3809. +#define ETHERDMA_IN_CRC (1<<9)
  3810. +#define ETHERDMA_IN_OVR (1<<8)
  3811. +#define ETHERDMA_IN_CF (1<<7)
  3812. +#define ETHERDMA_IN_VLT (1<<6)
  3813. +#define ETHERDMA_IN_BP (1<<5)
  3814. +#define ETHERDMA_IN_MP (1<<4)
  3815. +#define ETHERDMA_IN_FM (1<<3)
  3816. +#define ETHERDMA_IN_ROK (1<<2)
  3817. +#define ETHERDMA_IN_LD (1<<1)
  3818. +#define ETHERDMA_IN_FD (1<<0)
  3819. +
  3820. +//DMA DEVCS OUT
  3821. +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
  3822. +#define ETHERDMA_OUT_CNT 0x001e0000
  3823. +#define ETHERDMA_OUT_SHFT 17
  3824. +#define ETHERDMA_OUT_LE (1<<16)
  3825. +
  3826. +#define ETHERDMA_OUT_CRC (1<<15)
  3827. +#define ETHERDMA_OUT_TD (1<<14)
  3828. +#define ETHERDMA_OUT_LC (1<<13)
  3829. +#define ETHERDMA_OUT_EC (1<<12)
  3830. +#define ETHERDMA_OUT_ED (1<<11)
  3831. +#define ETHERDMA_OUT_OF (1<<10)
  3832. +#define ETHERDMA_OUT_UND (1<<9)
  3833. +#define ETHERDMA_OUT_BP (1<<8)
  3834. +#define ETHERDMA_OUT_MP (1<<7)
  3835. +#define ETHERDMA_OUT_TOK (1<<6)
  3836. +#define ETHERDMA_OUT_HEN (1<<5)
  3837. +#define ETHERDMA_OUT_CEN (1<<4)
  3838. +#define ETHERDMA_OUT_PEN (1<<3)
  3839. +#define ETHERDMA_OUT_OEN (1<<2)
  3840. +#define ETHERDMA_OUT_LD (1<<1)
  3841. +#define ETHERDMA_OUT_FD (1<<0)
  3842. +
  3843. +#define RCV_ERRS \
  3844. + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
  3845. +#define TX_ERRS \
  3846. + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
  3847. + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
  3848. +
  3849. +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
  3850. +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
  3851. +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
  3852. +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
  3853. +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
  3854. +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
  3855. +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
  3856. +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
  3857. +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
  3858. +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
  3859. +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
  3860. +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
  3861. + Range */
  3862. +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
  3863. +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
  3864. + received packet */
  3865. +
  3866. +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
  3867. +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
  3868. +
  3869. +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
  3870. +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
  3871. + Underflow */
  3872. +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
  3873. +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
  3874. + deferral */
  3875. +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
  3876. + collisions */
  3877. +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
  3878. +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
  3879. +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
  3880. +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
  3881. +
  3882. +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
  3883. +
  3884. +#endif /* RC32355_ETHER_H */
  3885. +
  3886. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365.h
  3887. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365.h 1969-12-31 19:00:00.000000000 -0500
  3888. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365.h 2007-09-20 00:16:52.000000000 -0400
  3889. @@ -0,0 +1,160 @@
  3890. +/**************************************************************************
  3891. + *
  3892. + * BRIEF MODULE DESCRIPTION
  3893. + * Definitions for IDT RC32365 CPU.
  3894. + *
  3895. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  3896. + *
  3897. + * This program is free software; you can redistribute it and/or modify it
  3898. + * under the terms of the GNU General Public License as published by the
  3899. + * Free Software Foundation; either version 2 of the License, or (at your
  3900. + * option) any later version.
  3901. + *
  3902. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  3903. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  3904. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  3905. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  3906. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  3907. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  3908. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  3909. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  3910. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  3911. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  3912. + *
  3913. + * You should have received a copy of the GNU General Public License along
  3914. + * with this program; if not, write to the Free Software Foundation, Inc.,
  3915. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  3916. + *
  3917. + *
  3918. + **************************************************************************
  3919. + * May 2004 P. Sadik.
  3920. + *
  3921. + * Initial Release
  3922. + *
  3923. + *
  3924. + *
  3925. + **************************************************************************
  3926. + */
  3927. +
  3928. +#ifndef __IDT_RC32365_H__
  3929. +#define __IDT_RC32365_H__
  3930. +
  3931. +extern unsigned int cedar_za;
  3932. +
  3933. +/* Base address of internal registers */
  3934. +#define RC32365_REG_BASE 0x18000000
  3935. +
  3936. +/* System ID Registers */
  3937. +#define CPU_SYSID (RC32365_REG_BASE + 0x00018)
  3938. +#define CPU_DEVTYPE (RC32365_REG_BASE + 0x0001c)
  3939. +
  3940. +/* Reset Controller */
  3941. +#define RESET_CNTL (RC32365_REG_BASE + 0x08000)
  3942. +#define BOOT_VECTOR (RC32365_REG_BASE + 0x08004)
  3943. +
  3944. +/* Device Controller */
  3945. +#define DEV0_BASE (RC32365_REG_BASE + 0x10000)
  3946. +#define DEV0_MASK (RC32365_REG_BASE + 0x10004)
  3947. +#define DEV0_CNTL (RC32365_REG_BASE + 0x10008)
  3948. +#define DEV0_TIMING (RC32365_REG_BASE + 0x1000c)
  3949. +#define DEV_REG_OFFSET 0x10
  3950. +
  3951. +/* SDRAM Controller */
  3952. +#define SDRAM0_BASE (RC32365_REG_BASE + 0x18000)
  3953. +#define SDRAM0_MASK (RC32365_REG_BASE + 0x18004)
  3954. +#define SDRAM1_BASE (RC32365_REG_BASE + 0x18008)
  3955. +#define SDRAM1_MASK (RC32365_REG_BASE + 0x1800c)
  3956. +#define SDRAM_CNTL (RC32365_REG_BASE + 0x18010)
  3957. +
  3958. +/* Counters/Timers */
  3959. +#define TIMER0_COUNT (RC32365_REG_BASE + 0x20000)
  3960. +#define TIMER0_COMPARE (RC32365_REG_BASE + 0x20004)
  3961. +#define TIMER0_CNTL (RC32365_REG_BASE + 0x20008)
  3962. +#define TIMER0_SELECT (RC32365_REG_BASE + 0x2000c)
  3963. +#define TIMER_REG_OFFSET 0x10
  3964. +
  3965. +/* System Integrity */
  3966. +
  3967. +/* Interrupt Controller */
  3968. +#define IC_GROUP0_PEND (RC32365_REG_BASE + 0x30000)
  3969. +#define IC_GROUP0_TEST (RC32365_REG_BASE + 0x30004)
  3970. +#define IC_GROUP0_MASK (RC32365_REG_BASE + 0x30008)
  3971. +#define IC_GROUP_OFFSET 0x0c
  3972. +
  3973. +#define NUM_INTR_GROUPS 5
  3974. +/*
  3975. + * The IRQ mapping is as follows:
  3976. + *
  3977. + * IRQ Mapped To
  3978. + * --- -------------------
  3979. + * 0 SW0 (IP0) SW0 intr
  3980. + * 1 SW1 (IP1) SW1 intr
  3981. + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
  3982. + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
  3983. + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
  3984. + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
  3985. + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
  3986. + * 7 Int5 (IP7) CP0 Timer
  3987. + *
  3988. + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
  3989. + * internally on the RC32365 is routed to the Expansion
  3990. + * Interrupt Controller.
  3991. + */
  3992. +#define MIPS_CPU_TIMER_IRQ 7
  3993. +
  3994. +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
  3995. +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
  3996. +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // RNG, SEC
  3997. +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
  3998. +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
  3999. +
  4000. +#define RC32365_NR_IRQS (GROUP4_IRQ_BASE + 32)
  4001. +
  4002. +/* DMA - see rc32365_dma.h for full list of registers */
  4003. +
  4004. +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
  4005. +#define DMA_CHAN_OFFSET 0x14
  4006. +
  4007. +/* GPIO Controller */
  4008. +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
  4009. +
  4010. +/* 16550 UARTs */
  4011. +#ifdef __MIPSEB__
  4012. +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
  4013. +#else
  4014. +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
  4015. +#endif
  4016. +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 0)
  4017. +
  4018. +/* Ethernet - see rc32365_eth.h for full list of registers */
  4019. +
  4020. +#define RC32365_ETH_BASE (RC32365_REG_BASE + 0x58000)
  4021. +
  4022. +#define IDT_CLOCK_MULT 2
  4023. +
  4024. +/* FLASH (device 1) */
  4025. +#define FLASH_BASE 0x08000000
  4026. +#define FLASH_SIZE 0x00800000
  4027. +
  4028. +/* LCD 4-digit display (device 2) */
  4029. +#define LCD_DIGIT0 0x0C000003
  4030. +#define LCD_DIGIT1 0x0C000002
  4031. +#define LCD_DIGIT2 0x0C000001
  4032. +#define LCD_DIGIT3 0x0C000000
  4033. +
  4034. +/* RTC (DS1553) (device 2) */
  4035. +#define RTC_BASE 0x0c800000
  4036. +/* NVRAM */
  4037. +#define NVRAM_BASE RTC_BASE
  4038. +#define NVRAM_ENVSIZE_OFF 4
  4039. +#define NVRAM_ENVSTART_OFF 32
  4040. +
  4041. +/* Interrupts routed on 79EB365 board */
  4042. +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE + 8)
  4043. +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE + 9)
  4044. +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
  4045. +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
  4046. +
  4047. +#define RAM_SIZE (32 * 1024 * 1024)
  4048. +
  4049. +#endif //__IDT_RC32365_H__
  4050. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
  4051. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1969-12-31 19:00:00.000000000 -0500
  4052. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2007-09-20 00:16:52.000000000 -0400
  4053. @@ -0,0 +1,226 @@
  4054. +/**************************************************************************
  4055. + *
  4056. + * BRIEF MODULE DESCRIPTION
  4057. + * RC32365/336 DMA hardware abstraction.
  4058. + *
  4059. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  4060. + *
  4061. + * This program is free software; you can redistribute it and/or modify it
  4062. + * under the terms of the GNU General Public License as published by the
  4063. + * Free Software Foundation; either version 2 of the License, or (at your
  4064. + * option) any later version.
  4065. + *
  4066. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  4067. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  4068. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  4069. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  4070. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  4071. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  4072. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  4073. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  4074. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  4075. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  4076. + *
  4077. + * You should have received a copy of the GNU General Public License along
  4078. + * with this program; if not, write to the Free Software Foundation, Inc.,
  4079. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  4080. + *
  4081. + *
  4082. + **************************************************************************
  4083. + * May 2004 P. Sadik.
  4084. + *
  4085. + * Initial Release
  4086. + *
  4087. + *
  4088. + *
  4089. + **************************************************************************
  4090. + */
  4091. +
  4092. +#ifndef __IDT_RC32365_DMA_H__
  4093. +#define __IDT_RC32365_DMA_H__
  4094. +
  4095. +enum
  4096. +{
  4097. + DMA0_PhysicalAddress = 0x18038000,
  4098. + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
  4099. +
  4100. + DMA0_VirtualAddress = 0xb8038000,
  4101. + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
  4102. +} ;
  4103. +
  4104. +/*
  4105. + * DMA descriptor (in physical memory).
  4106. + */
  4107. +
  4108. +typedef struct DMAD_s
  4109. +{
  4110. + u32 control ; // Control. use DMAD_*
  4111. + u32 ca ; // Current Address.
  4112. + u32 devcs ; // Device control and status.
  4113. + u32 link ; // Next descriptor in chain.
  4114. +} volatile *DMAD_t ;
  4115. +
  4116. +enum
  4117. +{
  4118. + DMAD_size = sizeof (struct DMAD_s),
  4119. + DMAD_count_b = 0, // in DMAD_t -> control
  4120. + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
  4121. + DMAD_ds_b = 20, // in DMAD_t -> control
  4122. + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
  4123. + DMAD_ds_extToMem0_v = 0,
  4124. + DMAD_ds_memToExt0_v = 1,
  4125. + DMAD_ds_extToMem1_v = 0,
  4126. + DMAD_ds_memToExt1_v = 1,
  4127. + DMAD_ds_ethRcv0_v = 0,
  4128. + DMAD_ds_ethXmt0_v = 0,
  4129. + DMAD_ds_ethRcv1_v = 0,
  4130. + DMAD_ds_ethXmt2_v = 0,
  4131. + DMAD_ds_memToFifo_v = 0,
  4132. + DMAD_ds_fifoToMem_v = 0,
  4133. + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
  4134. + DMAD_ds_pciToMem_v = 0,
  4135. + DMAD_ds_memToPci_v = 0,
  4136. + DMAD_ds_securityInput_v = 0,
  4137. + DMAD_ds_securityOutput_v = 0,
  4138. + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
  4139. +
  4140. + DMAD_devcmd_b = 22, // in DMAD_t -> control
  4141. + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
  4142. + DMAD_devcmd_byte_v = 0, //memory-to-memory
  4143. + DMAD_devcmd_halfword_v = 1, //memory-to-memory
  4144. + DMAD_devcmd_word_v = 2, //memory-to-memory
  4145. + DMAD_devcmd_2words_v = 3, //memory-to-memory
  4146. + DMAD_devcmd_4words_v = 4, //memory-to-memory
  4147. + DMAD_devcmd_6words_v = 5, //memory-to-memory
  4148. + DMAD_devcmd_8words_v = 6, //memory-to-memory
  4149. + DMAD_devcmd_16words_v = 7, //memory-to-memory
  4150. + DMAD_cof_b = 25, // chain on finished
  4151. + DMAD_cof_m = 0x02000000, //
  4152. + DMAD_cod_b = 26, // chain on done
  4153. + DMAD_cod_m = 0x04000000, //
  4154. + DMAD_iof_b = 27, // interrupt on finished
  4155. + DMAD_iof_m = 0x08000000, //
  4156. + DMAD_iod_b = 28, // interrupt on done
  4157. + DMAD_iod_m = 0x10000000, //
  4158. + DMAD_t_b = 29, // terminated
  4159. + DMAD_t_m = 0x20000000, //
  4160. + DMAD_d_b = 30, // done
  4161. + DMAD_d_m = 0x40000000, //
  4162. + DMAD_f_b = 31, // finished
  4163. + DMAD_f_m = 0x80000000, //
  4164. +} ;
  4165. +
  4166. +/*
  4167. + * DMA register (within Internal Register Map).
  4168. + */
  4169. +
  4170. +struct DMA_Chan_s
  4171. +{
  4172. + u32 dmac ; // Control.
  4173. + u32 dmas ; // Status.
  4174. + u32 dmasm ; // Mask.
  4175. + u32 dmadptr ; // Descriptor pointer.
  4176. + u32 dmandptr ; // Next descriptor pointer.
  4177. +};
  4178. +
  4179. +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
  4180. +
  4181. +//DMA_Channels use DMACH_count instead
  4182. +
  4183. +enum
  4184. +{
  4185. + DMAC_run_b = 0, //
  4186. + DMAC_run_m = 0x00000001, //
  4187. + DMAC_dm_b = 1, // done mask
  4188. + DMAC_dm_m = 0x00000002, //
  4189. + DMAC_mode_b = 2, //
  4190. + DMAC_mode_m = 0x0000000c, //
  4191. + DMAC_mode_auto_v = 0,
  4192. + DMAC_mode_burst_v = 1,
  4193. + DMAC_mode_transfer_v = 2, //usually used
  4194. + DMAC_mode_reserved_v = 3,
  4195. + DMAC_a_b = 4, //
  4196. + DMAC_a_m = 0x00000010, //
  4197. +
  4198. + DMAS_f_b = 0, // finished (sticky)
  4199. + DMAS_f_m = 0x00000001, //
  4200. + DMAS_d_b = 1, // done (sticky)
  4201. + DMAS_d_m = 0x00000002, //
  4202. + DMAS_c_b = 2, // chain (sticky)
  4203. + DMAS_c_m = 0x00000004, //
  4204. + DMAS_e_b = 3, // error (sticky)
  4205. + DMAS_e_m = 0x00000008, //
  4206. + DMAS_h_b = 4, // halt (sticky)
  4207. + DMAS_h_m = 0x00000010, //
  4208. +
  4209. + DMASM_f_b = 0, // finished (1=mask)
  4210. + DMASM_f_m = 0x00000001, //
  4211. + DMASM_d_b = 1, // done (1=mask)
  4212. + DMASM_d_m = 0x00000002, //
  4213. + DMASM_c_b = 2, // chain (1=mask)
  4214. + DMASM_c_m = 0x00000004, //
  4215. + DMASM_e_b = 3, // error (1=mask)
  4216. + DMASM_e_m = 0x00000008, //
  4217. + DMASM_h_b = 4, // halt (1=mask)
  4218. + DMASM_h_m = 0x00000010, //
  4219. +} ;
  4220. +
  4221. +/*
  4222. + * DMA channel definitions
  4223. + */
  4224. +
  4225. +enum
  4226. +{
  4227. + DMACH_ethRcv0 = 0,
  4228. + DMACH_ethXmt0 = 1,
  4229. + DMACH_ethRcv1 = 2,
  4230. + DMACH_ethXmt2 = 3,
  4231. + DMACH_pciToMem = 4,
  4232. + DMACH_memToPci = 5,
  4233. + DMACH_securityInput = 6,
  4234. + DMACH_securityOutput = 7,
  4235. + DMACH_rng = 8,
  4236. +
  4237. + DMACH_count //must be last
  4238. +};
  4239. +
  4240. +
  4241. +typedef struct DMAC_s
  4242. +{
  4243. + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
  4244. +} volatile *DMA_t ;
  4245. +
  4246. +
  4247. +/*
  4248. + * External DMA parameters
  4249. +*/
  4250. +
  4251. +enum
  4252. +{
  4253. + DMADEVCMD_ts_b = 0, // ts field in devcmd
  4254. + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
  4255. + DMADEVCMD_ts_byte_v = 0,
  4256. + DMADEVCMD_ts_halfword_v = 1,
  4257. + DMADEVCMD_ts_word_v = 2,
  4258. + DMADEVCMD_ts_2word_v = 3,
  4259. + DMADEVCMD_ts_4word_v = 4,
  4260. + DMADEVCMD_ts_6word_v = 5,
  4261. + DMADEVCMD_ts_8word_v = 6,
  4262. + DMADEVCMD_ts_16word_v = 7
  4263. +};
  4264. +
  4265. +
  4266. +#if 1 // aws - Compatibility.
  4267. +# define EXTDMA_ts_b DMADEVCMD_ts_b
  4268. +# define EXTDMA_ts_m DMADEVCMD_ts_m
  4269. +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
  4270. +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
  4271. +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
  4272. +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
  4273. +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
  4274. +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
  4275. +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
  4276. +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
  4277. +#endif // aws - Compatibility.
  4278. +
  4279. +#endif // __IDT_RC32365_DMA_H__
  4280. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
  4281. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1969-12-31 19:00:00.000000000 -0500
  4282. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2007-09-20 00:16:52.000000000 -0400
  4283. @@ -0,0 +1,86 @@
  4284. +/**************************************************************************
  4285. + *
  4286. + * BRIEF MODULE DESCRIPTION
  4287. + * RC32365/336 DMA interface routines.
  4288. + *
  4289. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  4290. + *
  4291. + * This program is free software; you can redistribute it and/or modify it
  4292. + * under the terms of the GNU General Public License as published by the
  4293. + * Free Software Foundation; either version 2 of the License, or (at your
  4294. + * option) any later version.
  4295. + *
  4296. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  4297. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  4298. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  4299. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  4300. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  4301. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  4302. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  4303. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  4304. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  4305. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  4306. + *
  4307. + * You should have received a copy of the GNU General Public License along
  4308. + * with this program; if not, write to the Free Software Foundation, Inc.,
  4309. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  4310. + *
  4311. + *
  4312. + **************************************************************************
  4313. + * May 2004 P. Sadik.
  4314. + *
  4315. + * Initial Release
  4316. + *
  4317. + *
  4318. + *
  4319. + **************************************************************************
  4320. + */
  4321. +
  4322. +#ifndef __IDT_RC32365_DMA_V_H__
  4323. +#define __IDT_RC32365_DMA_V_H__
  4324. +
  4325. +
  4326. +#include <asm/idt-boards/rc32300/rc32300.h>
  4327. +#include <asm/idt-boards/rc32300/rc32365_dma.h>
  4328. +#include <asm/idt-boards/rc32300/rc32365.h>
  4329. +
  4330. +#define DMA_CHAN_OFFSET 0x14
  4331. +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
  4332. +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
  4333. +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
  4334. +
  4335. +#define DMA_COUNT(count) \
  4336. + ((count) & DMAD_count_m)
  4337. +
  4338. +#define DMA_HALT_TIMEOUT 500
  4339. +
  4340. +static inline int rc32365_halt_dma(DMA_Chan_t ch)
  4341. +{
  4342. + int timeout=1;
  4343. + if (local_readl(&ch->dmac) & DMAC_run_m) {
  4344. + local_writel(0, &ch->dmac);
  4345. +
  4346. + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
  4347. + if (local_readl(&ch->dmas) & DMAS_h_m) {
  4348. + local_writel(0, &ch->dmas);
  4349. + break;
  4350. + }
  4351. + }
  4352. +
  4353. + }
  4354. +
  4355. + return timeout ? 0 : 1;
  4356. +}
  4357. +
  4358. +
  4359. +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
  4360. +{
  4361. + local_writel(0, &ch->dmandptr);
  4362. + local_writel(dma_addr, &ch->dmadptr);
  4363. +}
  4364. +
  4365. +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
  4366. +{
  4367. + local_writel(dma_addr, &ch->dmandptr);
  4368. +}
  4369. +#endif //__IDT_RC32365_DMA_V_H__
  4370. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
  4371. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 1969-12-31 19:00:00.000000000 -0500
  4372. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2007-09-20 00:16:52.000000000 -0400
  4373. @@ -0,0 +1,344 @@
  4374. +/**************************************************************************
  4375. + *
  4376. + * BRIEF MODULE DESCRIPTION
  4377. + * RC32365/336 Ethernet hardware abstraction.
  4378. + *
  4379. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  4380. + *
  4381. + * This program is free software; you can redistribute it and/or modify it
  4382. + * under the terms of the GNU General Public License as published by the
  4383. + * Free Software Foundation; either version 2 of the License, or (at your
  4384. + * option) any later version.
  4385. + *
  4386. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  4387. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  4388. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  4389. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  4390. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  4391. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  4392. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  4393. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  4394. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  4395. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  4396. + *
  4397. + * You should have received a copy of the GNU General Public License along
  4398. + * with this program; if not, write to the Free Software Foundation, Inc.,
  4399. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  4400. + *
  4401. + *
  4402. + **************************************************************************
  4403. + * May 2004 P. Sadik.
  4404. + *
  4405. + * Initial Release
  4406. + *
  4407. + *
  4408. + *
  4409. + **************************************************************************
  4410. + */
  4411. +
  4412. +#ifndef __IDT_RC32365_ETH_H__
  4413. +#define __IDT_RC32365_ETH_H__
  4414. +
  4415. +enum
  4416. +{
  4417. + ETH0_PhysicalAddress = 0x18058000,
  4418. + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
  4419. + ETH0_VirtualAddress = 0xb8058000,
  4420. +
  4421. + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
  4422. +
  4423. + ETH1_PhysicalAddress = 0x18060000,
  4424. + ETH1_VirtualAddress = 0xb8060000, // Default
  4425. +} ;
  4426. +
  4427. +typedef struct
  4428. +{
  4429. + u32 ethintfc ;
  4430. + u32 ethfifott ;
  4431. + u32 etharc ;
  4432. + u32 ethhash0 ;
  4433. + u32 ethhash1 ;
  4434. + u32 ethu0 [4] ; // Reserved.
  4435. + u32 ethpfs ;
  4436. + u32 ethmcp ;
  4437. + u32 eth_u1 [10] ; // Reserved.
  4438. + u32 ethspare ;
  4439. + u32 eth_u2 [42] ; // Reserved.
  4440. + u32 ethsal0 ;
  4441. + u32 ethsah0 ;
  4442. + u32 ethsal1 ;
  4443. + u32 ethsah1 ;
  4444. + u32 ethsal2 ;
  4445. + u32 ethsah2 ;
  4446. + u32 ethsal3 ;
  4447. + u32 ethsah3 ;
  4448. + u32 ethrbc ;
  4449. + u32 ethrpc ;
  4450. + u32 ethrupc ;
  4451. + u32 ethrfc ;
  4452. + u32 ethtbc ;
  4453. + u32 ethgpf ;
  4454. + u32 eth_u9 [50] ; // Reserved.
  4455. + u32 ethmac1 ;
  4456. + u32 ethmac2 ;
  4457. + u32 ethipgt ;
  4458. + u32 ethipgr ;
  4459. + u32 ethclrt ;
  4460. + u32 ethmaxf ;
  4461. + u32 eth_u10 ; // Reserved.
  4462. + u32 ethmtest ;
  4463. + u32 miimcfg ;
  4464. + u32 miimcmd ;
  4465. + u32 miimaddr ;
  4466. + u32 miimwtd ;
  4467. + u32 miimrdd ;
  4468. + u32 miimind ;
  4469. + u32 eth_u11 ; // Reserved.
  4470. + u32 eth_u12 ; // Reserved.
  4471. + u32 ethcfsa0 ;
  4472. + u32 ethcfsa1 ;
  4473. + u32 ethcfsa2 ;
  4474. +} volatile *ETH_t;
  4475. +
  4476. +enum
  4477. +{
  4478. + ETHINTFC_en_b = 0,
  4479. + ETHINTFC_en_m = 0x00000001,
  4480. + ETHINTFC_its_b = 1,
  4481. + ETHINTFC_its_m = 0x00000002,
  4482. + ETHINTFC_rip_b = 2,
  4483. + ETHINTFC_rip_m = 0x00000004,
  4484. + ETHINTFC_jam_b = 3,
  4485. + ETHINTFC_jam_m = 0x00000008,
  4486. + ETHINTFC_ovr_b = 4,
  4487. + ETHINTFC_ovr_m = 0x00000010,
  4488. + ETHINTFC_und_b = 5,
  4489. + ETHINTFC_und_m = 0x00000020,
  4490. +
  4491. + ETHFIFOTT_tth_b = 0,
  4492. + ETHFIFOTT_tth_m = 0x0000007f,
  4493. +
  4494. + ETHARC_pro_b = 0,
  4495. + ETHARC_pro_m = 0x00000001,
  4496. + ETHARC_am_b = 1,
  4497. + ETHARC_am_m = 0x00000002,
  4498. + ETHARC_afm_b = 2,
  4499. + ETHARC_afm_m = 0x00000004,
  4500. + ETHARC_ab_b = 3,
  4501. + ETHARC_ab_m = 0x00000008,
  4502. +
  4503. + ETHSAL_byte5_b = 0,
  4504. + ETHSAL_byte5_m = 0x000000ff,
  4505. + ETHSAL_byte4_b = 8,
  4506. + ETHSAL_byte4_m = 0x0000ff00,
  4507. + ETHSAL_byte3_b = 16,
  4508. + ETHSAL_byte3_m = 0x00ff0000,
  4509. + ETHSAL_byte2_b = 24,
  4510. + ETHSAL_byte2_m = 0xff000000,
  4511. +
  4512. + ETHSAH_byte1_b = 0,
  4513. + ETHSAH_byte1_m = 0x000000ff,
  4514. + ETHSAH_byte0_b = 8,
  4515. + ETHSAH_byte0_m = 0x0000ff00,
  4516. +
  4517. + ETHGPF_ptv_b = 0,
  4518. + ETHGPF_ptv_m = 0x0000ffff,
  4519. +
  4520. + ETHPFS_pfd_b = 0,
  4521. + ETHPFS_pfd_m = 0x00000001,
  4522. +
  4523. + ETHCFSA0_cfsa4_b = 0,
  4524. + ETHCFSA0_cfsa4_m = 0x000000ff,
  4525. + ETHCFSA0_cfsa5_b = 8,
  4526. + ETHCFSA0_cfsa5_m = 0x0000ff00,
  4527. +
  4528. + ETHCFSA1_cfsa2_b = 0,
  4529. + ETHCFSA1_cfsa2_m = 0x000000ff,
  4530. + ETHCFSA1_cfsa3_b = 8,
  4531. + ETHCFSA1_cfsa3_m = 0x0000ff00,
  4532. +
  4533. + ETHCFSA2_cfsa0_b = 0,
  4534. + ETHCFSA2_cfsa0_m = 0x000000ff,
  4535. + ETHCFSA2_cfsa1_b = 8,
  4536. + ETHCFSA2_cfsa1_m = 0x0000ff00,
  4537. +
  4538. + ETHMAC1_re_b = 0,
  4539. + ETHMAC1_re_m = 0x00000001,
  4540. + ETHMAC1_paf_b = 1,
  4541. + ETHMAC1_paf_m = 0x00000002,
  4542. + ETHMAC1_rfc_b = 2,
  4543. + ETHMAC1_rfc_m = 0x00000004,
  4544. + ETHMAC1_tfc_b = 3,
  4545. + ETHMAC1_tfc_m = 0x00000008,
  4546. + ETHMAC1_lb_b = 4,
  4547. + ETHMAC1_lb_m = 0x00000010,
  4548. + ETHMAC1_mr_b = 31,
  4549. + ETHMAC1_mr_m = 0x80000000,
  4550. +
  4551. + ETHMAC2_fd_b = 0,
  4552. + ETHMAC2_fd_m = 0x00000001,
  4553. + ETHMAC2_flc_b = 1,
  4554. + ETHMAC2_flc_m = 0x00000002,
  4555. + ETHMAC2_hfe_b = 2,
  4556. + ETHMAC2_hfe_m = 0x00000004,
  4557. + ETHMAC2_dc_b = 3,
  4558. + ETHMAC2_dc_m = 0x00000008,
  4559. + ETHMAC2_cen_b = 4,
  4560. + ETHMAC2_cen_m = 0x00000010,
  4561. + ETHMAC2_pe_b = 5,
  4562. + ETHMAC2_pe_m = 0x00000020,
  4563. + ETHMAC2_vpe_b = 6,
  4564. + ETHMAC2_vpe_m = 0x00000040,
  4565. + ETHMAC2_ape_b = 7,
  4566. + ETHMAC2_ape_m = 0x00000080,
  4567. + ETHMAC2_ppe_b = 8,
  4568. + ETHMAC2_ppe_m = 0x00000100,
  4569. + ETHMAC2_lpe_b = 9,
  4570. + ETHMAC2_lpe_m = 0x00000200,
  4571. + ETHMAC2_nb_b = 12,
  4572. + ETHMAC2_nb_m = 0x00001000,
  4573. + ETHMAC2_bp_b = 13,
  4574. + ETHMAC2_bp_m = 0x00002000,
  4575. + ETHMAC2_ed_b = 14,
  4576. + ETHMAC2_ed_m = 0x00004000,
  4577. +
  4578. + ETHIPGT_ipgt_b = 0,
  4579. + ETHIPGT_ipgt_m = 0x0000007f,
  4580. +
  4581. + ETHIPGR_ipgr2_b = 0,
  4582. + ETHIPGR_ipgr2_m = 0x0000007f,
  4583. + ETHIPGR_ipgr1_b = 8,
  4584. + ETHIPGR_ipgr1_m = 0x00007f00,
  4585. +
  4586. + ETHCLRT_maxret_b = 0,
  4587. + ETHCLRT_maxret_m = 0x0000000f,
  4588. + ETHCLRT_colwin_b = 8,
  4589. + ETHCLRT_colwin_m = 0x00003f00,
  4590. +
  4591. + ETHMAXF_maxf_b = 0,
  4592. + ETHMAXF_maxf_m = 0x0000ffff,
  4593. +
  4594. + ETHMTEST_tb_b = 2,
  4595. + ETHMTEST_tb_m = 0x00000004,
  4596. +
  4597. + ETHMCP_div_b = 0,
  4598. + ETHMCP_div_m = 0x000000ff,
  4599. +
  4600. + MIIMCFG_rsv_b = 0,
  4601. + MIIMCFG_rsv_m = 0x0000000c,
  4602. +
  4603. + MIIMCMD_rd_b = 0,
  4604. + MIIMCMD_rd_m = 0x00000001,
  4605. + MIIMCMD_scn_b = 1,
  4606. + MIIMCMD_scn_m = 0x00000002,
  4607. +
  4608. + MIIMADDR_regaddr_b = 0,
  4609. + MIIMADDR_regaddr_m = 0x0000001f,
  4610. + MIIMADDR_phyaddr_b = 8,
  4611. + MIIMADDR_phyaddr_m = 0x00001f00,
  4612. +
  4613. + MIIMWTD_wdata_b = 0,
  4614. + MIIMWTD_wdata_m = 0x0000ffff,
  4615. +
  4616. + MIIMRDD_rdata_b = 0,
  4617. + MIIMRDD_rdata_m = 0x0000ffff,
  4618. +
  4619. + MIIMIND_bsy_b = 0,
  4620. + MIIMIND_bsy_m = 0x00000001,
  4621. + MIIMIND_scn_b = 1,
  4622. + MIIMIND_scn_m = 0x00000002,
  4623. + MIIMIND_nv_b = 2,
  4624. + MIIMIND_nv_m = 0x00000004,
  4625. +
  4626. +} ;
  4627. +
  4628. +/*
  4629. + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
  4630. + */
  4631. +enum
  4632. +{
  4633. + ETHRX_fd_b = 0,
  4634. + ETHRX_fd_m = 0x00000001,
  4635. + ETHRX_ld_b = 1,
  4636. + ETHRX_ld_m = 0x00000002,
  4637. + ETHRX_rok_b = 2,
  4638. + ETHRX_rok_m = 0x00000004,
  4639. + ETHRX_fm_b = 3,
  4640. + ETHRX_fm_m = 0x00000008,
  4641. + ETHRX_mp_b = 4,
  4642. + ETHRX_mp_m = 0x00000010,
  4643. + ETHRX_bp_b = 5,
  4644. + ETHRX_bp_m = 0x00000020,
  4645. + ETHRX_vlt_b = 6,
  4646. + ETHRX_vlt_m = 0x00000040,
  4647. + ETHRX_cf_b = 7,
  4648. + ETHRX_cf_m = 0x00000080,
  4649. + ETHRX_ovr_b = 8,
  4650. + ETHRX_ovr_m = 0x00000100,
  4651. + ETHRX_crc_b = 9,
  4652. + ETHRX_crc_m = 0x00000200,
  4653. + ETHRX_cv_b = 10,
  4654. + ETHRX_cv_m = 0x00000400,
  4655. + ETHRX_db_b = 11,
  4656. + ETHRX_db_m = 0x00000800,
  4657. + ETHRX_le_b = 12,
  4658. + ETHRX_le_m = 0x00001000,
  4659. + ETHRX_lor_b = 13,
  4660. + ETHRX_lor_m = 0x00002000,
  4661. + ETHRX_ces_b = 14,
  4662. + ETHRX_ces_m = 0x00004000,
  4663. + ETHRX_length_b = 16,
  4664. + ETHRX_length_m = 0xffff0000,
  4665. +
  4666. + ETHTX_fd_b = 0,
  4667. + ETHTX_fd_m = 0x00000001,
  4668. + ETHTX_ld_b = 1,
  4669. + ETHTX_ld_m = 0x00000002,
  4670. + ETHTX_oen_b = 2,
  4671. + ETHTX_oen_m = 0x00000004,
  4672. + ETHTX_pen_b = 3,
  4673. + ETHTX_pen_m = 0x00000008,
  4674. + ETHTX_cen_b = 4,
  4675. + ETHTX_cen_m = 0x00000010,
  4676. + ETHTX_hen_b = 5,
  4677. + ETHTX_hen_m = 0x00000020,
  4678. + ETHTX_tok_b = 6,
  4679. + ETHTX_tok_m = 0x00000040,
  4680. + ETHTX_mp_b = 7,
  4681. + ETHTX_mp_m = 0x00000080,
  4682. + ETHTX_bp_b = 8,
  4683. + ETHTX_bp_m = 0x00000100,
  4684. + ETHTX_und_b = 9,
  4685. + ETHTX_und_m = 0x00000200,
  4686. + ETHTX_of_b = 10,
  4687. + ETHTX_of_m = 0x00000400,
  4688. + ETHTX_ed_b = 11,
  4689. + ETHTX_ed_m = 0x00000800,
  4690. + ETHTX_ec_b = 12,
  4691. + ETHTX_ec_m = 0x00001000,
  4692. + ETHTX_lc_b = 13,
  4693. + ETHTX_lc_m = 0x00002000,
  4694. + ETHTX_td_b = 14,
  4695. + ETHTX_td_m = 0x00004000,
  4696. + ETHTX_crc_b = 15,
  4697. + ETHTX_crc_m = 0x00008000,
  4698. + ETHTX_le_b = 16,
  4699. + ETHTX_le_m = 0x00010000,
  4700. + ETHTX_cc_b = 17,
  4701. + ETHTX_cc_m = 0x001E0000,
  4702. +} ;
  4703. +
  4704. +enum
  4705. +{
  4706. + ETH0_IPABMC_PhysicalAddress = 0x18040010,
  4707. + ETH0_IPABMC_VirtualAddress = 0xb8040000,
  4708. + ETH1_IPABMC_PhysicalAddress = 0x18040018,
  4709. + ETH1_IPABMC_VirtualAddress = 0xb8040018,
  4710. +} ;
  4711. +
  4712. +typedef struct
  4713. +{
  4714. + u32 ipabmcrx ;
  4715. + u32 ipabmctx ;
  4716. +}volatile *IPABM_ETH_t;
  4717. +#endif //__IDT_RC32365_ETH_H__
  4718. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
  4719. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 1969-12-31 19:00:00.000000000 -0500
  4720. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 2007-09-20 00:16:52.000000000 -0400
  4721. @@ -0,0 +1,72 @@
  4722. +/**************************************************************************
  4723. + *
  4724. + * BRIEF MODULE DESCRIPTION
  4725. + * RC32365/336 Ethernet status checking.
  4726. + *
  4727. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  4728. + *
  4729. + * This program is free software; you can redistribute it and/or modify it
  4730. + * under the terms of the GNU General Public License as published by the
  4731. + * Free Software Foundation; either version 2 of the License, or (at your
  4732. + * option) any later version.
  4733. + *
  4734. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  4735. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  4736. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  4737. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  4738. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  4739. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  4740. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  4741. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  4742. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  4743. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  4744. + *
  4745. + * You should have received a copy of the GNU General Public License along
  4746. + * with this program; if not, write to the Free Software Foundation, Inc.,
  4747. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  4748. + *
  4749. + *
  4750. + **************************************************************************
  4751. + * May 2004 P. Sadik.
  4752. + *
  4753. + * Initial Release
  4754. + *
  4755. + *
  4756. + *
  4757. + **************************************************************************
  4758. + */
  4759. +
  4760. +#ifndef __IDT_RC32365_ETH_V_H__
  4761. +#define __IDT_RC32365_ETH_V_H__
  4762. +#include <asm/idt-boards/rc32300/rc32365_eth.h>
  4763. +
  4764. +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
  4765. +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
  4766. +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
  4767. +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
  4768. +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
  4769. +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
  4770. +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
  4771. +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
  4772. +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
  4773. +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
  4774. +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
  4775. +
  4776. +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
  4777. +
  4778. +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
  4779. +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
  4780. +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
  4781. +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
  4782. +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
  4783. +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
  4784. +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
  4785. +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
  4786. +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
  4787. +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
  4788. +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
  4789. +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
  4790. +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
  4791. +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
  4792. +
  4793. +#endif //__IDT_RC32365_ETH_V_H__
  4794. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
  4795. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 1969-12-31 19:00:00.000000000 -0500
  4796. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 2007-09-20 00:16:52.000000000 -0400
  4797. @@ -0,0 +1,181 @@
  4798. +/**************************************************************************
  4799. + *
  4800. + * BRIEF MODULE DESCRIPTION
  4801. + * RC32365/336 GPIO hardware abstraction.
  4802. + *
  4803. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  4804. + *
  4805. + * This program is free software; you can redistribute it and/or modify it
  4806. + * under the terms of the GNU General Public License as published by the
  4807. + * Free Software Foundation; either version 2 of the License, or (at your
  4808. + * option) any later version.
  4809. + *
  4810. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  4811. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  4812. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  4813. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  4814. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  4815. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  4816. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  4817. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  4818. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  4819. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  4820. + *
  4821. + * You should have received a copy of the GNU General Public License along
  4822. + * with this program; if not, write to the Free Software Foundation, Inc.,
  4823. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  4824. + *
  4825. + *
  4826. + **************************************************************************
  4827. + * May 2004 P. Sadik.
  4828. + *
  4829. + * Initial Release
  4830. + *
  4831. + *
  4832. + *
  4833. + **************************************************************************
  4834. + */
  4835. +
  4836. +#ifndef __IDT_RC32365_GPIO_H__
  4837. +#define __IDT_RC32365_GPIO_H__
  4838. +
  4839. +enum
  4840. +{
  4841. + GPIO0_PhysicalAddress = 0x18048000,
  4842. + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
  4843. +
  4844. + GPIO0_VirtualAddress = 0xb8048000,
  4845. + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
  4846. +} ;
  4847. +
  4848. +typedef struct
  4849. +{
  4850. + u32 gpiofunc; /* GPIO Function Register
  4851. + * gpiofunc[x]==0 bit = gpio
  4852. + * func[x]==1 bit = altfunc
  4853. + */
  4854. + u32 gpiocfg; /* GPIO Configuration Register
  4855. + * gpiocfg[x]==0 bit = input
  4856. + * gpiocfg[x]==1 bit = output
  4857. + */
  4858. + u32 gpiod; /* GPIO Data Register
  4859. + * gpiod[x] read/write gpio pinX status
  4860. + */
  4861. + u32 gpioilevel; /* GPIO Interrupt Status Register
  4862. + * interrupt level (see gpioistat)
  4863. + */
  4864. + u32 gpioistat; /* Gpio Interrupt Status Register
  4865. + * istat[x] = (gpiod[x] == level[x])
  4866. + * cleared in ISR (STICKY bits)
  4867. + */
  4868. + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
  4869. +} volatile * GPIO_t ;
  4870. +
  4871. +typedef enum
  4872. +{
  4873. + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
  4874. + GPIO_alt_v = 1, // gpiofunc use pin as alt.
  4875. + GPIO_input_v = 0, // gpiocfg use pin as input.
  4876. + GPIO_output_v = 1, // gpiocfg use pin as output.
  4877. + GPIO_pin0_b = 0,
  4878. + GPIO_pin0_m = 0x00000001,
  4879. + GPIO_pin1_b = 1,
  4880. + GPIO_pin1_m = 0x00000002,
  4881. + GPIO_pin2_b = 2,
  4882. + GPIO_pin2_m = 0x00000004,
  4883. + GPIO_pin3_b = 3,
  4884. + GPIO_pin3_m = 0x00000008,
  4885. + GPIO_pin4_b = 4,
  4886. + GPIO_pin4_m = 0x00000010,
  4887. + GPIO_pin5_b = 5,
  4888. + GPIO_pin5_m = 0x00000020,
  4889. + GPIO_pin6_b = 6,
  4890. + GPIO_pin6_m = 0x00000040,
  4891. + GPIO_pin7_b = 7,
  4892. + GPIO_pin7_m = 0x00000080,
  4893. + GPIO_pin8_b = 8,
  4894. + GPIO_pin8_m = 0x00000100,
  4895. + GPIO_pin9_b = 9,
  4896. + GPIO_pin9_m = 0x00000200,
  4897. + GPIO_pin10_b = 10,
  4898. + GPIO_pin10_m = 0x00000400,
  4899. + GPIO_pin11_b = 11,
  4900. + GPIO_pin11_m = 0x00000800,
  4901. + GPIO_pin12_b = 12,
  4902. + GPIO_pin12_m = 0x00001000,
  4903. + GPIO_pin13_b = 13,
  4904. + GPIO_pin13_m = 0x00002000,
  4905. + GPIO_pin14_b = 14,
  4906. + GPIO_pin14_m = 0x00004000,
  4907. + GPIO_pin15_b = 15,
  4908. + GPIO_pin15_m = 0x00008000,
  4909. +
  4910. +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
  4911. +
  4912. + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
  4913. + GPIO_u0sout_m = GPIO_pin0_m,
  4914. + GPIO_u0sout_cfg_v = GPIO_output_v,
  4915. +
  4916. + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
  4917. + GPIO_u0sinp_m = GPIO_pin1_m,
  4918. + GPIO_u0sinp_cfg_v = GPIO_input_v,
  4919. +
  4920. + GPIO_maddr22_b = GPIO_pin2_b, // M&P bus bit 22.
  4921. + GPIO_maddr22_m = GPIO_pin2_m,
  4922. + GPIO_maddr22_cfg_v = GPIO_output_v,
  4923. +
  4924. + GPIO_maddr23_b = GPIO_pin3_b, // M&P bus bit 23.
  4925. + GPIO_maddr23_m = GPIO_pin3_m,
  4926. + GPIO_maddr23_cfg_v = GPIO_output_v,
  4927. +
  4928. + GPIO_maddr24_b = GPIO_pin4_b, // M&P bus bit 24.
  4929. + GPIO_maddr24_m = GPIO_pin4_m,
  4930. + GPIO_maddr24_cfg_v = GPIO_output_v,
  4931. +
  4932. + GPIO_maddr25_b = GPIO_pin5_b, // M&P bus bit 25.
  4933. + GPIO_maddr25_m = GPIO_pin5_m,
  4934. + GPIO_maddr25_cfg_v = GPIO_output_v,
  4935. +
  4936. + GPIO_rngclk_b = GPIO_pin6_b, // reserved.
  4937. + GPIO_rngclk_m = GPIO_pin6_m,
  4938. + GPIO_rngclk_cfg_v = GPIO_input_v,
  4939. +
  4940. + GPIO_sdckenp_b = GPIO_pin7_b, // reserved.
  4941. + GPIO_sdckenp_m = GPIO_pin7_m,
  4942. + GPIO_sdckenp_cfg_v = GPIO_output_v,
  4943. +
  4944. + GPIO_cen1_b = GPIO_pin8_b, // reserved.
  4945. + GPIO_cen1_m = GPIO_pin8_m,
  4946. + GPIO_cen1_cfg_v = GPIO_output_v,
  4947. +
  4948. + GPIO_cen2_b = GPIO_pin9_b, // reserved.
  4949. + GPIO_cen2_m = GPIO_pin9_m,
  4950. + GPIO_cen2_cfg_v = GPIO_output_v,
  4951. +
  4952. + GPIO_regn_b = GPIO_pin10_b, // reserved.
  4953. + GPIO_regn_m = GPIO_pin10_m,
  4954. + GPIO_regn_cfg_v = GPIO_output_v,
  4955. +
  4956. + GPIO_iordn_b = GPIO_pin11_b, // reserved.
  4957. + GPIO_iordn_m = GPIO_pin11_m,
  4958. + GPIO_iordn_cfg_v = GPIO_output_v,
  4959. +
  4960. + GPIO_iowrn_b = GPIO_pin12_b, // reserved.
  4961. + GPIO_iowrn_m = GPIO_pin12_m,
  4962. + GPIO_iowrn_cfg_v = GPIO_output_v,
  4963. +
  4964. + GPIO_pcireqn2_b = GPIO_pin13_b, // PCI messaging int.
  4965. + GPIO_pcireqn2_m = GPIO_pin13_m,
  4966. + GPIO_pcireqn2_cfg_v = GPIO_input_v,
  4967. +
  4968. + GPIO_pcigntn2_b = GPIO_pin14_b, // PCI messaging int.
  4969. + GPIO_pcigntn2_m = GPIO_pin14_m,
  4970. + GPIO_pcigntn2_cfg_v = GPIO_output_v,
  4971. +
  4972. + GPIO_pcimuintn_b = GPIO_pin15_b, // PCI messaging int.
  4973. + GPIO_pcimuintn_m = GPIO_pin15_m,
  4974. + GPIO_pcimuintn_cfg_v= GPIO_output_v,
  4975. +
  4976. +} GPIO_DEFS_t;
  4977. +
  4978. +#endif //__IDT_RC32365_GPIO_H__
  4979. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
  4980. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 1969-12-31 19:00:00.000000000 -0500
  4981. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 2007-09-20 00:16:52.000000000 -0400
  4982. @@ -0,0 +1,91 @@
  4983. +/**************************************************************************
  4984. + *
  4985. + * BRIEF MODULE DESCRIPTION
  4986. + * Routines to set/clear/toggle GPIO on RC32365
  4987. + *
  4988. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  4989. + *
  4990. + * This program is free software; you can redistribute it and/or modify it
  4991. + * under the terms of the GNU General Public License as published by the
  4992. + * Free Software Foundation; either version 2 of the License, or (at your
  4993. + * option) any later version.
  4994. + *
  4995. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  4996. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  4997. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  4998. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  4999. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  5000. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  5001. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  5002. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  5003. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  5004. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  5005. + *
  5006. + * You should have received a copy of the GNU General Public License along
  5007. + * with this program; if not, write to the Free Software Foundation, Inc.,
  5008. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  5009. + *
  5010. + *
  5011. + **************************************************************************
  5012. + * May 2004 P. Sadik.
  5013. + *
  5014. + * Initial Release
  5015. + *
  5016. + *
  5017. + *
  5018. + **************************************************************************
  5019. + */
  5020. +#ifndef __IDT_RC32365_GPIO_V_H__
  5021. +#define __IDT_RC32365_GPIO_V_H__
  5022. +
  5023. +
  5024. +#ifdef _LANGUAGE_ASSEMBLY
  5025. +#define SET_GPIO(pin) \
  5026. + lui t5,0xb804 ; \
  5027. + ori t5,t5,0x8000 ; \
  5028. + lw t4,8(t5) ; \
  5029. + ori t4,t4,pin ; \
  5030. + sw t4,8(t5) ;
  5031. +
  5032. +#define CLEAR_GPIO(pin) \
  5033. + lui t5,0xb804 ; \
  5034. + ori t5,t5,0x8000 ; \
  5035. + lw t4,8(t5) ; \
  5036. + lui t6,0xFFFF; \
  5037. + ori t6,t6,0xFFFF; \
  5038. + xori t6,t6,pin ; \
  5039. + and t4,t6 ; \
  5040. + sw t4,8(t5) ;
  5041. +
  5042. +#define TOGGLE_GPIO(pin) \
  5043. + lui t5,0xb804 ; \
  5044. + ori t5,t5,0x8000 ; \
  5045. + lw t4,8(t5) ; \
  5046. + xori t4,t4,pin ; \
  5047. + sw t4,8(t5) ;
  5048. +
  5049. +#else // !_LANGUAGE_ASSEMBLY
  5050. +#include <asm/rc32300/types.h>
  5051. +#include <asm/rc32300/rc32365_gpio.h>
  5052. +#include <asm/rc32300/rc32365.h>
  5053. +
  5054. +static inline void set_gpio(unsigned long pin)
  5055. +{
  5056. + idt_gpio->gpiod |= pin;
  5057. +}
  5058. +
  5059. +static inline void clear_gpio(unsigned long pin)
  5060. +{
  5061. + idt_gpio->gpiod &= ~pin;
  5062. +}
  5063. +static inline void toggle_gpio(unsigned long pin)
  5064. +{
  5065. + idt_gpio->gpiod ^= pin;
  5066. +}
  5067. +#define SET_GPIO(pin) set_gpio(pin)
  5068. +#define CLEAR_GPIO(pin) clear_gpio(pin)
  5069. +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
  5070. +#endif // _LANGUAGE_ASSEMBLY
  5071. +
  5072. +#endif //__IDT_RC32365_GPIO_V_H__
  5073. +
  5074. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
  5075. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 1969-12-31 19:00:00.000000000 -0500
  5076. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2007-09-20 00:16:52.000000000 -0400
  5077. @@ -0,0 +1,515 @@
  5078. +/**************************************************************************
  5079. + *
  5080. + * BRIEF MODULE DESCRIPTION
  5081. + * Datatype declaration for IDT 79EB365/336 PCI
  5082. + *
  5083. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  5084. + *
  5085. + * This program is free software; you can redistribute it and/or modify it
  5086. + * under the terms of the GNU General Public License as published by the
  5087. + * Free Software Foundation; either version 2 of the License, or (at your
  5088. + * option) any later version.
  5089. + *
  5090. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  5091. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  5092. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  5093. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  5094. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  5095. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  5096. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  5097. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  5098. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  5099. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  5100. + *
  5101. + * You should have received a copy of the GNU General Public License along
  5102. + * with this program; if not, write to the Free Software Foundation, Inc.,
  5103. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  5104. + *
  5105. + *
  5106. + **************************************************************************
  5107. + * May 2004 P. Sadik.
  5108. + *
  5109. + * Initial Release
  5110. + *
  5111. + *
  5112. + *
  5113. + **************************************************************************
  5114. + */
  5115. +
  5116. +#ifndef __IDT_RC32365_PCI_H__
  5117. +#define __IDT_RC32365_PCI_H__
  5118. +
  5119. +enum
  5120. +{
  5121. + PCI0_PhysicalAddress = 0x18068000,
  5122. + PCI_PhysicalAddress = PCI0_PhysicalAddress,
  5123. +
  5124. + PCI0_VirtualAddress = 0xb8068000,
  5125. + PCI_VirtualAddress = PCI0_VirtualAddress,
  5126. +} ;
  5127. +
  5128. +enum
  5129. +{
  5130. + PCI_LbaCount = 4, // Local base addresses.
  5131. +} ;
  5132. +
  5133. +typedef struct
  5134. +{
  5135. + u32 a ; // Address.
  5136. + u32 c ; // Control.
  5137. + u32 m ; // mapping.
  5138. +} PCI_Map_s ;
  5139. +
  5140. +typedef struct
  5141. +{
  5142. + u32 pcic ;
  5143. + u32 pcis ;
  5144. + u32 pcism ;
  5145. + u32 pcicfga ;
  5146. + u32 pcicfgd ;
  5147. + PCI_Map_s pcilba [PCI_LbaCount] ;
  5148. + u32 pcidac ;
  5149. + u32 pcidas ;
  5150. + u32 pcidasm ;
  5151. + u32 pcidad ;
  5152. + u32 pcidma8c ;
  5153. + u32 pcidma9c ;
  5154. + u32 pcitc ;
  5155. +} volatile *PCI_t ;
  5156. +
  5157. +// PCI messaging unit.
  5158. +enum
  5159. +{
  5160. + PCIM_Count = 2,
  5161. +} ;
  5162. +typedef struct
  5163. +{
  5164. + u32 pciim [PCIM_Count] ;
  5165. + u32 pciom [PCIM_Count] ;
  5166. + u32 pciid ;
  5167. + u32 pciiic ;
  5168. + u32 pciiim ;
  5169. + u32 pciiod ;
  5170. + u32 pciioic ;
  5171. + u32 pciioim ;
  5172. +} volatile *PCIM_t ;
  5173. +
  5174. +/*******************************************************************************
  5175. + *
  5176. + * PCI Control Register
  5177. + *
  5178. + ******************************************************************************/
  5179. +enum
  5180. +{
  5181. + PCIC_en_b = 0,
  5182. + PCIC_en_m = 0x00000001,
  5183. + PCIC_tnr_b = 1,
  5184. + PCIC_tnr_m = 0x00000002,
  5185. + PCIC_sce_b = 2,
  5186. + PCIC_sce_m = 0x00000004,
  5187. + PCIC_ien_b = 3,
  5188. + PCIC_ien_m = 0x00000008,
  5189. + PCIC_aaa_b = 4,
  5190. + PCIC_aaa_m = 0x00000010,
  5191. + PCIC_eap_b = 5,
  5192. + PCIC_eap_m = 0x00000020,
  5193. + PCIC_pcim_b = 6,
  5194. + PCIC_pcim_m = 0x000001c0,
  5195. + PCIC_pcim_disabled_v = 0,
  5196. + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
  5197. + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
  5198. + PCIC_pcim_extern_v = 3, // Host - external arbiter.
  5199. + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
  5200. + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
  5201. + PCIC_pcim_reserved6_v = 6,
  5202. + PCIC_pcim_reserved7_v = 7,
  5203. + PCIC_igm_b = 9,
  5204. + PCIC_igm_m = 0x00000200,
  5205. +} ;
  5206. +
  5207. +/*******************************************************************************
  5208. + *
  5209. + * PCI Status Register
  5210. + *
  5211. + ******************************************************************************/
  5212. +enum {
  5213. + PCIS_eed_b = 0,
  5214. + PCIS_eed_m = 0x00000001,
  5215. + PCIS_wr_b = 1,
  5216. + PCIS_wr_m = 0x00000002,
  5217. + PCIS_nmi_b = 2,
  5218. + PCIS_nmi_m = 0x00000004,
  5219. + PCIS_ii_b = 3,
  5220. + PCIS_ii_m = 0x00000008,
  5221. + PCIS_cwe_b = 4,
  5222. + PCIS_cwe_m = 0x00000010,
  5223. + PCIS_cre_b = 5,
  5224. + PCIS_cre_m = 0x00000020,
  5225. + PCIS_mdpe_b = 6,
  5226. + PCIS_mdpe_m = 0x00000040,
  5227. + PCIS_sta_b = 7,
  5228. + PCIS_sta_m = 0x00000080,
  5229. + PCIS_rta_b = 8,
  5230. + PCIS_rta_m = 0x00000100,
  5231. + PCIS_rma_b = 9,
  5232. + PCIS_rma_m = 0x00000200,
  5233. + PCIS_sse_b = 10,
  5234. + PCIS_sse_m = 0x00000400,
  5235. + PCIS_ose_b = 11,
  5236. + PCIS_ose_m = 0x00000800,
  5237. + PCIS_pe_b = 12,
  5238. + PCIS_pe_m = 0x00001000,
  5239. + PCIS_tae_b = 13,
  5240. + PCIS_tae_m = 0x00002000,
  5241. + PCIS_rle_b = 14,
  5242. + PCIS_rle_m = 0x00004000,
  5243. + PCIS_bme_b = 15,
  5244. + PCIS_bme_m = 0x00008000,
  5245. + PCIS_prd_b = 16,
  5246. + PCIS_prd_m = 0x00010000,
  5247. + PCIS_rip_b = 17,
  5248. + PCIS_rip_m = 0x00020000,
  5249. +} ;
  5250. +
  5251. +/*******************************************************************************
  5252. + *
  5253. + * PCI Status Mask Register
  5254. + *
  5255. + ******************************************************************************/
  5256. +enum {
  5257. + PCISM_eed_b = 0,
  5258. + PCISM_eed_m = 0x00000001,
  5259. + PCISM_wr_b = 1,
  5260. + PCISM_wr_m = 0x00000002,
  5261. + PCISM_nmi_b = 2,
  5262. + PCISM_nmi_m = 0x00000004,
  5263. + PCISM_ii_b = 3,
  5264. + PCISM_ii_m = 0x00000008,
  5265. + PCISM_cwe_b = 4,
  5266. + PCISM_cwe_m = 0x00000010,
  5267. + PCISM_cre_b = 5,
  5268. + PCISM_cre_m = 0x00000020,
  5269. + PCISM_mdpe_b = 6,
  5270. + PCISM_mdpe_m = 0x00000040,
  5271. + PCISM_sta_b = 7,
  5272. + PCISM_sta_m = 0x00000080,
  5273. + PCISM_rta_b = 8,
  5274. + PCISM_rta_m = 0x00000100,
  5275. + PCISM_rma_b = 9,
  5276. + PCISM_rma_m = 0x00000200,
  5277. + PCISM_sse_b = 10,
  5278. + PCISM_sse_m = 0x00000400,
  5279. + PCISM_ose_b = 11,
  5280. + PCISM_ose_m = 0x00000800,
  5281. + PCISM_pe_b = 12,
  5282. + PCISM_pe_m = 0x00001000,
  5283. + PCISM_tae_b = 13,
  5284. + PCISM_tae_m = 0x00002000,
  5285. + PCISM_rle_b = 14,
  5286. + PCISM_rle_m = 0x00004000,
  5287. + PCISM_bme_b = 15,
  5288. + PCISM_bme_m = 0x00008000,
  5289. + PCISM_prd_b = 16,
  5290. + PCISM_prd_m = 0x00010000,
  5291. + PCISM_rip_b = 17,
  5292. + PCISM_rip_m = 0x00020000,
  5293. +} ;
  5294. +
  5295. +/*******************************************************************************
  5296. + *
  5297. + * PCI Configuration Address Register
  5298. + *
  5299. + ******************************************************************************/
  5300. +enum {
  5301. + PCICFGA_reg_b = 2,
  5302. + PCICFGA_reg_m = 0x000000fc,
  5303. + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
  5304. + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
  5305. + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
  5306. + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
  5307. + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
  5308. + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
  5309. + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
  5310. + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
  5311. + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
  5312. + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
  5313. + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
  5314. + PCICFGA_reg_pba0m_v = 0x48>>2,
  5315. + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
  5316. + PCICFGA_reg_pba1m_v = 0x50>>2,
  5317. + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
  5318. + PCICFGA_reg_pba2m_v = 0x58>>2,
  5319. + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
  5320. + PCICFGA_reg_pba3m_v = 0x60>>2,
  5321. + PCICFGA_reg_pmgt_v = 0x64>>2,
  5322. + PCICFGA_func_b = 8,
  5323. + PCICFGA_func_m = 0x00000700,
  5324. + PCICFGA_dev_b = 11,
  5325. + PCICFGA_dev_m = 0x0000f800,
  5326. + PCICFGA_dev_internal_v = 0,
  5327. + PCICFGA_bus_b = 16,
  5328. + PCICFGA_bus_m = 0x00ff0000,
  5329. + PCICFGA_bus_type0_v = 0, //local bus
  5330. + PCICFGA_en_b = 31, // read only
  5331. + PCICFGA_en_m = 0x80000000,
  5332. +} ;
  5333. +
  5334. +enum {
  5335. + PCFGID_vendor_b = 0,
  5336. + PCFGID_vendor_m = 0x0000ffff,
  5337. + PCFGID_vendor_IDT_v = 0x111d,
  5338. + PCFGID_device_b = 16,
  5339. + PCFGID_device_m = 0xffff0000,
  5340. + PCFGID_device_Acaciade_v = 0x0207,
  5341. +
  5342. + PCFG04_command_ioena_b = 1,
  5343. + PCFG04_command_ioena_m = 0x00000001,
  5344. + PCFG04_command_memena_b = 2,
  5345. + PCFG04_command_memena_m = 0x00000002,
  5346. + PCFG04_command_bmena_b = 3,
  5347. + PCFG04_command_bmena_m = 0x00000004,
  5348. + PCFG04_command_mwinv_b = 5,
  5349. + PCFG04_command_mwinv_m = 0x00000010,
  5350. + PCFG04_command_parena_b = 7,
  5351. + PCFG04_command_parena_m = 0x00000040,
  5352. + PCFG04_command_serrena_b = 9,
  5353. + PCFG04_command_serrena_m = 0x00000100,
  5354. + PCFG04_command_fastbbena_b = 10,
  5355. + PCFG04_command_fastbbena_m = 0x00000200,
  5356. + PCFG04_status_b = 16,
  5357. + PCFG04_status_m = 0xffff0000,
  5358. + PCFG04_status_66MHz_b = 21, // 66 MHz enable
  5359. + PCFG04_status_66MHz_m = 0x00200000,
  5360. + PCFG04_status_fbb_b = 23,
  5361. + PCFG04_status_fbb_m = 0x00800000,
  5362. + PCFG04_status_mdpe_b = 24,
  5363. + PCFG04_status_mdpe_m = 0x01000000,
  5364. + PCFG04_status_dst_b = 25,
  5365. + PCFG04_status_dst_m = 0x06000000,
  5366. + PCFG04_status_sta_b = 27,
  5367. + PCFG04_status_sta_m = 0x08000000,
  5368. + PCFG04_status_rta_b = 28,
  5369. + PCFG04_status_rta_m = 0x10000000,
  5370. + PCFG04_status_rma_b = 29,
  5371. + PCFG04_status_rma_m = 0x20000000,
  5372. + PCFG04_status_sse_b = 30,
  5373. + PCFG04_status_sse_m = 0x40000000,
  5374. + PCFG04_status_pe_b = 31,
  5375. + PCFG04_status_pe_m = 0x40000000,
  5376. +
  5377. + PCFG08_revId_b = 0,
  5378. + PCFG08_revId_m = 0x000000ff,
  5379. + PCFG08_classCode_b = 0,
  5380. + PCFG08_classCode_m = 0xffffff00,
  5381. + PCFG08_classCode_bridge_v = 06,
  5382. + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
  5383. + PCFG0C_cacheline_b = 0,
  5384. + PCFG0C_cacheline_m = 0x000000ff,
  5385. + PCFG0C_masterLatency_b = 8,
  5386. + PCFG0C_masterLatency_m = 0x0000ff00,
  5387. + PCFG0C_headerType_b = 16,
  5388. + PCFG0C_headerType_m = 0x00ff0000,
  5389. + PCFG0C_bist_b = 24,
  5390. + PCFG0C_bist_m = 0xff000000,
  5391. +
  5392. + PCIPBA_msi_b = 0,
  5393. + PCIPBA_msi_m = 0x00000001,
  5394. + PCIPBA_p_b = 3,
  5395. + PCIPBA_p_m = 0x00000004,
  5396. + PCIPBA_baddr_b = 8,
  5397. + PCIPBA_baddr_m = 0xffffff00,
  5398. +
  5399. + PCFGSS_vendorId_b = 0,
  5400. + PCFGSS_vendorId_m = 0x0000ffff,
  5401. + PCFGSS_id_b = 16,
  5402. + PCFGSS_id_m = 0xffff0000,
  5403. +
  5404. + PCFG3C_interruptLine_b = 0,
  5405. + PCFG3C_interruptLine_m = 0x000000ff,
  5406. + PCFG3C_interruptPin_b = 8,
  5407. + PCFG3C_interruptPin_m = 0x0000ff00,
  5408. + PCFG3C_minGrant_b = 16,
  5409. + PCFG3C_minGrant_m = 0x00ff0000,
  5410. + PCFG3C_maxLat_b = 24,
  5411. + PCFG3C_maxLat_m = 0xff000000,
  5412. +
  5413. + PCIPBAC_msi_b = 0,
  5414. + PCIPBAC_msi_m = 0x00000001,
  5415. + PCIPBAC_p_b = 1,
  5416. + PCIPBAC_p_m = 0x00000002,
  5417. + PCIPBAC_size_b = 2,
  5418. + PCIPBAC_size_m = 0x0000007c,
  5419. + PCIPBAC_sb_b = 7,
  5420. + PCIPBAC_sb_m = 0x00000080,
  5421. + PCIPBAC_pp_b = 8,
  5422. + PCIPBAC_pp_m = 0x00000100,
  5423. + PCIPBAC_mr_b = 9,
  5424. + PCIPBAC_mr_m = 0x00000600,
  5425. + PCIPBAC_mr_read_v =0, //no prefetching
  5426. + PCIPBAC_mr_readLine_v =1,
  5427. + PCIPBAC_mr_readMult_v =2,
  5428. + PCIPBAC_mrl_b = 11,
  5429. + PCIPBAC_mrl_m = 0x00000800,
  5430. + PCIPBAC_mrm_b = 12,
  5431. + PCIPBAC_mrm_m = 0x00001000,
  5432. + PCIPBAC_trp_b = 13,
  5433. + PCIPBAC_trp_m = 0x00002000,
  5434. +
  5435. + PCFG40_trdyTimeout_b = 0,
  5436. + PCFG40_trdyTimeout_m = 0x000000ff,
  5437. + PCFG40_retryLim_b = 8,
  5438. + PCFG40_retryLim_m = 0x0000ff00,
  5439. +};
  5440. +
  5441. +/*******************************************************************************
  5442. + *
  5443. + * PCI Local Base Address [0|1|2|3] Register
  5444. + *
  5445. + ******************************************************************************/
  5446. +enum {
  5447. + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
  5448. + PCILBA_baddr_m = 0xffffff00,
  5449. +} ;
  5450. +/*******************************************************************************
  5451. + *
  5452. + * PCI Local Base Address Control Register
  5453. + *
  5454. + ******************************************************************************/
  5455. +enum {
  5456. + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
  5457. + PCILBAC_msi_m = 0x00000001,
  5458. + PCILBAC_msi_mem_v = 0,
  5459. + PCILBAC_msi_io_v = 1,
  5460. + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
  5461. + PCILBAC_size_m = 0x0000007c,
  5462. + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
  5463. + PCILBAC_sb_m = 0x00000080,
  5464. + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
  5465. + PCILBAC_rt_m = 0x00000100,
  5466. + PCILBAC_rt_noprefetch_v = 0, // mem read
  5467. + PCILBAC_rt_prefetch_v = 1, // mem readline
  5468. +} ;
  5469. +
  5470. +/*******************************************************************************
  5471. + *
  5472. + * PCI Local Base Address [0|1|2|3] Mapping Register
  5473. + *
  5474. + ******************************************************************************/
  5475. +enum {
  5476. + PCILBAM_maddr_b = 8,
  5477. + PCILBAM_maddr_m = 0xffffff00,
  5478. +} ;
  5479. +
  5480. +/*******************************************************************************
  5481. + *
  5482. + * PCI Decoupled Access Control Register
  5483. + *
  5484. + ******************************************************************************/
  5485. +enum {
  5486. + PCIDAC_den_b = 0,
  5487. + PCIDAC_den_m = 0x00000001,
  5488. +} ;
  5489. +
  5490. +/*******************************************************************************
  5491. + *
  5492. + * PCI Decoupled Access Status Register
  5493. + *
  5494. + ******************************************************************************/
  5495. +enum {
  5496. + PCIDAS_d_b = 0,
  5497. + PCIDAS_d_m = 0x00000001,
  5498. + PCIDAS_b_b = 1,
  5499. + PCIDAS_b_m = 0x00000002,
  5500. + PCIDAS_e_b = 2,
  5501. + PCIDAS_e_m = 0x00000004,
  5502. + PCIDAS_ofe_b = 3,
  5503. + PCIDAS_ofe_m = 0x00000008,
  5504. + PCIDAS_off_b = 4,
  5505. + PCIDAS_off_m = 0x00000010,
  5506. + PCIDAS_ife_b = 5,
  5507. + PCIDAS_ife_m = 0x00000020,
  5508. + PCIDAS_iff_b = 6,
  5509. + PCIDAS_iff_m = 0x00000040,
  5510. +} ;
  5511. +
  5512. +/*******************************************************************************
  5513. + *
  5514. + * PCI DMA Channel 8 Configuration Register
  5515. + *
  5516. + ******************************************************************************/
  5517. +enum
  5518. +{
  5519. + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
  5520. + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
  5521. + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
  5522. + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
  5523. +} ;
  5524. +
  5525. +/*******************************************************************************
  5526. + *
  5527. + * PCI DMA Channel 9 Configuration Register
  5528. + *
  5529. + ******************************************************************************/
  5530. +enum
  5531. +{
  5532. + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
  5533. + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
  5534. +} ;
  5535. +
  5536. +/*******************************************************************************
  5537. + *
  5538. + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
  5539. + *
  5540. + ******************************************************************************/
  5541. +enum {
  5542. + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
  5543. + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
  5544. + // These are for reads (DMA channel 8)
  5545. + PCIDMAD_devcmd_mr_v = 0, //memory read
  5546. + PCIDMAD_devcmd_mrl_v = 1, //memory read line
  5547. + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
  5548. + PCIDMAD_devcmd_ior_v = 3, //I/O read
  5549. + // These are for writes (DMA channel 9)
  5550. + PCIDMAD_devcmd_mw_v = 0, //memory write
  5551. + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
  5552. + PCIDMAD_devcmd_iow_v = 3, //I/O write
  5553. +
  5554. + // Swap byte field applies to both DMA channel 8 and 9
  5555. + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
  5556. + PCIDMAD_sb_m = 0x01000000, // swap byte field
  5557. +} ;
  5558. +
  5559. +
  5560. +/*******************************************************************************
  5561. + *
  5562. + * PCI Target Control Register
  5563. + *
  5564. + ******************************************************************************/
  5565. +enum
  5566. +{
  5567. + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
  5568. + PCITC_rtimer_m = 0x000000ff,
  5569. + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
  5570. + PCITC_dtimer_m = 0x0000ff00,
  5571. + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
  5572. + PCITC_rdr_m = 0x00040000,
  5573. + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
  5574. + PCITC_ddt_m = 0x00080000,
  5575. +} ;
  5576. +/*******************************************************************************
  5577. + *
  5578. + * PCI messaging unit [applies to both inbound and outbound registers ]
  5579. + *
  5580. + ******************************************************************************/
  5581. +enum
  5582. +{
  5583. + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
  5584. + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
  5585. + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
  5586. + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
  5587. + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
  5588. + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
  5589. +};
  5590. +
  5591. +
  5592. +#endif // __IDT_RC32365_PCI_H__
  5593. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
  5594. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 1969-12-31 19:00:00.000000000 -0500
  5595. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 2007-09-20 00:16:52.000000000 -0400
  5596. @@ -0,0 +1,217 @@
  5597. +/**************************************************************************
  5598. + *
  5599. + * BRIEF MODULE DESCRIPTION
  5600. + * PCI header values for IDT 79EB365/336
  5601. + *
  5602. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  5603. + *
  5604. + * This program is free software; you can redistribute it and/or modify it
  5605. + * under the terms of the GNU General Public License as published by the
  5606. + * Free Software Foundation; either version 2 of the License, or (at your
  5607. + * option) any later version.
  5608. + *
  5609. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  5610. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  5611. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  5612. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  5613. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  5614. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  5615. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  5616. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  5617. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  5618. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  5619. + *
  5620. + * You should have received a copy of the GNU General Public License along
  5621. + * with this program; if not, write to the Free Software Foundation, Inc.,
  5622. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  5623. + *
  5624. + *
  5625. + **************************************************************************
  5626. + * May 2004 P. Sadik.
  5627. + *
  5628. + * Initial Release
  5629. + *
  5630. + *
  5631. + *
  5632. + **************************************************************************
  5633. + */
  5634. +
  5635. +#ifndef __IDT_RC32365_PCI_V_H__
  5636. +#define __IDT_RC32365_PCI_V_H__
  5637. +
  5638. +
  5639. +#define PCI_MSG_VirtualAddress 0xB806C010
  5640. +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
  5641. +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
  5642. +
  5643. +#define PCIM_SHFT 0x6
  5644. +#define PCIM_BIT_LEN 0x7
  5645. +#define PCIM_H_EA 0x3
  5646. +#define PCIM_H_IA_FIX 0x4
  5647. +#define PCIM_H_IA_RR 0x5
  5648. +
  5649. +#define PCI_ADDR_START 0x50000000
  5650. +
  5651. +#define CPUTOPCI_MEM_WIN 0x02000000
  5652. +#define CPUTOPCI_IO_WIN 0x00100000
  5653. +#define PCILBA_SIZE_SHFT 2
  5654. +#define PCILBA_SIZE_MASK 0x1F
  5655. +#define SIZE_256MB 0x1C
  5656. +#define SIZE_128MB 0x1B
  5657. +#define SIZE_64MB 0x1A
  5658. +#define SIZE_32MB 0x19
  5659. +#define SIZE_16MB 0x18
  5660. +#define SIZE_4MB 0x16
  5661. +#define SIZE_2MB 0x15
  5662. +#define SIZE_1MB 0x14
  5663. +#define CEDAR_CONFIG0_ADDR 0x80000000
  5664. +#define CEDAR_CONFIG1_ADDR 0x80000004
  5665. +#define CEDAR_CONFIG2_ADDR 0x80000008
  5666. +#define CEDAR_CONFIG3_ADDR 0x8000000C
  5667. +#define CEDAR_CONFIG4_ADDR 0x80000010
  5668. +#define CEDAR_CONFIG5_ADDR 0x80000014
  5669. +#define CEDAR_CONFIG6_ADDR 0x80000018
  5670. +#define CEDAR_CONFIG7_ADDR 0x8000001C
  5671. +#define CEDAR_CONFIG8_ADDR 0x80000020
  5672. +#define CEDAR_CONFIG9_ADDR 0x80000024
  5673. +#define CEDAR_CONFIG10_ADDR 0x80000028
  5674. +#define CEDAR_CONFIG11_ADDR 0x8000002C
  5675. +#define CEDAR_CONFIG12_ADDR 0x80000030
  5676. +#define CEDAR_CONFIG13_ADDR 0x80000034
  5677. +#define CEDAR_CONFIG14_ADDR 0x80000038
  5678. +#define CEDAR_CONFIG15_ADDR 0x8000003C
  5679. +#define CEDAR_CONFIG16_ADDR 0x80000040
  5680. +#define CEDAR_CONFIG17_ADDR 0x80000044
  5681. +#define CEDAR_CONFIG18_ADDR 0x80000048
  5682. +#define CEDAR_CONFIG19_ADDR 0x8000004C
  5683. +#define CEDAR_CONFIG20_ADDR 0x80000050
  5684. +#define CEDAR_CONFIG21_ADDR 0x80000054
  5685. +#define CEDAR_CONFIG22_ADDR 0x80000058
  5686. +#define CEDAR_CONFIG23_ADDR 0x8000005C
  5687. +#define CEDAR_CONFIG24_ADDR 0x80000060
  5688. +#define CEDAR_CONFIG25_ADDR 0x80000064
  5689. +#define CEDAR_CMD (PCFG04_command_ioena_m | \
  5690. + PCFG04_command_memena_m | \
  5691. + PCFG04_command_bmena_m | \
  5692. + PCFG04_command_mwinv_m | \
  5693. + PCFG04_command_parena_m | \
  5694. + PCFG04_command_serrena_m )
  5695. +
  5696. +#define CEDAR_STAT (PCFG04_status_mdpe_m | \
  5697. + PCFG04_status_sta_m | \
  5698. + PCFG04_status_rta_m | \
  5699. + PCFG04_status_rma_m | \
  5700. + PCFG04_status_sse_m | \
  5701. + PCFG04_status_pe_m)
  5702. +
  5703. +#define CEDAR_CNFG1 ((CEDAR_STAT << 16) | \
  5704. + CEDAR_CMD)
  5705. +
  5706. +#define CEDAR_REVID 0
  5707. +#define CEDAR_CLASS_CODE 0
  5708. +#define CEDAR_CNFG2 ((CEDAR_CLASS_CODE << 8) | \
  5709. + CEDAR_REVID)
  5710. +
  5711. +#define CEDAR_CACHE_LINE_SIZE 4
  5712. +#define CEDAR_MASTER_LAT 0x3c
  5713. +#define CEDAR_HEADER_TYPE 0
  5714. +#define CEDAR_BIST 0
  5715. +
  5716. +#define CEDAR_CNFG3 ((CEDAR_BIST << 24) | \
  5717. + (CEDAR_HEADER_TYPE << 16) | \
  5718. + (CEDAR_MASTER_LAT << 8) | \
  5719. + CEDAR_CACHE_LINE_SIZE)
  5720. +
  5721. +#define CEDAR_BAR0 0x00000008 /* 128 MB Memory */
  5722. +#define CEDAR_BAR1 0x18800001 /* 1 MB IO */
  5723. +#define CEDAR_BAR2 0x18000001 /* 2 MB IO window for Cedar
  5724. + internal Registers */
  5725. +#define CEDAR_BAR3 0x48000008 /* Spare 128 MB Memory */
  5726. +
  5727. +#define CEDAR_CNFG4 CEDAR_BAR0
  5728. +#define CEDAR_CNFG5 CEDAR_BAR1
  5729. +#define CEDAR_CNFG6 CEDAR_BAR2
  5730. +#define CEDAR_CNFG7 CEDAR_BAR3
  5731. +
  5732. +#define CEDAR_SUBSYS_VENDOR_ID 0
  5733. +#define CEDAR_SUBSYSTEM_ID 0
  5734. +#define CEDAR_CNFG8 0
  5735. +#define CEDAR_CNFG9 0
  5736. +#define CEDAR_CNFG10 0
  5737. +#define CEDAR_CNFG11 ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
  5738. + CEDAR_SUBSYSTEM_ID)
  5739. +#define CEDAR_INT_LINE 1
  5740. +#define CEDAR_INT_PIN 1
  5741. +#define CEDAR_MIN_GNT 8
  5742. +#define CEDAR_MAX_LAT 0x38
  5743. +#define CEDAR_CNFG12 0
  5744. +#define CEDAR_CNFG13 0
  5745. +#define CEDAR_CNFG14 0
  5746. +#define CEDAR_CNFG15 ((CEDAR_MAX_LAT << 24) | \
  5747. + (CEDAR_MIN_GNT << 16) | \
  5748. + (CEDAR_INT_PIN << 8) | \
  5749. + CEDAR_INT_LINE)
  5750. +#define CEDAR_RETRY_LIMIT 0x80
  5751. +#define CEDAR_TRDY_LIMIT 0x80
  5752. +#define CEDAR_CNFG16 ((CEDAR_RETRY_LIMIT << 8) | \
  5753. + CEDAR_TRDY_LIMIT)
  5754. +#define PCI_PBAxC_R 0x0
  5755. +#define PCI_PBAxC_RL 0x1
  5756. +#define PCI_PBAxC_RM 0x2
  5757. +#define SIZE_SHFT 2
  5758. +#ifdef __MIPSEB__
  5759. +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
  5760. + PCIPBAC_pp_m | \
  5761. + PCIPBAC_sb_m | \
  5762. + (SIZE_128MB << SIZE_SHFT) | \
  5763. + PCIPBAC_p_m)
  5764. +#else
  5765. +
  5766. +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
  5767. + PCIPBAC_pp_m | \
  5768. + (SIZE_128MB << SIZE_SHFT) | \
  5769. + PCIPBAC_p_m)
  5770. +#endif
  5771. +#define CEDAR_CNFG17 CEDAR_PBA0C
  5772. +#define CEDAR_PBA0M 0x0
  5773. +#define CEDAR_CNFG18 CEDAR_PBA0M
  5774. +
  5775. +#ifdef __MIPSEB__
  5776. +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
  5777. + PCIPBAC_sb_m | \
  5778. + PCIPBAC_msi_m)
  5779. +#else
  5780. +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
  5781. + PCIPBAC_msi_m)
  5782. +#endif
  5783. +#define CEDAR_CNFG19 CEDAR_PBA1C
  5784. +#define CEDAR_PBA1M 0x0
  5785. +#define CEDAR_CNFG20 CEDAR_PBA1M
  5786. +
  5787. +#ifdef __MIPSEB__
  5788. +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
  5789. + PCIPBAC_sb_m | \
  5790. + PCIPBAC_msi_m)
  5791. +#else
  5792. +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
  5793. + PCIPBAC_msi_m)
  5794. +#endif
  5795. +
  5796. +#define CEDAR_CNFG21 CEDAR_PBA2C
  5797. +#define CEDAR_PBA2M 0x18000000
  5798. +#define CEDAR_CNFG22 CEDAR_PBA2M
  5799. +
  5800. +#ifdef __MIPSEB__
  5801. +#define CEDAR_PBA3C PCIPBAC_sb_m
  5802. +#else
  5803. +#define CEDAR_PBA3C 0
  5804. +#endif
  5805. +
  5806. +#define CEDAR_CNFG23 CEDAR_PBA3C
  5807. +#define CEDAR_PBA3M 0
  5808. +#define CEDAR_CNFG24 CEDAR_PBA3M
  5809. +
  5810. +#define PCITC_DTIMER_VAL 8
  5811. +#define PCITC_RTIMER_VAL 0x10
  5812. +
  5813. +#endif //__IDT_RC32365_PCI_V_H__
  5814. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434.h
  5815. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434.h 1969-12-31 19:00:00.000000000 -0500
  5816. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434.h 2007-09-20 00:16:52.000000000 -0400
  5817. @@ -0,0 +1,199 @@
  5818. + /**************************************************************************
  5819. + *
  5820. + * BRIEF MODULE DESCRIPTION
  5821. + * Definitions for IDT RC32434 CPU
  5822. + *
  5823. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  5824. + *
  5825. + * This program is free software; you can redistribute it and/or modify it
  5826. + * under the terms of the GNU General Public License as published by the
  5827. + * Free Software Foundation; either version 2 of the License, or (at your
  5828. + * option) any later version.
  5829. + *
  5830. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  5831. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  5832. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  5833. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  5834. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  5835. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  5836. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  5837. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  5838. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  5839. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  5840. + *
  5841. + * You should have received a copy of the GNU General Public License along
  5842. + * with this program; if not, write to the Free Software Foundation, Inc.,
  5843. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  5844. + *
  5845. + *
  5846. + **************************************************************************
  5847. + * May 2004 rkt, neb.
  5848. + *
  5849. + * Initial Release
  5850. + *
  5851. + *
  5852. + *
  5853. + **************************************************************************
  5854. + */
  5855. +
  5856. +#ifndef _RC32434_H_
  5857. +#define _RC32434_H_
  5858. +
  5859. +#include <linux/autoconf.h>
  5860. +#include <linux/delay.h>
  5861. +#include <asm/io.h>
  5862. +#include <asm/idt-boards/rc32434/rc32434_timer.h>
  5863. +
  5864. +#define RC32434_REG_BASE 0x18000000
  5865. +
  5866. +
  5867. +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
  5868. +#define idt_timer ((volatile TIM_t) TIM0_VirtualAddress)
  5869. +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
  5870. +
  5871. +#define IDT_CLOCK_MULT 2
  5872. +#define MIPS_CPU_TIMER_IRQ 7
  5873. +/* Interrupt Controller */
  5874. +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
  5875. +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
  5876. +#define IC_GROUP_OFFSET 0x0C
  5877. +#define RTC_BASE 0xBA001FF0
  5878. +
  5879. +#define NUM_INTR_GROUPS 5
  5880. +/* 16550 UARTs */
  5881. +
  5882. +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
  5883. +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
  5884. +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
  5885. +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
  5886. +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
  5887. +
  5888. +#ifdef __MIPSEB__
  5889. +
  5890. +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
  5891. +#define EB434_UART1_BASE (0x19800003)
  5892. +
  5893. +#else
  5894. +
  5895. +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
  5896. +#define EB434_UART1_BASE (0x19800000)
  5897. +
  5898. +#endif
  5899. +
  5900. +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
  5901. +#define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
  5902. +
  5903. +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
  5904. +
  5905. +/* cpu pipeline flush */
  5906. +static inline void rc32434_sync(void)
  5907. +{
  5908. + __asm__ volatile ("sync");
  5909. +}
  5910. +
  5911. +static inline void rc32434_sync_udelay(int us)
  5912. +{
  5913. + __asm__ volatile ("sync");
  5914. + udelay(us);
  5915. +}
  5916. +
  5917. +static inline void rc32434_sync_delay(int ms)
  5918. +{
  5919. + __asm__ volatile ("sync");
  5920. + mdelay(ms);
  5921. +}
  5922. +
  5923. +
  5924. +
  5925. +/*
  5926. + * Macros to access internal RC32434 registers. No byte
  5927. + * swapping should be done when accessing the internal
  5928. + * registers.
  5929. + */
  5930. +
  5931. +#define rc32434_readb __raw_readb
  5932. +#define rc32434_readw __raw_readw
  5933. +#define rc32434_readl __raw_readl
  5934. +
  5935. +#define rc32434_writeb __raw_writeb
  5936. +#define rc32434_writew __raw_writew
  5937. +#define rc32434_writel __raw_writel
  5938. +
  5939. +#if 0
  5940. +static inline u8 rc32434_readb(unsigned long pa)
  5941. +{
  5942. + return *((volatile u8 *)KSEG1ADDR(pa));
  5943. +}
  5944. +static inline u16 rc32434_readw(unsigned long pa)
  5945. +{
  5946. + return *((volatile u16 *)KSEG1ADDR(pa));
  5947. +}
  5948. +static inline u32 rc32434_readl(unsigned long pa)
  5949. +{
  5950. + return *((volatile u32 *)KSEG1ADDR(pa));
  5951. +}
  5952. +static inline void rc32434_writeb(u8 val, unsigned long pa)
  5953. +{
  5954. + *((volatile u8 *)KSEG1ADDR(pa)) = val;
  5955. +}
  5956. +static inline void rc32434_writew(u16 val, unsigned long pa)
  5957. +{
  5958. + *((volatile u16 *)KSEG1ADDR(pa)) = val;
  5959. +}
  5960. +static inline void rc32434_writel(u32 val, unsigned long pa)
  5961. +{
  5962. + *((volatile u32 *)KSEG1ADDR(pa)) = val;
  5963. +}
  5964. +
  5965. +#endif
  5966. +
  5967. +
  5968. +/*
  5969. + * C access to CLZ and CLO instructions
  5970. + * (count leading zeroes/ones).
  5971. + */
  5972. +static inline int rc32434_clz(unsigned long val)
  5973. +{
  5974. + int ret;
  5975. + __asm__ volatile (
  5976. + ".set\tnoreorder\n\t"
  5977. + ".set\tnoat\n\t"
  5978. + ".set\tmips32\n\t"
  5979. + "clz\t%0,%1\n\t"
  5980. + ".set\tmips0\n\t"
  5981. + ".set\tat\n\t"
  5982. + ".set\treorder"
  5983. + : "=r" (ret)
  5984. + : "r" (val));
  5985. +
  5986. + return ret;
  5987. +}
  5988. +static inline int rc32434_clo(unsigned long val)
  5989. +{
  5990. + int ret;
  5991. + __asm__ volatile (
  5992. + ".set\tnoreorder\n\t"
  5993. + ".set\tnoat\n\t"
  5994. + ".set\tmips32\n\t"
  5995. + "clo\t%0,%1\n\t"
  5996. + ".set\tmips0\n\t"
  5997. + ".set\tat\n\t"
  5998. + ".set\treorder"
  5999. + : "=r" (ret)
  6000. + : "r" (val));
  6001. +
  6002. + return ret;
  6003. +}
  6004. +#endif /* _RC32434_H_ */
  6005. +
  6006. +
  6007. +
  6008. +
  6009. +
  6010. +
  6011. +
  6012. +
  6013. +
  6014. +
  6015. +
  6016. +
  6017. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
  6018. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 1969-12-31 19:00:00.000000000 -0500
  6019. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2007-09-20 00:16:52.000000000 -0400
  6020. @@ -0,0 +1,205 @@
  6021. +/**************************************************************************
  6022. + *
  6023. + * BRIEF MODULE DESCRIPTION
  6024. + * DMA register definition
  6025. + *
  6026. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  6027. + *
  6028. + * This program is free software; you can redistribute it and/or modify it
  6029. + * under the terms of the GNU General Public License as published by the
  6030. + * Free Software Foundation; either version 2 of the License, or (at your
  6031. + * option) any later version.
  6032. + *
  6033. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  6034. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  6035. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  6036. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  6037. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  6038. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  6039. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  6040. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  6041. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  6042. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  6043. + *
  6044. + * You should have received a copy of the GNU General Public License along
  6045. + * with this program; if not, write to the Free Software Foundation, Inc.,
  6046. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  6047. + *
  6048. + *
  6049. + **************************************************************************
  6050. + * May 2004 rkt, neb
  6051. + *
  6052. + * Initial Release
  6053. + *
  6054. + *
  6055. + *
  6056. + **************************************************************************
  6057. + */
  6058. +
  6059. +#ifndef __IDT_DMA_H__
  6060. +#define __IDT_DMA_H__
  6061. +
  6062. +enum
  6063. +{
  6064. + DMA0_PhysicalAddress = 0x18040000,
  6065. + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
  6066. +
  6067. + DMA0_VirtualAddress = 0xb8040000,
  6068. + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
  6069. +} ;
  6070. +
  6071. +/*
  6072. + * DMA descriptor (in physical memory).
  6073. + */
  6074. +
  6075. +typedef struct DMAD_s
  6076. +{
  6077. + u32 control ; // Control. use DMAD_*
  6078. + u32 ca ; // Current Address.
  6079. + u32 devcs ; // Device control and status.
  6080. + u32 link ; // Next descriptor in chain.
  6081. +} volatile *DMAD_t ;
  6082. +
  6083. +enum
  6084. +{
  6085. + DMAD_size = sizeof (struct DMAD_s),
  6086. + DMAD_count_b = 0, // in DMAD_t -> control
  6087. + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
  6088. + DMAD_ds_b = 20, // in DMAD_t -> control
  6089. + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
  6090. + DMAD_ds_ethRcv0_v = 0,
  6091. + DMAD_ds_ethXmt0_v = 0,
  6092. + DMAD_ds_memToFifo_v = 0,
  6093. + DMAD_ds_fifoToMem_v = 0,
  6094. + DMAD_ds_pciToMem_v = 0,
  6095. + DMAD_ds_memToPci_v = 0,
  6096. +
  6097. + DMAD_devcmd_b = 22, // in DMAD_t -> control
  6098. + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
  6099. + DMAD_devcmd_byte_v = 0, //memory-to-memory
  6100. + DMAD_devcmd_halfword_v = 1, //memory-to-memory
  6101. + DMAD_devcmd_word_v = 2, //memory-to-memory
  6102. + DMAD_devcmd_2words_v = 3, //memory-to-memory
  6103. + DMAD_devcmd_4words_v = 4, //memory-to-memory
  6104. + DMAD_devcmd_6words_v = 5, //memory-to-memory
  6105. + DMAD_devcmd_8words_v = 6, //memory-to-memory
  6106. + DMAD_devcmd_16words_v = 7, //memory-to-memory
  6107. + DMAD_cof_b = 25, // chain on finished
  6108. + DMAD_cof_m = 0x02000000, //
  6109. + DMAD_cod_b = 26, // chain on done
  6110. + DMAD_cod_m = 0x04000000, //
  6111. + DMAD_iof_b = 27, // interrupt on finished
  6112. + DMAD_iof_m = 0x08000000, //
  6113. + DMAD_iod_b = 28, // interrupt on done
  6114. + DMAD_iod_m = 0x10000000, //
  6115. + DMAD_t_b = 29, // terminated
  6116. + DMAD_t_m = 0x20000000, //
  6117. + DMAD_d_b = 30, // done
  6118. + DMAD_d_m = 0x40000000, //
  6119. + DMAD_f_b = 31, // finished
  6120. + DMAD_f_m = 0x80000000, //
  6121. +} ;
  6122. +
  6123. +/*
  6124. + * DMA register (within Internal Register Map).
  6125. + */
  6126. +
  6127. +struct DMA_Chan_s
  6128. +{
  6129. + u32 dmac ; // Control.
  6130. + u32 dmas ; // Status.
  6131. + u32 dmasm ; // Mask.
  6132. + u32 dmadptr ; // Descriptor pointer.
  6133. + u32 dmandptr ; // Next descriptor pointer.
  6134. +};
  6135. +
  6136. +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
  6137. +
  6138. +//DMA_Channels use DMACH_count instead
  6139. +
  6140. +enum
  6141. +{
  6142. + DMAC_run_b = 0, //
  6143. + DMAC_run_m = 0x00000001, //
  6144. + DMAC_dm_b = 1, // done mask
  6145. + DMAC_dm_m = 0x00000002, //
  6146. + DMAC_mode_b = 2, //
  6147. + DMAC_mode_m = 0x0000000c, //
  6148. + DMAC_mode_auto_v = 0,
  6149. + DMAC_mode_burst_v = 1,
  6150. + DMAC_mode_transfer_v = 2, //usually used
  6151. + DMAC_mode_reserved_v = 3,
  6152. + DMAC_a_b = 4, //
  6153. + DMAC_a_m = 0x00000010, //
  6154. +
  6155. + DMAS_f_b = 0, // finished (sticky)
  6156. + DMAS_f_m = 0x00000001, //
  6157. + DMAS_d_b = 1, // done (sticky)
  6158. + DMAS_d_m = 0x00000002, //
  6159. + DMAS_c_b = 2, // chain (sticky)
  6160. + DMAS_c_m = 0x00000004, //
  6161. + DMAS_e_b = 3, // error (sticky)
  6162. + DMAS_e_m = 0x00000008, //
  6163. + DMAS_h_b = 4, // halt (sticky)
  6164. + DMAS_h_m = 0x00000010, //
  6165. +
  6166. + DMASM_f_b = 0, // finished (1=mask)
  6167. + DMASM_f_m = 0x00000001, //
  6168. + DMASM_d_b = 1, // done (1=mask)
  6169. + DMASM_d_m = 0x00000002, //
  6170. + DMASM_c_b = 2, // chain (1=mask)
  6171. + DMASM_c_m = 0x00000004, //
  6172. + DMASM_e_b = 3, // error (1=mask)
  6173. + DMASM_e_m = 0x00000008, //
  6174. + DMASM_h_b = 4, // halt (1=mask)
  6175. + DMASM_h_m = 0x00000010, //
  6176. +} ;
  6177. +
  6178. +/*
  6179. + * DMA channel definitions
  6180. + */
  6181. +
  6182. +enum
  6183. +{
  6184. + DMACH_ethRcv0 = 0,
  6185. + DMACH_ethXmt0 = 1,
  6186. + DMACH_memToFifo = 2,
  6187. + DMACH_fifoToMem = 3,
  6188. + DMACH_pciToMem = 4,
  6189. + DMACH_memToPci = 5,
  6190. +
  6191. + DMACH_count //must be last
  6192. +};
  6193. +
  6194. +
  6195. +typedef struct DMAC_s
  6196. +{
  6197. + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
  6198. +} volatile *DMA_t ;
  6199. +
  6200. +
  6201. +/*
  6202. + * External DMA parameters
  6203. +*/
  6204. +
  6205. +enum
  6206. +{
  6207. + DMADEVCMD_ts_b = 0, // ts field in devcmd
  6208. + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
  6209. + DMADEVCMD_ts_byte_v = 0,
  6210. + DMADEVCMD_ts_halfword_v = 1,
  6211. + DMADEVCMD_ts_word_v = 2,
  6212. + DMADEVCMD_ts_2word_v = 3,
  6213. + DMADEVCMD_ts_4word_v = 4,
  6214. + DMADEVCMD_ts_6word_v = 5,
  6215. + DMADEVCMD_ts_8word_v = 6,
  6216. + DMADEVCMD_ts_16word_v = 7
  6217. +};
  6218. +
  6219. +
  6220. +#endif // __IDT_DMA_H__
  6221. +
  6222. +
  6223. +
  6224. +
  6225. +
  6226. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
  6227. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 1969-12-31 19:00:00.000000000 -0500
  6228. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 2007-09-20 00:16:52.000000000 -0400
  6229. @@ -0,0 +1,89 @@
  6230. +/**************************************************************************
  6231. + *
  6232. + * BRIEF MODULE DESCRIPTION
  6233. + * Definitions for DMA controller.
  6234. + *
  6235. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  6236. + *
  6237. + * This program is free software; you can redistribute it and/or modify it
  6238. + * under the terms of the GNU General Public License as published by the
  6239. + * Free Software Foundation; either version 2 of the License, or (at your
  6240. + * option) any later version.
  6241. + *
  6242. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  6243. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  6244. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  6245. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  6246. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  6247. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  6248. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  6249. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  6250. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  6251. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  6252. + *
  6253. + * You should have received a copy of the GNU General Public License along
  6254. + * with this program; if not, write to the Free Software Foundation, Inc.,
  6255. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  6256. + *
  6257. + *
  6258. + **************************************************************************
  6259. + * May 2004 rkt, neb.
  6260. + *
  6261. + * Initial Release
  6262. + *
  6263. + *
  6264. + *
  6265. + **************************************************************************
  6266. + */
  6267. +
  6268. +#ifndef __IDT_DMA_V_H__
  6269. +#define __IDT_DMA_V_H__
  6270. +
  6271. +#include <asm/idt-boards/rc32434/rc32434_dma.h>
  6272. +#include <asm/idt-boards/rc32434/rc32434.h>
  6273. +
  6274. +#define DMA_CHAN_OFFSET 0x14
  6275. +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
  6276. +#define DMA_COUNT(count) \
  6277. + ((count) & DMAD_count_m)
  6278. +
  6279. +#define DMA_HALT_TIMEOUT 500
  6280. +
  6281. +
  6282. +static inline int rc32434_halt_dma(DMA_Chan_t ch)
  6283. +{
  6284. + int timeout=1;
  6285. + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
  6286. + rc32434_writel(0, &ch->dmac);
  6287. +
  6288. + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
  6289. + if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
  6290. + rc32434_writel(0, &ch->dmas);
  6291. + break;
  6292. + }
  6293. + }
  6294. +
  6295. + }
  6296. +
  6297. + return timeout ? 0 : 1;
  6298. +}
  6299. +
  6300. +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
  6301. +{
  6302. + rc32434_writel(0, &ch->dmandptr);
  6303. + rc32434_writel(dma_addr, &ch->dmadptr);
  6304. +}
  6305. +
  6306. +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
  6307. +{
  6308. + rc32434_writel(dma_addr, &ch->dmandptr);
  6309. +}
  6310. +
  6311. +#endif // __IDT_DMA_V_H__
  6312. +
  6313. +
  6314. +
  6315. +
  6316. +
  6317. +
  6318. +
  6319. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
  6320. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 1969-12-31 19:00:00.000000000 -0500
  6321. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2007-09-20 00:16:52.000000000 -0400
  6322. @@ -0,0 +1,333 @@
  6323. +/**************************************************************************
  6324. + *
  6325. + * BRIEF MODULE DESCRIPTION
  6326. + * Ethernet register definition
  6327. + *
  6328. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  6329. + *
  6330. + * This program is free software; you can redistribute it and/or modify it
  6331. + * under the terms of the GNU General Public License as published by the
  6332. + * Free Software Foundation; either version 2 of the License, or (at your
  6333. + * option) any later version.
  6334. + *
  6335. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  6336. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  6337. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  6338. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  6339. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  6340. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  6341. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  6342. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  6343. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  6344. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  6345. + *
  6346. + * You should have received a copy of the GNU General Public License along
  6347. + * with this program; if not, write to the Free Software Foundation, Inc.,
  6348. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  6349. + *
  6350. + *
  6351. + **************************************************************************
  6352. + * May 2004 rkt, neb.
  6353. + *
  6354. + * Initial Release
  6355. + *
  6356. + *
  6357. + *
  6358. + **************************************************************************
  6359. + */
  6360. +
  6361. +#ifndef __IDT_ETH_H__
  6362. +#define __IDT_ETH_H__
  6363. +
  6364. +
  6365. +enum
  6366. +{
  6367. + ETH0_PhysicalAddress = 0x18060000,
  6368. + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
  6369. +
  6370. + ETH0_VirtualAddress = 0xb8060000,
  6371. + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
  6372. +} ;
  6373. +
  6374. +typedef struct
  6375. +{
  6376. + u32 ethintfc ;
  6377. + u32 ethfifott ;
  6378. + u32 etharc ;
  6379. + u32 ethhash0 ;
  6380. + u32 ethhash1 ;
  6381. + u32 ethu0 [4] ; // Reserved.
  6382. + u32 ethpfs ;
  6383. + u32 ethmcp ;
  6384. + u32 eth_u1 [10] ; // Reserved.
  6385. + u32 ethspare ;
  6386. + u32 eth_u2 [42] ; // Reserved.
  6387. + u32 ethsal0 ;
  6388. + u32 ethsah0 ;
  6389. + u32 ethsal1 ;
  6390. + u32 ethsah1 ;
  6391. + u32 ethsal2 ;
  6392. + u32 ethsah2 ;
  6393. + u32 ethsal3 ;
  6394. + u32 ethsah3 ;
  6395. + u32 ethrbc ;
  6396. + u32 ethrpc ;
  6397. + u32 ethrupc ;
  6398. + u32 ethrfc ;
  6399. + u32 ethtbc ;
  6400. + u32 ethgpf ;
  6401. + u32 eth_u9 [50] ; // Reserved.
  6402. + u32 ethmac1 ;
  6403. + u32 ethmac2 ;
  6404. + u32 ethipgt ;
  6405. + u32 ethipgr ;
  6406. + u32 ethclrt ;
  6407. + u32 ethmaxf ;
  6408. + u32 eth_u10 ; // Reserved.
  6409. + u32 ethmtest ;
  6410. + u32 miimcfg ;
  6411. + u32 miimcmd ;
  6412. + u32 miimaddr ;
  6413. + u32 miimwtd ;
  6414. + u32 miimrdd ;
  6415. + u32 miimind ;
  6416. + u32 eth_u11 ; // Reserved.
  6417. + u32 eth_u12 ; // Reserved.
  6418. + u32 ethcfsa0 ;
  6419. + u32 ethcfsa1 ;
  6420. + u32 ethcfsa2 ;
  6421. +} volatile *ETH_t;
  6422. +
  6423. +enum
  6424. +{
  6425. + ETHINTFC_en_b = 0,
  6426. + ETHINTFC_en_m = 0x00000001,
  6427. + ETHINTFC_its_b = 1,
  6428. + ETHINTFC_its_m = 0x00000002,
  6429. + ETHINTFC_rip_b = 2,
  6430. + ETHINTFC_rip_m = 0x00000004,
  6431. + ETHINTFC_jam_b = 3,
  6432. + ETHINTFC_jam_m = 0x00000008,
  6433. + ETHINTFC_ovr_b = 4,
  6434. + ETHINTFC_ovr_m = 0x00000010,
  6435. + ETHINTFC_und_b = 5,
  6436. + ETHINTFC_und_m = 0x00000020,
  6437. +
  6438. + ETHFIFOTT_tth_b = 0,
  6439. + ETHFIFOTT_tth_m = 0x0000007f,
  6440. +
  6441. + ETHARC_pro_b = 0,
  6442. + ETHARC_pro_m = 0x00000001,
  6443. + ETHARC_am_b = 1,
  6444. + ETHARC_am_m = 0x00000002,
  6445. + ETHARC_afm_b = 2,
  6446. + ETHARC_afm_m = 0x00000004,
  6447. + ETHARC_ab_b = 3,
  6448. + ETHARC_ab_m = 0x00000008,
  6449. +
  6450. + ETHSAL_byte5_b = 0,
  6451. + ETHSAL_byte5_m = 0x000000ff,
  6452. + ETHSAL_byte4_b = 8,
  6453. + ETHSAL_byte4_m = 0x0000ff00,
  6454. + ETHSAL_byte3_b = 16,
  6455. + ETHSAL_byte3_m = 0x00ff0000,
  6456. + ETHSAL_byte2_b = 24,
  6457. + ETHSAL_byte2_m = 0xff000000,
  6458. +
  6459. + ETHSAH_byte1_b = 0,
  6460. + ETHSAH_byte1_m = 0x000000ff,
  6461. + ETHSAH_byte0_b = 8,
  6462. + ETHSAH_byte0_m = 0x0000ff00,
  6463. +
  6464. + ETHGPF_ptv_b = 0,
  6465. + ETHGPF_ptv_m = 0x0000ffff,
  6466. +
  6467. + ETHPFS_pfd_b = 0,
  6468. + ETHPFS_pfd_m = 0x00000001,
  6469. +
  6470. + ETHCFSA0_cfsa4_b = 0,
  6471. + ETHCFSA0_cfsa4_m = 0x000000ff,
  6472. + ETHCFSA0_cfsa5_b = 8,
  6473. + ETHCFSA0_cfsa5_m = 0x0000ff00,
  6474. +
  6475. + ETHCFSA1_cfsa2_b = 0,
  6476. + ETHCFSA1_cfsa2_m = 0x000000ff,
  6477. + ETHCFSA1_cfsa3_b = 8,
  6478. + ETHCFSA1_cfsa3_m = 0x0000ff00,
  6479. +
  6480. + ETHCFSA2_cfsa0_b = 0,
  6481. + ETHCFSA2_cfsa0_m = 0x000000ff,
  6482. + ETHCFSA2_cfsa1_b = 8,
  6483. + ETHCFSA2_cfsa1_m = 0x0000ff00,
  6484. +
  6485. + ETHMAC1_re_b = 0,
  6486. + ETHMAC1_re_m = 0x00000001,
  6487. + ETHMAC1_paf_b = 1,
  6488. + ETHMAC1_paf_m = 0x00000002,
  6489. + ETHMAC1_rfc_b = 2,
  6490. + ETHMAC1_rfc_m = 0x00000004,
  6491. + ETHMAC1_tfc_b = 3,
  6492. + ETHMAC1_tfc_m = 0x00000008,
  6493. + ETHMAC1_lb_b = 4,
  6494. + ETHMAC1_lb_m = 0x00000010,
  6495. + ETHMAC1_mr_b = 31,
  6496. + ETHMAC1_mr_m = 0x80000000,
  6497. +
  6498. + ETHMAC2_fd_b = 0,
  6499. + ETHMAC2_fd_m = 0x00000001,
  6500. + ETHMAC2_flc_b = 1,
  6501. + ETHMAC2_flc_m = 0x00000002,
  6502. + ETHMAC2_hfe_b = 2,
  6503. + ETHMAC2_hfe_m = 0x00000004,
  6504. + ETHMAC2_dc_b = 3,
  6505. + ETHMAC2_dc_m = 0x00000008,
  6506. + ETHMAC2_cen_b = 4,
  6507. + ETHMAC2_cen_m = 0x00000010,
  6508. + ETHMAC2_pe_b = 5,
  6509. + ETHMAC2_pe_m = 0x00000020,
  6510. + ETHMAC2_vpe_b = 6,
  6511. + ETHMAC2_vpe_m = 0x00000040,
  6512. + ETHMAC2_ape_b = 7,
  6513. + ETHMAC2_ape_m = 0x00000080,
  6514. + ETHMAC2_ppe_b = 8,
  6515. + ETHMAC2_ppe_m = 0x00000100,
  6516. + ETHMAC2_lpe_b = 9,
  6517. + ETHMAC2_lpe_m = 0x00000200,
  6518. + ETHMAC2_nb_b = 12,
  6519. + ETHMAC2_nb_m = 0x00001000,
  6520. + ETHMAC2_bp_b = 13,
  6521. + ETHMAC2_bp_m = 0x00002000,
  6522. + ETHMAC2_ed_b = 14,
  6523. + ETHMAC2_ed_m = 0x00004000,
  6524. +
  6525. + ETHIPGT_ipgt_b = 0,
  6526. + ETHIPGT_ipgt_m = 0x0000007f,
  6527. +
  6528. + ETHIPGR_ipgr2_b = 0,
  6529. + ETHIPGR_ipgr2_m = 0x0000007f,
  6530. + ETHIPGR_ipgr1_b = 8,
  6531. + ETHIPGR_ipgr1_m = 0x00007f00,
  6532. +
  6533. + ETHCLRT_maxret_b = 0,
  6534. + ETHCLRT_maxret_m = 0x0000000f,
  6535. + ETHCLRT_colwin_b = 8,
  6536. + ETHCLRT_colwin_m = 0x00003f00,
  6537. +
  6538. + ETHMAXF_maxf_b = 0,
  6539. + ETHMAXF_maxf_m = 0x0000ffff,
  6540. +
  6541. + ETHMTEST_tb_b = 2,
  6542. + ETHMTEST_tb_m = 0x00000004,
  6543. +
  6544. + ETHMCP_div_b = 0,
  6545. + ETHMCP_div_m = 0x000000ff,
  6546. +
  6547. + MIIMCFG_rsv_b = 0,
  6548. + MIIMCFG_rsv_m = 0x0000000c,
  6549. +
  6550. + MIIMCMD_rd_b = 0,
  6551. + MIIMCMD_rd_m = 0x00000001,
  6552. + MIIMCMD_scn_b = 1,
  6553. + MIIMCMD_scn_m = 0x00000002,
  6554. +
  6555. + MIIMADDR_regaddr_b = 0,
  6556. + MIIMADDR_regaddr_m = 0x0000001f,
  6557. + MIIMADDR_phyaddr_b = 8,
  6558. + MIIMADDR_phyaddr_m = 0x00001f00,
  6559. +
  6560. + MIIMWTD_wdata_b = 0,
  6561. + MIIMWTD_wdata_m = 0x0000ffff,
  6562. +
  6563. + MIIMRDD_rdata_b = 0,
  6564. + MIIMRDD_rdata_m = 0x0000ffff,
  6565. +
  6566. + MIIMIND_bsy_b = 0,
  6567. + MIIMIND_bsy_m = 0x00000001,
  6568. + MIIMIND_scn_b = 1,
  6569. + MIIMIND_scn_m = 0x00000002,
  6570. + MIIMIND_nv_b = 2,
  6571. + MIIMIND_nv_m = 0x00000004,
  6572. +
  6573. +} ;
  6574. +
  6575. +/*
  6576. + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
  6577. + */
  6578. +enum
  6579. +{
  6580. + ETHRX_fd_b = 0,
  6581. + ETHRX_fd_m = 0x00000001,
  6582. + ETHRX_ld_b = 1,
  6583. + ETHRX_ld_m = 0x00000002,
  6584. + ETHRX_rok_b = 2,
  6585. + ETHRX_rok_m = 0x00000004,
  6586. + ETHRX_fm_b = 3,
  6587. + ETHRX_fm_m = 0x00000008,
  6588. + ETHRX_mp_b = 4,
  6589. + ETHRX_mp_m = 0x00000010,
  6590. + ETHRX_bp_b = 5,
  6591. + ETHRX_bp_m = 0x00000020,
  6592. + ETHRX_vlt_b = 6,
  6593. + ETHRX_vlt_m = 0x00000040,
  6594. + ETHRX_cf_b = 7,
  6595. + ETHRX_cf_m = 0x00000080,
  6596. + ETHRX_ovr_b = 8,
  6597. + ETHRX_ovr_m = 0x00000100,
  6598. + ETHRX_crc_b = 9,
  6599. + ETHRX_crc_m = 0x00000200,
  6600. + ETHRX_cv_b = 10,
  6601. + ETHRX_cv_m = 0x00000400,
  6602. + ETHRX_db_b = 11,
  6603. + ETHRX_db_m = 0x00000800,
  6604. + ETHRX_le_b = 12,
  6605. + ETHRX_le_m = 0x00001000,
  6606. + ETHRX_lor_b = 13,
  6607. + ETHRX_lor_m = 0x00002000,
  6608. + ETHRX_ces_b = 14,
  6609. + ETHRX_ces_m = 0x00004000,
  6610. + ETHRX_length_b = 16,
  6611. + ETHRX_length_m = 0xffff0000,
  6612. +
  6613. + ETHTX_fd_b = 0,
  6614. + ETHTX_fd_m = 0x00000001,
  6615. + ETHTX_ld_b = 1,
  6616. + ETHTX_ld_m = 0x00000002,
  6617. + ETHTX_oen_b = 2,
  6618. + ETHTX_oen_m = 0x00000004,
  6619. + ETHTX_pen_b = 3,
  6620. + ETHTX_pen_m = 0x00000008,
  6621. + ETHTX_cen_b = 4,
  6622. + ETHTX_cen_m = 0x00000010,
  6623. + ETHTX_hen_b = 5,
  6624. + ETHTX_hen_m = 0x00000020,
  6625. + ETHTX_tok_b = 6,
  6626. + ETHTX_tok_m = 0x00000040,
  6627. + ETHTX_mp_b = 7,
  6628. + ETHTX_mp_m = 0x00000080,
  6629. + ETHTX_bp_b = 8,
  6630. + ETHTX_bp_m = 0x00000100,
  6631. + ETHTX_und_b = 9,
  6632. + ETHTX_und_m = 0x00000200,
  6633. + ETHTX_of_b = 10,
  6634. + ETHTX_of_m = 0x00000400,
  6635. + ETHTX_ed_b = 11,
  6636. + ETHTX_ed_m = 0x00000800,
  6637. + ETHTX_ec_b = 12,
  6638. + ETHTX_ec_m = 0x00001000,
  6639. + ETHTX_lc_b = 13,
  6640. + ETHTX_lc_m = 0x00002000,
  6641. + ETHTX_td_b = 14,
  6642. + ETHTX_td_m = 0x00004000,
  6643. + ETHTX_crc_b = 15,
  6644. + ETHTX_crc_m = 0x00008000,
  6645. + ETHTX_le_b = 16,
  6646. + ETHTX_le_m = 0x00010000,
  6647. + ETHTX_cc_b = 17,
  6648. + ETHTX_cc_m = 0x001E0000,
  6649. +} ;
  6650. +
  6651. +#endif // __IDT_ETH_H__
  6652. +
  6653. +
  6654. +
  6655. +
  6656. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
  6657. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 1969-12-31 19:00:00.000000000 -0500
  6658. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 2007-09-20 00:16:52.000000000 -0400
  6659. @@ -0,0 +1,77 @@
  6660. +/**************************************************************************
  6661. + *
  6662. + * BRIEF MODULE DESCRIPTION
  6663. + * Ethernet register definition
  6664. + *
  6665. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  6666. + *
  6667. + * This program is free software; you can redistribute it and/or modify it
  6668. + * under the terms of the GNU General Public License as published by the
  6669. + * Free Software Foundation; either version 2 of the License, or (at your
  6670. + * option) any later version.
  6671. + *
  6672. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  6673. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  6674. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  6675. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  6676. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  6677. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  6678. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  6679. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  6680. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  6681. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  6682. + *
  6683. + * You should have received a copy of the GNU General Public License along
  6684. + * with this program; if not, write to the Free Software Foundation, Inc.,
  6685. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  6686. + *
  6687. + *
  6688. + **************************************************************************
  6689. + * May 2004 rkt, neb.
  6690. + *
  6691. + * Initial Release
  6692. + *
  6693. + *
  6694. + *
  6695. + **************************************************************************
  6696. + */
  6697. +
  6698. +#ifndef __IDT_ETH_V_H__
  6699. +#define __IDT_ETH_V_H__
  6700. +
  6701. +#include <asm/idt-boards/rc32434/rc32434_eth.h>
  6702. +
  6703. +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
  6704. +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
  6705. +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
  6706. +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
  6707. +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
  6708. +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
  6709. +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
  6710. +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
  6711. +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
  6712. +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
  6713. +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
  6714. +
  6715. +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
  6716. +
  6717. +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
  6718. +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
  6719. +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
  6720. +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
  6721. +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
  6722. +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
  6723. +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
  6724. +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
  6725. +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
  6726. +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
  6727. +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
  6728. +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
  6729. +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
  6730. +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
  6731. +#endif // __IDT_ETH_V_H__
  6732. +
  6733. +
  6734. +
  6735. +
  6736. +
  6737. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
  6738. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 1969-12-31 19:00:00.000000000 -0500
  6739. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 2007-09-20 00:16:52.000000000 -0400
  6740. @@ -0,0 +1,167 @@
  6741. +/**************************************************************************
  6742. + *
  6743. + * BRIEF MODULE DESCRIPTION
  6744. + * GPIO register definition
  6745. + *
  6746. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  6747. + *
  6748. + * This program is free software; you can redistribute it and/or modify it
  6749. + * under the terms of the GNU General Public License as published by the
  6750. + * Free Software Foundation; either version 2 of the License, or (at your
  6751. + * option) any later version.
  6752. + *
  6753. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  6754. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  6755. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  6756. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  6757. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  6758. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  6759. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  6760. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  6761. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  6762. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  6763. + *
  6764. + * You should have received a copy of the GNU General Public License along
  6765. + * with this program; if not, write to the Free Software Foundation, Inc.,
  6766. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  6767. + *
  6768. + *
  6769. + **************************************************************************
  6770. + * May 2004 rkt, neb.
  6771. + *
  6772. + * Initial Release
  6773. + *
  6774. + *
  6775. + *
  6776. + **************************************************************************
  6777. + */
  6778. +
  6779. +#ifndef __IDT_GPIO_H__
  6780. +#define __IDT_GPIO_H__
  6781. +
  6782. +enum
  6783. +{
  6784. + GPIO0_PhysicalAddress = 0x18050000,
  6785. + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
  6786. +
  6787. + GPIO0_VirtualAddress = 0xb8050000,
  6788. + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
  6789. +} ;
  6790. +
  6791. +typedef struct
  6792. +{
  6793. + u32 gpiofunc; /* GPIO Function Register
  6794. + * gpiofunc[x]==0 bit = gpio
  6795. + * func[x]==1 bit = altfunc
  6796. + */
  6797. + u32 gpiocfg; /* GPIO Configuration Register
  6798. + * gpiocfg[x]==0 bit = input
  6799. + * gpiocfg[x]==1 bit = output
  6800. + */
  6801. + u32 gpiod; /* GPIO Data Register
  6802. + * gpiod[x] read/write gpio pinX status
  6803. + */
  6804. + u32 gpioilevel; /* GPIO Interrupt Status Register
  6805. + * interrupt level (see gpioistat)
  6806. + */
  6807. + u32 gpioistat; /* Gpio Interrupt Status Register
  6808. + * istat[x] = (gpiod[x] == level[x])
  6809. + * cleared in ISR (STICKY bits)
  6810. + */
  6811. + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
  6812. +} volatile * GPIO_t ;
  6813. +
  6814. +typedef enum
  6815. +{
  6816. + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
  6817. + GPIO_alt_v = 1, // gpiofunc use pin as alt.
  6818. + GPIO_input_v = 0, // gpiocfg use pin as input.
  6819. + GPIO_output_v = 1, // gpiocfg use pin as output.
  6820. + GPIO_pin0_b = 0,
  6821. + GPIO_pin0_m = 0x00000001,
  6822. + GPIO_pin1_b = 1,
  6823. + GPIO_pin1_m = 0x00000002,
  6824. + GPIO_pin2_b = 2,
  6825. + GPIO_pin2_m = 0x00000004,
  6826. + GPIO_pin3_b = 3,
  6827. + GPIO_pin3_m = 0x00000008,
  6828. + GPIO_pin4_b = 4,
  6829. + GPIO_pin4_m = 0x00000010,
  6830. + GPIO_pin5_b = 5,
  6831. + GPIO_pin5_m = 0x00000020,
  6832. + GPIO_pin6_b = 6,
  6833. + GPIO_pin6_m = 0x00000040,
  6834. + GPIO_pin7_b = 7,
  6835. + GPIO_pin7_m = 0x00000080,
  6836. + GPIO_pin8_b = 8,
  6837. + GPIO_pin8_m = 0x00000100,
  6838. + GPIO_pin9_b = 9,
  6839. + GPIO_pin9_m = 0x00000200,
  6840. + GPIO_pin10_b = 10,
  6841. + GPIO_pin10_m = 0x00000400,
  6842. + GPIO_pin11_b = 11,
  6843. + GPIO_pin11_m = 0x00000800,
  6844. + GPIO_pin12_b = 12,
  6845. + GPIO_pin12_m = 0x00001000,
  6846. + GPIO_pin13_b = 13,
  6847. + GPIO_pin13_m = 0x00002000,
  6848. +
  6849. +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
  6850. +
  6851. + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
  6852. + GPIO_u0sout_m = GPIO_pin0_m,
  6853. + GPIO_u0sout_cfg_v = GPIO_output_v,
  6854. + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
  6855. + GPIO_u0sinp_m = GPIO_pin1_m,
  6856. + GPIO_u0sinp_cfg_v = GPIO_input_v,
  6857. + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
  6858. + GPIO_u0rtsn_m = GPIO_pin2_m,
  6859. + GPIO_u0rtsn_cfg_v = GPIO_output_v,
  6860. + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
  6861. + GPIO_u0ctsn_m = GPIO_pin3_m,
  6862. + GPIO_u0ctsn_cfg_v = GPIO_input_v,
  6863. +
  6864. + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
  6865. + GPIO_maddr22_m = GPIO_pin4_m,
  6866. + GPIO_maddr22_cfg_v = GPIO_output_v,
  6867. +
  6868. + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
  6869. + GPIO_maddr23_m = GPIO_pin5_m,
  6870. + GPIO_maddr23_cfg_v = GPIO_output_v,
  6871. +
  6872. + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
  6873. + GPIO_maddr24_m = GPIO_pin6_m,
  6874. + GPIO_maddr24_cfg_v = GPIO_output_v,
  6875. +
  6876. + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
  6877. + GPIO_maddr25_m = GPIO_pin7_m,
  6878. + GPIO_maddr25_cfg_v = GPIO_output_v,
  6879. +
  6880. + GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
  6881. + GPIO_cpudmadebug_m = GPIO_pin8_m,
  6882. + GPIO_cpudmadebug_cfg_v = GPIO_output_v,
  6883. +
  6884. + GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
  6885. + GPIO_pcireq4_m = GPIO_pin9_m,
  6886. + GPIO_pcireq4_cfg_v = GPIO_input_v,
  6887. +
  6888. + GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
  6889. + GPIO_pcigrant4_m = GPIO_pin10_m,
  6890. + GPIO_pcigrant4_cfg_v = GPIO_output_v,
  6891. +
  6892. + GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
  6893. + GPIO_pcireq5_m = GPIO_pin11_m,
  6894. + GPIO_pcireq5_cfg_v = GPIO_input_v,
  6895. +
  6896. + GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
  6897. + GPIO_pcigrant5_m = GPIO_pin12_m,
  6898. + GPIO_pcigrant5_cfg_v = GPIO_output_v,
  6899. +
  6900. + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
  6901. + GPIO_pcimuintn_m = GPIO_pin13_m,
  6902. + GPIO_pcimuintn_cfg_v = GPIO_output_v,
  6903. +
  6904. +} GPIO_DEFS_t;
  6905. +
  6906. +#endif // __IDT_GPIO_H__
  6907. +
  6908. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_int.h
  6909. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_int.h 1969-12-31 19:00:00.000000000 -0500
  6910. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2007-09-20 00:16:52.000000000 -0400
  6911. @@ -0,0 +1,174 @@
  6912. +/**************************************************************************
  6913. + *
  6914. + * BRIEF MODULE DESCRIPTION
  6915. + * Interrupt Controller register definition.
  6916. + *
  6917. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  6918. + *
  6919. + * This program is free software; you can redistribute it and/or modify it
  6920. + * under the terms of the GNU General Public License as published by the
  6921. + * Free Software Foundation; either version 2 of the License, or (at your
  6922. + * option) any later version.
  6923. + *
  6924. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  6925. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  6926. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  6927. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  6928. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  6929. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  6930. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  6931. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  6932. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  6933. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  6934. + *
  6935. + * You should have received a copy of the GNU General Public License along
  6936. + * with this program; if not, write to the Free Software Foundation, Inc.,
  6937. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  6938. + *
  6939. + *
  6940. + **************************************************************************
  6941. + * May 2004 rkt, neb.
  6942. + *
  6943. + * Initial Release
  6944. + *
  6945. + *
  6946. + *
  6947. + **************************************************************************
  6948. + */
  6949. +
  6950. +#ifndef __IDT_INT_H__
  6951. +#define __IDT_INT_H__
  6952. +
  6953. +enum
  6954. +{
  6955. + INT0_PhysicalAddress = 0x18038000,
  6956. + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
  6957. +
  6958. + INT0_VirtualAddress = 0xB8038000,
  6959. + INT_VirtualAddress = INT0_VirtualAddress, // Default
  6960. +} ;
  6961. +
  6962. +struct INT_s
  6963. +{
  6964. + u32 ipend ; //Pending interrupts. use INT?_
  6965. + u32 itest ; //Test bits. use INT?_
  6966. + u32 imask ; //Interrupt disabled when set. use INT?_
  6967. +} ;
  6968. +
  6969. +enum
  6970. +{
  6971. + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
  6972. + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
  6973. + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
  6974. + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
  6975. + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
  6976. +
  6977. + IPEND_count, // must be last (used in loops)
  6978. + IPEND_min = IPEND2 // min IPEND (used in loops)
  6979. +};
  6980. +
  6981. +typedef struct INTC_s
  6982. +{
  6983. + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
  6984. + u32 nmips ; // use NMIPS_
  6985. +} volatile *INT_t ;
  6986. +
  6987. +enum
  6988. +{
  6989. + INT2_timer0_b = 0,
  6990. + INT2_timer0_m = 0x00000001,
  6991. + INT2_timer1_b = 1,
  6992. + INT2_timer1_m = 0x00000002,
  6993. + INT2_timer2_b = 2,
  6994. + INT2_timer2_m = 0x00000004,
  6995. + INT2_refresh_b = 3,
  6996. + INT2_refresh_m = 0x00000008,
  6997. + INT2_watchdogTimeout_b = 4,
  6998. + INT2_watchdogTimeout_m = 0x00000010,
  6999. + INT2_undecodedCpuWrite_b = 5,
  7000. + INT2_undecodedCpuWrite_m = 0x00000020,
  7001. + INT2_undecodedCpuRead_b = 6,
  7002. + INT2_undecodedCpuRead_m = 0x00000040,
  7003. + INT2_undecodedPciWrite_b = 7,
  7004. + INT2_undecodedPciWrite_m = 0x00000080,
  7005. + INT2_undecodedPciRead_b = 8,
  7006. + INT2_undecodedPciRead_m = 0x00000100,
  7007. + INT2_undecodedDmaWrite_b = 9,
  7008. + INT2_undecodedDmaWrite_m = 0x00000200,
  7009. + INT2_undecodedDmaRead_b = 10,
  7010. + INT2_undecodedDmaRead_m = 0x00000400,
  7011. + INT2_ipBusSlaveAckError_b = 11,
  7012. + INT2_ipBusSlaveAckError_m = 0x00000800,
  7013. +
  7014. + INT3_dmaChannel0_b = 0,
  7015. + INT3_dmaChannel0_m = 0x00000001,
  7016. + INT3_dmaChannel1_b = 1,
  7017. + INT3_dmaChannel1_m = 0x00000002,
  7018. + INT3_dmaChannel2_b = 2,
  7019. + INT3_dmaChannel2_m = 0x00000004,
  7020. + INT3_dmaChannel3_b = 3,
  7021. + INT3_dmaChannel3_m = 0x00000008,
  7022. + INT3_dmaChannel4_b = 4,
  7023. + INT3_dmaChannel4_m = 0x00000010,
  7024. + INT3_dmaChannel5_b = 5,
  7025. + INT3_dmaChannel5_m = 0x00000020,
  7026. +
  7027. + INT5_uartGeneral0_b = 0,
  7028. + INT5_uartGeneral0_m = 0x00000001,
  7029. + INT5_uartTxrdy0_b = 1,
  7030. + INT5_uartTxrdy0_m = 0x00000002,
  7031. + INT5_uartRxrdy0_b = 2,
  7032. + INT5_uartRxrdy0_m = 0x00000004,
  7033. + INT5_pci_b = 3,
  7034. + INT5_pci_m = 0x00000008,
  7035. + INT5_pciDecoupled_b = 4,
  7036. + INT5_pciDecoupled_m = 0x00000010,
  7037. + INT5_spi_b = 5,
  7038. + INT5_spi_m = 0x00000020,
  7039. + INT5_deviceDecoupled_b = 6,
  7040. + INT5_deviceDecoupled_m = 0x00000040,
  7041. + INT5_eth0Ovr_b = 9,
  7042. + INT5_eth0Ovr_m = 0x00000200,
  7043. + INT5_eth0Und_b = 10,
  7044. + INT5_eth0Und_m = 0x00000400,
  7045. + INT5_eth0Pfd_b = 11,
  7046. + INT5_eth0Pfd_m = 0x00000800,
  7047. + INT5_nvram_b = 12,
  7048. + INT5_nvram_m = 0x00001000,
  7049. +
  7050. + INT6_gpio0_b = 0,
  7051. + INT6_gpio0_m = 0x00000001,
  7052. + INT6_gpio1_b = 1,
  7053. + INT6_gpio1_m = 0x00000002,
  7054. + INT6_gpio2_b = 2,
  7055. + INT6_gpio2_m = 0x00000004,
  7056. + INT6_gpio3_b = 3,
  7057. + INT6_gpio3_m = 0x00000008,
  7058. + INT6_gpio4_b = 4,
  7059. + INT6_gpio4_m = 0x00000010,
  7060. + INT6_gpio5_b = 5,
  7061. + INT6_gpio5_m = 0x00000020,
  7062. + INT6_gpio6_b = 6,
  7063. + INT6_gpio6_m = 0x00000040,
  7064. + INT6_gpio7_b = 7,
  7065. + INT6_gpio7_m = 0x00000080,
  7066. + INT6_gpio8_b = 8,
  7067. + INT6_gpio8_m = 0x00000100,
  7068. + INT6_gpio9_b = 9,
  7069. + INT6_gpio9_m = 0x00000200,
  7070. + INT6_gpio10_b = 10,
  7071. + INT6_gpio10_m = 0x00000400,
  7072. + INT6_gpio11_b = 11,
  7073. + INT6_gpio11_m = 0x00000800,
  7074. + INT6_gpio12_b = 12,
  7075. + INT6_gpio12_m = 0x00001000,
  7076. + INT6_gpio13_b = 13,
  7077. + INT6_gpio13_m = 0x00002000,
  7078. +
  7079. + NMIPS_gpio_b = 0,
  7080. + NMIPS_gpio_m = 0x00000001,
  7081. +} ;
  7082. +
  7083. +#endif // __IDT_INT_H__
  7084. +
  7085. +
  7086. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
  7087. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 1969-12-31 19:00:00.000000000 -0500
  7088. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 2007-09-20 00:16:52.000000000 -0400
  7089. @@ -0,0 +1,90 @@
  7090. +/**************************************************************************
  7091. + *
  7092. + * BRIEF MODULE DESCRIPTION
  7093. + * System Integrity register definition
  7094. + *
  7095. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  7096. + *
  7097. + * This program is free software; you can redistribute it and/or modify it
  7098. + * under the terms of the GNU General Public License as published by the
  7099. + * Free Software Foundation; either version 2 of the License, or (at your
  7100. + * option) any later version.
  7101. + *
  7102. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  7103. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  7104. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  7105. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  7106. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  7107. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  7108. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  7109. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  7110. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  7111. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  7112. + *
  7113. + * You should have received a copy of the GNU General Public License along
  7114. + * with this program; if not, write to the Free Software Foundation, Inc.,
  7115. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  7116. + *
  7117. + *
  7118. + **************************************************************************
  7119. + * May 2004 rkt, neb
  7120. + *
  7121. + * Initial Release
  7122. + *
  7123. + *
  7124. + *
  7125. + **************************************************************************
  7126. + */
  7127. +
  7128. +#ifndef __IDT_INTEG_H__
  7129. +#define __IDT_INTEG_H__
  7130. +
  7131. +enum
  7132. +{
  7133. + INTEG0_PhysicalAddress = 0x18030000,
  7134. + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
  7135. +
  7136. + INTEG0_VirtualAddress = 0xB8030000,
  7137. + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
  7138. +} ;
  7139. +
  7140. +// if you are looking for CEA, try rst.h
  7141. +typedef struct
  7142. +{
  7143. + u32 filler [0xc] ; // 0x30 bytes unused.
  7144. + u32 errcs ; // sticky use ERRCS_
  7145. + u32 wtcount ; // Watchdog timer count reg.
  7146. + u32 wtcompare ; // Watchdog timer timeout value.
  7147. + u32 wtc ; // Watchdog timer control. use WTC_
  7148. +} volatile *INTEG_t ;
  7149. +
  7150. +enum
  7151. +{
  7152. + ERRCS_wto_b = 0, // In INTEG_t -> errcs
  7153. + ERRCS_wto_m = 0x00000001,
  7154. + ERRCS_wne_b = 1, // In INTEG_t -> errcs
  7155. + ERRCS_wne_m = 0x00000002,
  7156. + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
  7157. + ERRCS_ucw_m = 0x00000004,
  7158. + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
  7159. + ERRCS_ucr_m = 0x00000008,
  7160. + ERRCS_upw_b = 4, // In INTEG_t -> errcs
  7161. + ERRCS_upw_m = 0x00000010,
  7162. + ERRCS_upr_b = 5, // In INTEG_t -> errcs
  7163. + ERRCS_upr_m = 0x00000020,
  7164. + ERRCS_udw_b = 6, // In INTEG_t -> errcs
  7165. + ERRCS_udw_m = 0x00000040,
  7166. + ERRCS_udr_b = 7, // In INTEG_t -> errcs
  7167. + ERRCS_udr_m = 0x00000080,
  7168. + ERRCS_sae_b = 8, // In INTEG_t -> errcs
  7169. + ERRCS_sae_m = 0x00000100,
  7170. + ERRCS_wre_b = 9, // In INTEG_t -> errcs
  7171. + ERRCS_wre_m = 0x00000200,
  7172. +
  7173. + WTC_en_b = 0, // In INTEG_t -> wtc
  7174. + WTC_en_m = 0x00000001,
  7175. + WTC_to_b = 1, // In INTEG_t -> wtc
  7176. + WTC_to_m = 0x00000002,
  7177. +} ;
  7178. +
  7179. +#endif // __IDT_INTEG_H__
  7180. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
  7181. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 1969-12-31 19:00:00.000000000 -0500
  7182. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 2007-09-20 00:16:52.000000000 -0400
  7183. @@ -0,0 +1,111 @@
  7184. +/**************************************************************************
  7185. + *
  7186. + * BRIEF MODULE DESCRIPTION
  7187. + * IP Arbiter register definitions
  7188. + *
  7189. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  7190. + *
  7191. + * This program is free software; you can redistribute it and/or modify it
  7192. + * under the terms of the GNU General Public License as published by the
  7193. + * Free Software Foundation; either version 2 of the License, or (at your
  7194. + * option) any later version.
  7195. + *
  7196. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  7197. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  7198. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  7199. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  7200. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  7201. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  7202. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  7203. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  7204. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  7205. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  7206. + *
  7207. + * You should have received a copy of the GNU General Public License along
  7208. + * with this program; if not, write to the Free Software Foundation, Inc.,
  7209. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  7210. + *
  7211. + *
  7212. + **************************************************************************
  7213. + * May 2004 rkt,neb
  7214. + *
  7215. + * Initial Release
  7216. + *
  7217. + *
  7218. + *
  7219. + **************************************************************************
  7220. + */
  7221. +
  7222. +#ifndef __IDT_IPARB_H__
  7223. +#define __IDT_IPARB_H__
  7224. +
  7225. +enum
  7226. +{
  7227. + IPARB0_PhysicalAddress = 0x18048000,
  7228. + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
  7229. +
  7230. + IPARB0_VirtualAddress = 0xB8048000,
  7231. + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
  7232. +} ;
  7233. +
  7234. +enum
  7235. +{
  7236. + IPABMXC_ethernet0Receive = 0,
  7237. + IPABMXC_ethernet0Transmit = 1,
  7238. + IPABMXC_memoryToHoldFifo = 2,
  7239. + IPABMXC_holdFifoToMemory = 3,
  7240. + IPABMXC_pciToMemory = 4,
  7241. + IPABMXC_memoryToPci = 5,
  7242. + IPABMXC_pciTarget = 6,
  7243. + IPABMXC_pciTargetStart = 7,
  7244. + IPABMXC_cpuToIpBus = 8,
  7245. +
  7246. + IPABMXC_Count, // Must be last in list !
  7247. + IPABMXC_Min = IPABMXC_ethernet0Receive,
  7248. +
  7249. + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
  7250. +} ;
  7251. +
  7252. +typedef struct
  7253. +{
  7254. + u32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
  7255. + u32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
  7256. + u32 ipac ; // use IPAC_
  7257. + u32 ipaitcc; // use IPAITCC_
  7258. + u32 ipaspare ;
  7259. +} volatile * IPARB_t ;
  7260. +
  7261. +enum
  7262. +{
  7263. + IPAC_dp_b = 0,
  7264. + IPAC_dp_m = 0x00000001,
  7265. + IPAC_dep_b = 1,
  7266. + IPAC_dep_m = 0x00000002,
  7267. + IPAC_drm_b = 2,
  7268. + IPAC_drm_m = 0x00000004,
  7269. + IPAC_dwm_b = 3,
  7270. + IPAC_dwm_m = 0x00000008,
  7271. + IPAC_msk_b = 4,
  7272. + IPAC_msk_m = 0x00000010,
  7273. +
  7274. + IPAPC_ptc_b = 0,
  7275. + IPAPC_ptc_m = 0x00003fff,
  7276. + IPAPC_mf_b = 14,
  7277. + IPAPC_mf_m = 0x00004000,
  7278. + IPAPC_cptc_b = 16,
  7279. + IPAPC_cptc_m = 0x3fff0000,
  7280. +
  7281. + IPAITCC_itcc = 0,
  7282. + IPAITCC_itcc, = 0x000001ff,
  7283. +
  7284. + IPABMC_mtc_b = 0,
  7285. + IPABMC_mtc_m = 0x00000fff,
  7286. + IPABMC_p_b = 12,
  7287. + IPABMC_p_m = 0x00003000,
  7288. + IPABMC_msk_b = 14,
  7289. + IPABMC_msk_m = 0x00004000,
  7290. + IPABMC_cmtc_b = 16,
  7291. + IPABMC_cmtc_m = 0x0fff0000,
  7292. +};
  7293. +
  7294. +#endif // __IDT_IPARB_H__
  7295. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
  7296. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 1969-12-31 19:00:00.000000000 -0500
  7297. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2007-09-20 00:16:52.000000000 -0400
  7298. @@ -0,0 +1,695 @@
  7299. +/**************************************************************************
  7300. + *
  7301. + * BRIEF MODULE DESCRIPTION
  7302. + * PCI register definitio
  7303. + *
  7304. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  7305. + *
  7306. + * This program is free software; you can redistribute it and/or modify it
  7307. + * under the terms of the GNU General Public License as published by the
  7308. + * Free Software Foundation; either version 2 of the License, or (at your
  7309. + * option) any later version.
  7310. + *
  7311. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  7312. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  7313. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  7314. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  7315. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  7316. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  7317. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  7318. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  7319. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  7320. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  7321. + *
  7322. + * You should have received a copy of the GNU General Public License along
  7323. + * with this program; if not, write to the Free Software Foundation, Inc.,
  7324. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  7325. + *
  7326. + *
  7327. + **************************************************************************
  7328. + * May 2004 rkt, neb.
  7329. + *
  7330. + * Initial Release
  7331. + *
  7332. + *
  7333. + *
  7334. + **************************************************************************
  7335. + */
  7336. +
  7337. +#ifndef __IDT_PCI_H__
  7338. +#define __IDT_PCI_H__
  7339. +
  7340. +enum
  7341. +{
  7342. + PCI0_PhysicalAddress = 0x18080000,
  7343. + PCI_PhysicalAddress = PCI0_PhysicalAddress,
  7344. +
  7345. + PCI0_VirtualAddress = 0xB8080000,
  7346. + PCI_VirtualAddress = PCI0_VirtualAddress,
  7347. +} ;
  7348. +
  7349. +enum
  7350. +{
  7351. + PCI_LbaCount = 4, // Local base addresses.
  7352. +} ;
  7353. +
  7354. +typedef struct
  7355. +{
  7356. + u32 a ; // Address.
  7357. + u32 c ; // Control.
  7358. + u32 m ; // mapping.
  7359. +} PCI_Map_s ;
  7360. +
  7361. +typedef struct
  7362. +{
  7363. + u32 pcic ;
  7364. + u32 pcis ;
  7365. + u32 pcism ;
  7366. + u32 pcicfga ;
  7367. + u32 pcicfgd ;
  7368. + PCI_Map_s pcilba [PCI_LbaCount] ;
  7369. + u32 pcidac ;
  7370. + u32 pcidas ;
  7371. + u32 pcidasm ;
  7372. + u32 pcidad ;
  7373. + u32 pcidma8c ;
  7374. + u32 pcidma9c ;
  7375. + u32 pcitc ;
  7376. +} volatile *PCI_t ;
  7377. +
  7378. +// PCI messaging unit.
  7379. +enum
  7380. +{
  7381. + PCIM_Count = 2,
  7382. +} ;
  7383. +typedef struct
  7384. +{
  7385. + u32 pciim [PCIM_Count] ;
  7386. + u32 pciom [PCIM_Count] ;
  7387. + u32 pciid ;
  7388. + u32 pciiic ;
  7389. + u32 pciiim ;
  7390. + u32 pciiod ;
  7391. + u32 pciioic ;
  7392. + u32 pciioim ;
  7393. +} volatile *PCIM_t ;
  7394. +
  7395. +/*******************************************************************************
  7396. + *
  7397. + * PCI Control Register
  7398. + *
  7399. + ******************************************************************************/
  7400. +enum
  7401. +{
  7402. + PCIC_en_b = 0,
  7403. + PCIC_en_m = 0x00000001,
  7404. + PCIC_tnr_b = 1,
  7405. + PCIC_tnr_m = 0x00000002,
  7406. + PCIC_sce_b = 2,
  7407. + PCIC_sce_m = 0x00000004,
  7408. + PCIC_ien_b = 3,
  7409. + PCIC_ien_m = 0x00000008,
  7410. + PCIC_aaa_b = 4,
  7411. + PCIC_aaa_m = 0x00000010,
  7412. + PCIC_eap_b = 5,
  7413. + PCIC_eap_m = 0x00000020,
  7414. + PCIC_pcim_b = 6,
  7415. + PCIC_pcim_m = 0x000001c0,
  7416. + PCIC_pcim_disabled_v = 0,
  7417. + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
  7418. + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
  7419. + PCIC_pcim_extern_v = 3, // Host - external arbiter.
  7420. + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
  7421. + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
  7422. + PCIC_pcim_reserved6_v = 6,
  7423. + PCIC_pcim_reserved7_v = 7,
  7424. + PCIC_igm_b = 9,
  7425. + PCIC_igm_m = 0x00000200,
  7426. +} ;
  7427. +
  7428. +/*******************************************************************************
  7429. + *
  7430. + * PCI Status Register
  7431. + *
  7432. + ******************************************************************************/
  7433. +enum {
  7434. + PCIS_eed_b = 0,
  7435. + PCIS_eed_m = 0x00000001,
  7436. + PCIS_wr_b = 1,
  7437. + PCIS_wr_m = 0x00000002,
  7438. + PCIS_nmi_b = 2,
  7439. + PCIS_nmi_m = 0x00000004,
  7440. + PCIS_ii_b = 3,
  7441. + PCIS_ii_m = 0x00000008,
  7442. + PCIS_cwe_b = 4,
  7443. + PCIS_cwe_m = 0x00000010,
  7444. + PCIS_cre_b = 5,
  7445. + PCIS_cre_m = 0x00000020,
  7446. + PCIS_mdpe_b = 6,
  7447. + PCIS_mdpe_m = 0x00000040,
  7448. + PCIS_sta_b = 7,
  7449. + PCIS_sta_m = 0x00000080,
  7450. + PCIS_rta_b = 8,
  7451. + PCIS_rta_m = 0x00000100,
  7452. + PCIS_rma_b = 9,
  7453. + PCIS_rma_m = 0x00000200,
  7454. + PCIS_sse_b = 10,
  7455. + PCIS_sse_m = 0x00000400,
  7456. + PCIS_ose_b = 11,
  7457. + PCIS_ose_m = 0x00000800,
  7458. + PCIS_pe_b = 12,
  7459. + PCIS_pe_m = 0x00001000,
  7460. + PCIS_tae_b = 13,
  7461. + PCIS_tae_m = 0x00002000,
  7462. + PCIS_rle_b = 14,
  7463. + PCIS_rle_m = 0x00004000,
  7464. + PCIS_bme_b = 15,
  7465. + PCIS_bme_m = 0x00008000,
  7466. + PCIS_prd_b = 16,
  7467. + PCIS_prd_m = 0x00010000,
  7468. + PCIS_rip_b = 17,
  7469. + PCIS_rip_m = 0x00020000,
  7470. +} ;
  7471. +
  7472. +/*******************************************************************************
  7473. + *
  7474. + * PCI Status Mask Register
  7475. + *
  7476. + ******************************************************************************/
  7477. +enum {
  7478. + PCISM_eed_b = 0,
  7479. + PCISM_eed_m = 0x00000001,
  7480. + PCISM_wr_b = 1,
  7481. + PCISM_wr_m = 0x00000002,
  7482. + PCISM_nmi_b = 2,
  7483. + PCISM_nmi_m = 0x00000004,
  7484. + PCISM_ii_b = 3,
  7485. + PCISM_ii_m = 0x00000008,
  7486. + PCISM_cwe_b = 4,
  7487. + PCISM_cwe_m = 0x00000010,
  7488. + PCISM_cre_b = 5,
  7489. + PCISM_cre_m = 0x00000020,
  7490. + PCISM_mdpe_b = 6,
  7491. + PCISM_mdpe_m = 0x00000040,
  7492. + PCISM_sta_b = 7,
  7493. + PCISM_sta_m = 0x00000080,
  7494. + PCISM_rta_b = 8,
  7495. + PCISM_rta_m = 0x00000100,
  7496. + PCISM_rma_b = 9,
  7497. + PCISM_rma_m = 0x00000200,
  7498. + PCISM_sse_b = 10,
  7499. + PCISM_sse_m = 0x00000400,
  7500. + PCISM_ose_b = 11,
  7501. + PCISM_ose_m = 0x00000800,
  7502. + PCISM_pe_b = 12,
  7503. + PCISM_pe_m = 0x00001000,
  7504. + PCISM_tae_b = 13,
  7505. + PCISM_tae_m = 0x00002000,
  7506. + PCISM_rle_b = 14,
  7507. + PCISM_rle_m = 0x00004000,
  7508. + PCISM_bme_b = 15,
  7509. + PCISM_bme_m = 0x00008000,
  7510. + PCISM_prd_b = 16,
  7511. + PCISM_prd_m = 0x00010000,
  7512. + PCISM_rip_b = 17,
  7513. + PCISM_rip_m = 0x00020000,
  7514. +} ;
  7515. +
  7516. +/*******************************************************************************
  7517. + *
  7518. + * PCI Configuration Address Register
  7519. + *
  7520. + ******************************************************************************/
  7521. +enum {
  7522. + PCICFGA_reg_b = 2,
  7523. + PCICFGA_reg_m = 0x000000fc,
  7524. + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
  7525. + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
  7526. + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
  7527. + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
  7528. + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
  7529. + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
  7530. + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
  7531. + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
  7532. + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
  7533. + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
  7534. + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
  7535. + PCICFGA_reg_pba0m_v = 0x48>>2,
  7536. + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
  7537. + PCICFGA_reg_pba1m_v = 0x50>>2,
  7538. + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
  7539. + PCICFGA_reg_pba2m_v = 0x58>>2,
  7540. + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
  7541. + PCICFGA_reg_pba3m_v = 0x60>>2,
  7542. + PCICFGA_reg_pmgt_v = 0x64>>2,
  7543. + PCICFGA_func_b = 8,
  7544. + PCICFGA_func_m = 0x00000700,
  7545. + PCICFGA_dev_b = 11,
  7546. + PCICFGA_dev_m = 0x0000f800,
  7547. + PCICFGA_dev_internal_v = 0,
  7548. + PCICFGA_bus_b = 16,
  7549. + PCICFGA_bus_m = 0x00ff0000,
  7550. + PCICFGA_bus_type0_v = 0, //local bus
  7551. + PCICFGA_en_b = 31, // read only
  7552. + PCICFGA_en_m = 0x80000000,
  7553. +} ;
  7554. +
  7555. +enum {
  7556. + PCFGID_vendor_b = 0,
  7557. + PCFGID_vendor_m = 0x0000ffff,
  7558. + PCFGID_vendor_IDT_v = 0x111d,
  7559. + PCFGID_device_b = 16,
  7560. + PCFGID_device_m = 0xffff0000,
  7561. + PCFGID_device_Korinade_v = 0x0214,
  7562. +
  7563. + PCFG04_command_ioena_b = 1,
  7564. + PCFG04_command_ioena_m = 0x00000001,
  7565. + PCFG04_command_memena_b = 2,
  7566. + PCFG04_command_memena_m = 0x00000002,
  7567. + PCFG04_command_bmena_b = 3,
  7568. + PCFG04_command_bmena_m = 0x00000004,
  7569. + PCFG04_command_mwinv_b = 5,
  7570. + PCFG04_command_mwinv_m = 0x00000010,
  7571. + PCFG04_command_parena_b = 7,
  7572. + PCFG04_command_parena_m = 0x00000040,
  7573. + PCFG04_command_serrena_b = 9,
  7574. + PCFG04_command_serrena_m = 0x00000100,
  7575. + PCFG04_command_fastbbena_b = 10,
  7576. + PCFG04_command_fastbbena_m = 0x00000200,
  7577. + PCFG04_status_b = 16,
  7578. + PCFG04_status_m = 0xffff0000,
  7579. + PCFG04_status_66MHz_b = 21, // 66 MHz enable
  7580. + PCFG04_status_66MHz_m = 0x00200000,
  7581. + PCFG04_status_fbb_b = 23,
  7582. + PCFG04_status_fbb_m = 0x00800000,
  7583. + PCFG04_status_mdpe_b = 24,
  7584. + PCFG04_status_mdpe_m = 0x01000000,
  7585. + PCFG04_status_dst_b = 25,
  7586. + PCFG04_status_dst_m = 0x06000000,
  7587. + PCFG04_status_sta_b = 27,
  7588. + PCFG04_status_sta_m = 0x08000000,
  7589. + PCFG04_status_rta_b = 28,
  7590. + PCFG04_status_rta_m = 0x10000000,
  7591. + PCFG04_status_rma_b = 29,
  7592. + PCFG04_status_rma_m = 0x20000000,
  7593. + PCFG04_status_sse_b = 30,
  7594. + PCFG04_status_sse_m = 0x40000000,
  7595. + PCFG04_status_pe_b = 31,
  7596. + PCFG04_status_pe_m = 0x40000000,
  7597. +
  7598. + PCFG08_revId_b = 0,
  7599. + PCFG08_revId_m = 0x000000ff,
  7600. + PCFG08_classCode_b = 0,
  7601. + PCFG08_classCode_m = 0xffffff00,
  7602. + PCFG08_classCode_bridge_v = 06,
  7603. + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
  7604. + PCFG0C_cacheline_b = 0,
  7605. + PCFG0C_cacheline_m = 0x000000ff,
  7606. + PCFG0C_masterLatency_b = 8,
  7607. + PCFG0C_masterLatency_m = 0x0000ff00,
  7608. + PCFG0C_headerType_b = 16,
  7609. + PCFG0C_headerType_m = 0x00ff0000,
  7610. + PCFG0C_bist_b = 24,
  7611. + PCFG0C_bist_m = 0xff000000,
  7612. +
  7613. + PCIPBA_msi_b = 0,
  7614. + PCIPBA_msi_m = 0x00000001,
  7615. + PCIPBA_p_b = 3,
  7616. + PCIPBA_p_m = 0x00000004,
  7617. + PCIPBA_baddr_b = 8,
  7618. + PCIPBA_baddr_m = 0xffffff00,
  7619. +
  7620. + PCFGSS_vendorId_b = 0,
  7621. + PCFGSS_vendorId_m = 0x0000ffff,
  7622. + PCFGSS_id_b = 16,
  7623. + PCFGSS_id_m = 0xffff0000,
  7624. +
  7625. + PCFG3C_interruptLine_b = 0,
  7626. + PCFG3C_interruptLine_m = 0x000000ff,
  7627. + PCFG3C_interruptPin_b = 8,
  7628. + PCFG3C_interruptPin_m = 0x0000ff00,
  7629. + PCFG3C_minGrant_b = 16,
  7630. + PCFG3C_minGrant_m = 0x00ff0000,
  7631. + PCFG3C_maxLat_b = 24,
  7632. + PCFG3C_maxLat_m = 0xff000000,
  7633. +
  7634. + PCIPBAC_msi_b = 0,
  7635. + PCIPBAC_msi_m = 0x00000001,
  7636. + PCIPBAC_p_b = 1,
  7637. + PCIPBAC_p_m = 0x00000002,
  7638. + PCIPBAC_size_b = 2,
  7639. + PCIPBAC_size_m = 0x0000007c,
  7640. + PCIPBAC_sb_b = 7,
  7641. + PCIPBAC_sb_m = 0x00000080,
  7642. + PCIPBAC_pp_b = 8,
  7643. + PCIPBAC_pp_m = 0x00000100,
  7644. + PCIPBAC_mr_b = 9,
  7645. + PCIPBAC_mr_m = 0x00000600,
  7646. + PCIPBAC_mr_read_v =0, //no prefetching
  7647. + PCIPBAC_mr_readLine_v =1,
  7648. + PCIPBAC_mr_readMult_v =2,
  7649. + PCIPBAC_mrl_b = 11,
  7650. + PCIPBAC_mrl_m = 0x00000800,
  7651. + PCIPBAC_mrm_b = 12,
  7652. + PCIPBAC_mrm_m = 0x00001000,
  7653. + PCIPBAC_trp_b = 13,
  7654. + PCIPBAC_trp_m = 0x00002000,
  7655. +
  7656. + PCFG40_trdyTimeout_b = 0,
  7657. + PCFG40_trdyTimeout_m = 0x000000ff,
  7658. + PCFG40_retryLim_b = 8,
  7659. + PCFG40_retryLim_m = 0x0000ff00,
  7660. +};
  7661. +
  7662. +/*******************************************************************************
  7663. + *
  7664. + * PCI Local Base Address [0|1|2|3] Register
  7665. + *
  7666. + ******************************************************************************/
  7667. +enum {
  7668. + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
  7669. + PCILBA_baddr_m = 0xffffff00,
  7670. +} ;
  7671. +/*******************************************************************************
  7672. + *
  7673. + * PCI Local Base Address Control Register
  7674. + *
  7675. + ******************************************************************************/
  7676. +enum {
  7677. + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
  7678. + PCILBAC_msi_m = 0x00000001,
  7679. + PCILBAC_msi_mem_v = 0,
  7680. + PCILBAC_msi_io_v = 1,
  7681. + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
  7682. + PCILBAC_size_m = 0x0000007c,
  7683. + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
  7684. + PCILBAC_sb_m = 0x00000080,
  7685. + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
  7686. + PCILBAC_rt_m = 0x00000100,
  7687. + PCILBAC_rt_noprefetch_v = 0, // mem read
  7688. + PCILBAC_rt_prefetch_v = 1, // mem readline
  7689. +} ;
  7690. +
  7691. +/*******************************************************************************
  7692. + *
  7693. + * PCI Local Base Address [0|1|2|3] Mapping Register
  7694. + *
  7695. + ******************************************************************************/
  7696. +enum {
  7697. + PCILBAM_maddr_b = 8,
  7698. + PCILBAM_maddr_m = 0xffffff00,
  7699. +} ;
  7700. +
  7701. +/*******************************************************************************
  7702. + *
  7703. + * PCI Decoupled Access Control Register
  7704. + *
  7705. + ******************************************************************************/
  7706. +enum {
  7707. + PCIDAC_den_b = 0,
  7708. + PCIDAC_den_m = 0x00000001,
  7709. +} ;
  7710. +
  7711. +/*******************************************************************************
  7712. + *
  7713. + * PCI Decoupled Access Status Register
  7714. + *
  7715. + ******************************************************************************/
  7716. +enum {
  7717. + PCIDAS_d_b = 0,
  7718. + PCIDAS_d_m = 0x00000001,
  7719. + PCIDAS_b_b = 1,
  7720. + PCIDAS_b_m = 0x00000002,
  7721. + PCIDAS_e_b = 2,
  7722. + PCIDAS_e_m = 0x00000004,
  7723. + PCIDAS_ofe_b = 3,
  7724. + PCIDAS_ofe_m = 0x00000008,
  7725. + PCIDAS_off_b = 4,
  7726. + PCIDAS_off_m = 0x00000010,
  7727. + PCIDAS_ife_b = 5,
  7728. + PCIDAS_ife_m = 0x00000020,
  7729. + PCIDAS_iff_b = 6,
  7730. + PCIDAS_iff_m = 0x00000040,
  7731. +} ;
  7732. +
  7733. +/*******************************************************************************
  7734. + *
  7735. + * PCI DMA Channel 8 Configuration Register
  7736. + *
  7737. + ******************************************************************************/
  7738. +enum
  7739. +{
  7740. + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
  7741. + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
  7742. + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
  7743. + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
  7744. +} ;
  7745. +
  7746. +/*******************************************************************************
  7747. + *
  7748. + * PCI DMA Channel 9 Configuration Register
  7749. + *
  7750. + ******************************************************************************/
  7751. +enum
  7752. +{
  7753. + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
  7754. + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
  7755. +} ;
  7756. +
  7757. +/*******************************************************************************
  7758. + *
  7759. + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
  7760. + *
  7761. + ******************************************************************************/
  7762. +enum {
  7763. + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
  7764. + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
  7765. + // These are for reads (DMA channel 8)
  7766. + PCIDMAD_devcmd_mr_v = 0, //memory read
  7767. + PCIDMAD_devcmd_mrl_v = 1, //memory read line
  7768. + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
  7769. + PCIDMAD_devcmd_ior_v = 3, //I/O read
  7770. + // These are for writes (DMA channel 9)
  7771. + PCIDMAD_devcmd_mw_v = 0, //memory write
  7772. + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
  7773. + PCIDMAD_devcmd_iow_v = 3, //I/O write
  7774. +
  7775. + // Swap byte field applies to both DMA channel 8 and 9
  7776. + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
  7777. + PCIDMAD_sb_m = 0x01000000, // swap byte field
  7778. +} ;
  7779. +
  7780. +
  7781. +/*******************************************************************************
  7782. + *
  7783. + * PCI Target Control Register
  7784. + *
  7785. + ******************************************************************************/
  7786. +enum
  7787. +{
  7788. + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
  7789. + PCITC_rtimer_m = 0x000000ff,
  7790. + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
  7791. + PCITC_dtimer_m = 0x0000ff00,
  7792. + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
  7793. + PCITC_rdr_m = 0x00040000,
  7794. + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
  7795. + PCITC_ddt_m = 0x00080000,
  7796. +} ;
  7797. +/*******************************************************************************
  7798. + *
  7799. + * PCI messaging unit [applies to both inbound and outbound registers ]
  7800. + *
  7801. + ******************************************************************************/
  7802. +enum
  7803. +{
  7804. + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
  7805. + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
  7806. + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
  7807. + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
  7808. + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
  7809. + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
  7810. +};
  7811. +
  7812. +
  7813. +
  7814. +
  7815. +
  7816. +
  7817. +#define PCI_MSG_VirtualAddress 0xB8088010
  7818. +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
  7819. +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
  7820. +
  7821. +#define PCIM_SHFT 0x6
  7822. +#define PCIM_BIT_LEN 0x7
  7823. +#define PCIM_H_EA 0x3
  7824. +#define PCIM_H_IA_FIX 0x4
  7825. +#define PCIM_H_IA_RR 0x5
  7826. +#if 0
  7827. +#define PCI_ADDR_START 0x13000000
  7828. +#endif
  7829. +
  7830. +#define PCI_ADDR_START 0x50000000
  7831. +
  7832. +#define CPUTOPCI_MEM_WIN 0x02000000
  7833. +#define CPUTOPCI_IO_WIN 0x00100000
  7834. +#define PCILBA_SIZE_SHFT 2
  7835. +#define PCILBA_SIZE_MASK 0x1F
  7836. +#define SIZE_256MB 0x1C
  7837. +#define SIZE_128MB 0x1B
  7838. +#define SIZE_64MB 0x1A
  7839. +#define SIZE_32MB 0x19
  7840. +#define SIZE_16MB 0x18
  7841. +#define SIZE_4MB 0x16
  7842. +#define SIZE_2MB 0x15
  7843. +#define SIZE_1MB 0x14
  7844. +#define KORINA_CONFIG0_ADDR 0x80000000
  7845. +#define KORINA_CONFIG1_ADDR 0x80000004
  7846. +#define KORINA_CONFIG2_ADDR 0x80000008
  7847. +#define KORINA_CONFIG3_ADDR 0x8000000C
  7848. +#define KORINA_CONFIG4_ADDR 0x80000010
  7849. +#define KORINA_CONFIG5_ADDR 0x80000014
  7850. +#define KORINA_CONFIG6_ADDR 0x80000018
  7851. +#define KORINA_CONFIG7_ADDR 0x8000001C
  7852. +#define KORINA_CONFIG8_ADDR 0x80000020
  7853. +#define KORINA_CONFIG9_ADDR 0x80000024
  7854. +#define KORINA_CONFIG10_ADDR 0x80000028
  7855. +#define KORINA_CONFIG11_ADDR 0x8000002C
  7856. +#define KORINA_CONFIG12_ADDR 0x80000030
  7857. +#define KORINA_CONFIG13_ADDR 0x80000034
  7858. +#define KORINA_CONFIG14_ADDR 0x80000038
  7859. +#define KORINA_CONFIG15_ADDR 0x8000003C
  7860. +#define KORINA_CONFIG16_ADDR 0x80000040
  7861. +#define KORINA_CONFIG17_ADDR 0x80000044
  7862. +#define KORINA_CONFIG18_ADDR 0x80000048
  7863. +#define KORINA_CONFIG19_ADDR 0x8000004C
  7864. +#define KORINA_CONFIG20_ADDR 0x80000050
  7865. +#define KORINA_CONFIG21_ADDR 0x80000054
  7866. +#define KORINA_CONFIG22_ADDR 0x80000058
  7867. +#define KORINA_CONFIG23_ADDR 0x8000005C
  7868. +#define KORINA_CONFIG24_ADDR 0x80000060
  7869. +#define KORINA_CONFIG25_ADDR 0x80000064
  7870. +#define KORINA_CMD (PCFG04_command_ioena_m | \
  7871. + PCFG04_command_memena_m | \
  7872. + PCFG04_command_bmena_m | \
  7873. + PCFG04_command_mwinv_m | \
  7874. + PCFG04_command_parena_m | \
  7875. + PCFG04_command_serrena_m )
  7876. +
  7877. +#define KORINA_STAT (PCFG04_status_mdpe_m | \
  7878. + PCFG04_status_sta_m | \
  7879. + PCFG04_status_rta_m | \
  7880. + PCFG04_status_rma_m | \
  7881. + PCFG04_status_sse_m | \
  7882. + PCFG04_status_pe_m)
  7883. +
  7884. +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
  7885. +
  7886. +#define KORINA_REVID 0
  7887. +#define KORINA_CLASS_CODE 0
  7888. +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
  7889. + KORINA_REVID)
  7890. +
  7891. +#define KORINA_CACHE_LINE_SIZE 4
  7892. +#define KORINA_MASTER_LAT 0x3c
  7893. +#define KORINA_HEADER_TYPE 0
  7894. +#define KORINA_BIST 0
  7895. +
  7896. +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
  7897. + (KORINA_HEADER_TYPE<<16) | \
  7898. + (KORINA_MASTER_LAT<<8) | \
  7899. + KORINA_CACHE_LINE_SIZE )
  7900. +
  7901. +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
  7902. +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
  7903. +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
  7904. + internal Registers */
  7905. +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
  7906. +
  7907. +#define KORINA_CNFG4 KORINA_BAR0
  7908. +#define KORINA_CNFG5 KORINA_BAR1
  7909. +#define KORINA_CNFG6 KORINA_BAR2
  7910. +#define KORINA_CNFG7 KORINA_BAR3
  7911. +
  7912. +#define KORINA_SUBSYS_VENDOR_ID 0x011d
  7913. +#define KORINA_SUBSYSTEM_ID 0x0214
  7914. +#define KORINA_CNFG8 0
  7915. +#define KORINA_CNFG9 0
  7916. +#define KORINA_CNFG10 0
  7917. +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
  7918. + KORINA_SUBSYSTEM_ID)
  7919. +#define KORINA_INT_LINE 1
  7920. +#define KORINA_INT_PIN 1
  7921. +#define KORINA_MIN_GNT 8
  7922. +#define KORINA_MAX_LAT 0x38
  7923. +#define KORINA_CNFG12 0
  7924. +#define KORINA_CNFG13 0
  7925. +#define KORINA_CNFG14 0
  7926. +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
  7927. + (KORINA_MIN_GNT<<16) | \
  7928. + (KORINA_INT_PIN<<8) | \
  7929. + KORINA_INT_LINE)
  7930. +#define KORINA_RETRY_LIMIT 0x80
  7931. +#define KORINA_TRDY_LIMIT 0x80
  7932. +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
  7933. + KORINA_TRDY_LIMIT)
  7934. +#define PCI_PBAxC_R 0x0
  7935. +#define PCI_PBAxC_RL 0x1
  7936. +#define PCI_PBAxC_RM 0x2
  7937. +#define SIZE_SHFT 2
  7938. +
  7939. +#if defined(__MIPSEB__)
  7940. +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
  7941. + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
  7942. + PCIPBAC_pp_m | \
  7943. + (SIZE_128MB<<SIZE_SHFT) | \
  7944. + PCIPBAC_p_m)
  7945. +#else
  7946. +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
  7947. + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
  7948. + PCIPBAC_pp_m | \
  7949. + (SIZE_128MB<<SIZE_SHFT) | \
  7950. + PCIPBAC_p_m)
  7951. +#endif
  7952. +#define KORINA_CNFG17 KORINA_PBA0C
  7953. +#define KORINA_PBA0M 0x0
  7954. +#define KORINA_CNFG18 KORINA_PBA0M
  7955. +
  7956. +#if defined(__MIPSEB__)
  7957. +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
  7958. + PCIPBAC_msi_m)
  7959. +#else
  7960. +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
  7961. + PCIPBAC_msi_m)
  7962. +#endif
  7963. +#define KORINA_CNFG19 KORINA_PBA1C
  7964. +#define KORINA_PBA1M 0x0
  7965. +#define KORINA_CNFG20 KORINA_PBA1M
  7966. +
  7967. +#if defined(__MIPSEB__)
  7968. +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
  7969. + PCIPBAC_msi_m)
  7970. +#else
  7971. +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
  7972. + PCIPBAC_msi_m)
  7973. +#endif
  7974. +#define KORINA_CNFG21 KORINA_PBA2C
  7975. +#define KORINA_PBA2M 0x18000000
  7976. +#define KORINA_CNFG22 KORINA_PBA2M
  7977. +#define KORINA_PBA3C 0
  7978. +#define KORINA_CNFG23 KORINA_PBA3C
  7979. +#define KORINA_PBA3M 0
  7980. +#define KORINA_CNFG24 KORINA_PBA3M
  7981. +
  7982. +
  7983. +
  7984. +#define PCITC_DTIMER_VAL 8
  7985. +#define PCITC_RTIMER_VAL 0x10
  7986. +
  7987. +
  7988. +
  7989. +
  7990. +#endif // __IDT_PCI_H__
  7991. +
  7992. +
  7993. +
  7994. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
  7995. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 1969-12-31 19:00:00.000000000 -0500
  7996. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2007-09-20 00:16:52.000000000 -0400
  7997. @@ -0,0 +1,119 @@
  7998. +/**************************************************************************
  7999. + *
  8000. + * BRIEF MODULE DESCRIPTION
  8001. + * Reset register definitions.
  8002. + *
  8003. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  8004. + *
  8005. + * This program is free software; you can redistribute it and/or modify it
  8006. + * under the terms of the GNU General Public License as published by the
  8007. + * Free Software Foundation; either version 2 of the License, or (at your
  8008. + * option) any later version.
  8009. + *
  8010. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  8011. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  8012. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  8013. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  8014. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  8015. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  8016. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  8017. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  8018. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  8019. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  8020. + *
  8021. + * You should have received a copy of the GNU General Public License along
  8022. + * with this program; if not, write to the Free Software Foundation, Inc.,
  8023. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  8024. + *
  8025. + *
  8026. + **************************************************************************
  8027. + * May 2004 rkt, neb.
  8028. + *
  8029. + * Initial Release
  8030. + *
  8031. + *
  8032. + *
  8033. + **************************************************************************
  8034. + */
  8035. +
  8036. +#ifndef __IDT_RST_H__
  8037. +#define __IDT_RST_H__
  8038. +
  8039. +enum
  8040. +{
  8041. + RST0_PhysicalAddress = 0x18000000,
  8042. + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
  8043. +
  8044. + RST0_VirtualAddress = 0xb8000000,
  8045. + RST_VirtualAddress = RST0_VirtualAddress, // Default
  8046. +} ;
  8047. +
  8048. +typedef struct RST_s
  8049. +{
  8050. + u32 filler [0x0006] ;
  8051. + u32 sysid ;
  8052. + u32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
  8053. + u32 reset ;
  8054. + u32 bcv ;
  8055. + u32 cea ;
  8056. +} volatile * RST_t ;
  8057. +
  8058. +enum
  8059. +{
  8060. + SYSID_rev_b = 0,
  8061. + SYSID_rev_m = 0x000000ff,
  8062. + SYSID_imp_b = 8,
  8063. + SYSID_imp_m = 0x000fff00,
  8064. + SYSID_vendor_b = 8,
  8065. + SYSID_vendor_m = 0xfff00000,
  8066. +
  8067. + BCV_pll_b = 0,
  8068. + BCV_pll_m = 0x0000000f,
  8069. + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
  8070. + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
  8071. + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
  8072. + BCV_pll_SlowMul5_v = 0x3, // PCLK=5*CLK.
  8073. + BCV_pll_Mul5_v = 0x4, // PCLK=5*CLK.
  8074. + BCV_pll_SlowMul6_v = 0x5, // PCLK=6*CLK.
  8075. + BCV_pll_Mul6_v = 0x6, // PCLK=6*CLK.
  8076. + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
  8077. + BCV_pll_Mul10_v = 0x8, // PCLK=10*CLK.
  8078. + BCV_pll_Res9_v = 0x9,
  8079. + BCV_pll_Res10_v = 0xa,
  8080. + BCV_pll_Res11_v = 0xb,
  8081. + BCV_pll_Res12_v = 0xc,
  8082. + BCV_pll_Res13_v = 0xd,
  8083. + BCV_pll_Res14_v = 0xe,
  8084. + BCV_pll_Res15_v = 0xf,
  8085. + BCV_clkDiv_b = 4,
  8086. + BCV_clkDiv_m = 0x00000030,
  8087. + BCV_clkDiv_Div1_v = 0x0,
  8088. + BCV_clkDiv_Div2_v = 0x1,
  8089. + BCV_clkDiv_Div4_v = 0x2,
  8090. + BCV_clkDiv_Res3_v = 0x3,
  8091. + BCV_bigEndian_b = 6,
  8092. + BCV_bigEndian_m = 0x00000040,
  8093. + BCV_resetFast_b = 7,
  8094. + BCV_resetFast_m = 0x00000080,
  8095. + BCV_pciMode_b = 8,
  8096. + BCV_pciMode_m = 0x00000700,
  8097. + BCV_pciMode_disabled_v = 0, // PCI is disabled.
  8098. + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
  8099. + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
  8100. + BCV_pciMode_external_v = 3, // host, external arbiter.
  8101. + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
  8102. + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
  8103. + BCV_pciMode_res6_v = 6,
  8104. + BCV_pciMode_res7_v = 7,
  8105. + BCV_watchDisable_b = 11,
  8106. + BCV_watchDisable_m = 0x00000800,
  8107. + BCV_res12_b = 12,
  8108. + BCV_res12_m = 0x00001000,
  8109. + BCV_res13_b = 13,
  8110. + BCV_res13_m = 0x00002000,
  8111. + BCV_res14_b = 14,
  8112. + BCV_res14_m = 0x00004000,
  8113. + BCV_res15_b = 15,
  8114. + BCV_res15_m = 0x00008000,
  8115. +} ;
  8116. +#endif // __IDT_RST_H__
  8117. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
  8118. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 1969-12-31 19:00:00.000000000 -0500
  8119. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2007-09-20 00:16:52.000000000 -0400
  8120. @@ -0,0 +1,120 @@
  8121. +/**************************************************************************
  8122. + *
  8123. + * BRIEF MODULE DESCRIPTION
  8124. + * Serial Peripheral Interface register definitions.
  8125. + *
  8126. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  8127. + *
  8128. + * This program is free software; you can redistribute it and/or modify it
  8129. + * under the terms of the GNU General Public License as published by the
  8130. + * Free Software Foundation; either version 2 of the License, or (at your
  8131. + * option) any later version.
  8132. + *
  8133. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  8134. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  8135. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  8136. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  8137. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  8138. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  8139. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  8140. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  8141. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  8142. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  8143. + *
  8144. + * You should have received a copy of the GNU General Public License along
  8145. + * with this program; if not, write to the Free Software Foundation, Inc.,
  8146. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  8147. + *
  8148. + *
  8149. + **************************************************************************
  8150. + * May 2004 rkt, neb.
  8151. + *
  8152. + * Initial Release
  8153. + *
  8154. + *
  8155. + *
  8156. + **************************************************************************
  8157. + */
  8158. +
  8159. +#ifndef __IDT_SPI_H__
  8160. +#define __IDT_SPI_H__
  8161. +
  8162. +enum
  8163. +{
  8164. + SPI0_PhysicalAddress = 0x18070000,
  8165. + SPI_PhysicalAddress = SPI0_PhysicalAddress,
  8166. +
  8167. + SPI0_VirtualAddress = 0xB8070000,
  8168. + SPI_VirtualAddress = SPI0_VirtualAddress,
  8169. +} ;
  8170. +
  8171. +typedef struct
  8172. +{
  8173. + u32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
  8174. + u32 spc ; // spi control reg use SPC_
  8175. + u32 sps ; // spi status reg use SPS_
  8176. + u32 spd ; // spi data reg use SPD_
  8177. + u32 siofunc ; // serial IO function use SIOFUNC_
  8178. + u32 siocfg ; // serial IO config use SIOCFG_
  8179. + u32 siod; // serial IO data use SIOD_
  8180. +} volatile *SPI_t ;
  8181. +
  8182. +enum
  8183. +{
  8184. + SPCP_div_b = 0,
  8185. + SPCP_div_m = 0x000000ff,
  8186. + SPC_spr_b = 0,
  8187. + SPC_spr_m = 0x00000003,
  8188. + SPC_spr_div2_v = 0,
  8189. + SPC_spr_div4_v = 1,
  8190. + SPC_spr_div16_v = 2,
  8191. + SPC_spr_div32_v = 3,
  8192. + SPC_cpha_b = 2,
  8193. + SPC_cpha_m = 0x00000004,
  8194. + SPC_cpol_b = 3,
  8195. + SPC_cpol_m = 0x00000008,
  8196. + SPC_mstr_b = 4,
  8197. + SPC_mstr_m = 0x00000010,
  8198. + SPC_spe_b = 6,
  8199. + SPC_spe_m = 0x00000040,
  8200. + SPC_spie_b = 7,
  8201. + SPC_spie_m = 0x00000080,
  8202. +
  8203. + SPS_modf_b = 4,
  8204. + SPS_modf_m = 0x00000010,
  8205. + SPS_wcol_b = 6,
  8206. + SPS_wcol_m = 0x00000040,
  8207. + SPS_spif_b = 7,
  8208. + SPS_spif_m = 0x00000070,
  8209. +
  8210. + SPD_data_b = 0,
  8211. + SPD_data_m = 0x000000ff,
  8212. +
  8213. + SIOFUNC_sdo_b = 0,
  8214. + SIOFUNC_sdo_m = 0x00000001,
  8215. + SIOFUNC_sdi_b = 1,
  8216. + SIOFUNC_sdi_m = 0x00000002,
  8217. + SIOFUNC_sck_b = 2,
  8218. + SIOFUNC_sck_m = 0x00000004,
  8219. + SIOFUNC_pci_b = 3,
  8220. + SIOFUNC_pci_m = 0x00000008,
  8221. +
  8222. + SIOCFG_sdo_b = 0,
  8223. + SIOCFG_sdo_m = 0x00000001,
  8224. + SIOCFG_sdi_b = 1,
  8225. + SIOCFG_sdi_m = 0x00000002,
  8226. + SIOCFG_sck_b = 2,
  8227. + SIOCFG_sck_m = 0x00000004,
  8228. + SIOCFG_pci_b = 3,
  8229. + SIOCFG_pci_m = 0x00000008,
  8230. +
  8231. + SIOD_sdo_b = 0,
  8232. + SIOD_sdo_m = 0x00000001,
  8233. + SIOD_sdi_b = 1,
  8234. + SIOD_sdi_m = 0x00000002,
  8235. + SIOD_sck_b = 2,
  8236. + SIOD_sck_m = 0x00000004,
  8237. + SIOD_pci_b = 3,
  8238. + SIOD_pci_m = 0x00000008,
  8239. +} ;
  8240. +#endif // __IDT_SPI_H__
  8241. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
  8242. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 1969-12-31 19:00:00.000000000 -0500
  8243. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 2007-09-20 00:16:52.000000000 -0400
  8244. @@ -0,0 +1,91 @@
  8245. +/**************************************************************************
  8246. + *
  8247. + * BRIEF MODULE DESCRIPTION
  8248. + * Definitions for timer registers
  8249. + *
  8250. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  8251. + *
  8252. + * This program is free software; you can redistribute it and/or modify it
  8253. + * under the terms of the GNU General Public License as published by the
  8254. + * Free Software Foundation; either version 2 of the License, or (at your
  8255. + * option) any later version.
  8256. + *
  8257. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  8258. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  8259. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  8260. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  8261. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  8262. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  8263. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  8264. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  8265. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  8266. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  8267. + *
  8268. + * You should have received a copy of the GNU General Public License along
  8269. + * with this program; if not, write to the Free Software Foundation, Inc.,
  8270. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  8271. + *
  8272. + *
  8273. + **************************************************************************
  8274. + * May 2004 rkt,neb.
  8275. + *
  8276. + * Initial Release
  8277. + *
  8278. + *
  8279. + *
  8280. + **************************************************************************
  8281. + */
  8282. +
  8283. +#ifndef __IDT_TIM_H__
  8284. +#define __IDT_TIM_H__
  8285. +
  8286. +enum
  8287. +{
  8288. + TIM0_PhysicalAddress = 0x18028000,
  8289. + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
  8290. +
  8291. + TIM0_VirtualAddress = 0xb8028000,
  8292. + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
  8293. +} ;
  8294. +
  8295. +enum
  8296. +{
  8297. + TIM_Count = 3,
  8298. +} ;
  8299. +
  8300. +struct TIM_CNTR_s
  8301. +{
  8302. + u32 count ;
  8303. + u32 compare ;
  8304. + u32 ctc ; //use CTC_
  8305. +} ;
  8306. +
  8307. +typedef struct TIM_s
  8308. +{
  8309. + struct TIM_CNTR_s tim [TIM_Count] ;
  8310. + u32 rcount ; //use RCOUNT_
  8311. + u32 rcompare ; //use RCOMPARE_
  8312. + u32 rtc ; //use RTC_
  8313. +} volatile * TIM_t ;
  8314. +
  8315. +enum
  8316. +{
  8317. + CTC_en_b = 0,
  8318. + CTC_en_m = 0x00000001,
  8319. + CTC_to_b = 1,
  8320. + CTC_to_m = 0x00000002,
  8321. +
  8322. + RCOUNT_count_b = 0,
  8323. + RCOUNT_count_m = 0x0000ffff,
  8324. + RCOMPARE_compare_b = 0,
  8325. + RCOMPARE_compare_m = 0x0000ffff,
  8326. + RTC_ce_b = 0,
  8327. + RTC_ce_m = 0x00000001,
  8328. + RTC_to_b = 1,
  8329. + RTC_to_m = 0x00000002,
  8330. + RTC_rqe_b = 2,
  8331. + RTC_rqe_m = 0x00000004,
  8332. +
  8333. +} ;
  8334. +#endif // __IDT_TIM_H__
  8335. +
  8336. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
  8337. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 1969-12-31 19:00:00.000000000 -0500
  8338. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 2007-09-20 00:16:52.000000000 -0400
  8339. @@ -0,0 +1,189 @@
  8340. +/**************************************************************************
  8341. + *
  8342. + * BRIEF MODULE DESCRIPTION
  8343. + * UART register definitions
  8344. + *
  8345. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  8346. + *
  8347. + * This program is free software; you can redistribute it and/or modify it
  8348. + * under the terms of the GNU General Public License as published by the
  8349. + * Free Software Foundation; either version 2 of the License, or (at your
  8350. + * option) any later version.
  8351. + *
  8352. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  8353. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  8354. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  8355. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  8356. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  8357. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  8358. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  8359. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  8360. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  8361. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  8362. + *
  8363. + * You should have received a copy of the GNU General Public License along
  8364. + * with this program; if not, write to the Free Software Foundation, Inc.,
  8365. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  8366. + *
  8367. + *
  8368. + **************************************************************************
  8369. + * May 2004 rkt, neb.
  8370. + *
  8371. + * Initial Release
  8372. + *
  8373. + *
  8374. + *
  8375. + **************************************************************************
  8376. + */
  8377. +
  8378. +#ifndef __IDT_UART_H__
  8379. +#define __IDT_UART_H__
  8380. +
  8381. +enum
  8382. +{
  8383. + UART0_PhysicalAddress = 0x1c000000,
  8384. + UART_PhysicalAddress = UART0_PhysicalAddress, // Default
  8385. +
  8386. + UART0_VirtualAddress = 0xbc000000,
  8387. + UART_VirtualAddress = UART0_VirtualAddress, // Default
  8388. +} ;
  8389. +
  8390. +/*
  8391. + * Register definitions are in bytes so we can handle endian problems.
  8392. + */
  8393. +
  8394. +typedef struct UART_s
  8395. +{
  8396. + union
  8397. + {
  8398. + u32 const uartrb ; // 0x00 - DLAB=0, read.
  8399. + u32 uartth ; // 0x00 - DLAB=0, write.
  8400. + u32 uartdll ; // 0x00 - DLAB=1, read/write.
  8401. + } ;
  8402. +
  8403. + union
  8404. + {
  8405. + u32 uartie ; // 0x04 - DLAB=0, read/write.
  8406. + u32 uartdlh ; // 0x04 - DLAB=1, read/write.
  8407. + } ;
  8408. + union
  8409. + {
  8410. + u32 const uartii ; // 0x08 - DLAB=0, read.
  8411. + u32 uartfc ; // 0x08 - DLAB=0, write.
  8412. + } ;
  8413. +
  8414. + u32 uartlc ; // 0x0c
  8415. + u32 uartmc ; // 0x10
  8416. + u32 uartls ; // 0x14
  8417. + u32 uartms ; // 0x18
  8418. + u32 uarts ; // 0x1c
  8419. +} volatile *UART_t ;
  8420. +
  8421. +// Reset registers.
  8422. +typedef u32 volatile *UARTRR_t ;
  8423. +
  8424. +enum
  8425. +{
  8426. + UARTIE_rda_b = 0,
  8427. + UARTIE_rda_m = 0x00000001,
  8428. + UARTIE_the_b = 1,
  8429. + UARTIE_the_m = 0x00000002,
  8430. + UARTIE_rls_b = 2,
  8431. + UARTIE_rls_m = 0x00000004,
  8432. + UARTIE_ems_b = 3,
  8433. + UARTIE_ems_m = 0x00000008,
  8434. +
  8435. + UARTII_pi_b = 0,
  8436. + UARTII_pi_m = 0x00000001,
  8437. + UARTII_iid_b = 1,
  8438. + UARTII_iid_m = 0x0000000e,
  8439. + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
  8440. + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
  8441. + UARTII_iid_rda_v = 2, // Receive data available
  8442. + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
  8443. + UARTII_iid_res4_v = 4, // reserved.
  8444. + UARTII_iid_res5_v = 5, // reserved.
  8445. + UARTII_iid_cto_v = 6, // Character timeout.
  8446. + UARTII_iid_res7_v = 7, // reserved.
  8447. +
  8448. + UARTFC_en_b = 0,
  8449. + UARTFC_en_m = 0x00000001,
  8450. + UARTFC_rr_b = 1,
  8451. + UARTFC_rr_m = 0x00000002,
  8452. + UARTFC_tr_b = 2,
  8453. + UARTFC_tr_m = 0x00000004,
  8454. + UARTFC_dms_b = 3,
  8455. + UARTFC_dms_m = 0x00000008,
  8456. + UARTFC_rt_b = 6,
  8457. + UARTFC_rt_m = 0x000000c0,
  8458. + UARTFC_rt_1Byte_v = 0,
  8459. + UARTFC_rt_4Byte_v = 1,
  8460. + UARTFC_rt_8Byte_v = 2,
  8461. + UARTFC_rt_14Byte_v = 3,
  8462. +
  8463. + UARTLC_wls_b = 0,
  8464. + UARTLC_wls_m = 0x00000003,
  8465. + UARTLC_wls_5Bits_v = 0,
  8466. + UARTLC_wls_6Bits_v = 1,
  8467. + UARTLC_wls_7Bits_v = 2,
  8468. + UARTLC_wls_8Bits_v = 3,
  8469. + UARTLC_stb_b = 2,
  8470. + UARTLC_stb_m = 0x00000004,
  8471. + UARTLC_pen_b = 3,
  8472. + UARTLC_pen_m = 0x00000008,
  8473. + UARTLC_eps_b = 4,
  8474. + UARTLC_eps_m = 0x00000010,
  8475. + UARTLC_sp_b = 5,
  8476. + UARTLC_sp_m = 0x00000020,
  8477. + UARTLC_sb_b = 6,
  8478. + UARTLC_sb_m = 0x00000040,
  8479. + UARTLC_dlab_b = 7,
  8480. + UARTLC_dlab_m = 0x00000080,
  8481. +
  8482. + UARTMC_dtr_b = 0,
  8483. + UARTMC_dtr_m = 0x00000001,
  8484. + UARTMC_rts_b = 1,
  8485. + UARTMC_rts_m = 0x00000002,
  8486. + UARTMC_o1_b = 2,
  8487. + UARTMC_o1_m = 0x00000004,
  8488. + UARTMC_o2_b = 3,
  8489. + UARTMC_o2_m = 0x00000008,
  8490. + UARTMC_lp_b = 4,
  8491. + UARTMC_lp_m = 0x00000010,
  8492. +
  8493. + UARTLS_dr_b = 0,
  8494. + UARTLS_dr_m = 0x00000001,
  8495. + UARTLS_oe_b = 1,
  8496. + UARTLS_oe_m = 0x00000002,
  8497. + UARTLS_pe_b = 2,
  8498. + UARTLS_pe_m = 0x00000004,
  8499. + UARTLS_fe_b = 3,
  8500. + UARTLS_fe_m = 0x00000008,
  8501. + UARTLS_bi_b = 4,
  8502. + UARTLS_bi_m = 0x00000010,
  8503. + UARTLS_thr_b = 5,
  8504. + UARTLS_thr_m = 0x00000020,
  8505. + UARTLS_te_b = 6,
  8506. + UARTLS_te_m = 0x00000040,
  8507. + UARTLS_rfe_b = 7,
  8508. + UARTLS_rfe_m = 0x00000080,
  8509. +
  8510. + UARTMS_dcts_b = 0,
  8511. + UARTMS_dcts_m = 0x00000001,
  8512. + UARTMS_ddsr_b = 1,
  8513. + UARTMS_ddsr_m = 0x00000002,
  8514. + UARTMS_teri_b = 2,
  8515. + UARTMS_teri_m = 0x00000004,
  8516. + UARTMS_ddcd_b = 3,
  8517. + UARTMS_ddcd_m = 0x00000008,
  8518. + UARTMS_cts_b = 4,
  8519. + UARTMS_cts_m = 0x00000010,
  8520. + UARTMS_dsr_b = 5,
  8521. + UARTMS_dsr_m = 0x00000020,
  8522. + UARTMS_ri_b = 6,
  8523. + UARTMS_ri_m = 0x00000040,
  8524. + UARTMS_dcd_b = 7,
  8525. + UARTMS_dcd_m = 0x00000080,
  8526. +} ;
  8527. +
  8528. +#endif // __IDT_UART_H__
  8529. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438.h
  8530. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438.h 1969-12-31 19:00:00.000000000 -0500
  8531. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438.h 2007-09-20 00:16:52.000000000 -0400
  8532. @@ -0,0 +1,152 @@
  8533. +/**************************************************************************
  8534. + *
  8535. + * BRIEF MODULE DESCRIPTION
  8536. + * Definitions for IDT RC32438 CPU.
  8537. + *
  8538. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  8539. + *
  8540. + * This program is free software; you can redistribute it and/or modify it
  8541. + * under the terms of the GNU General Public License as published by the
  8542. + * Free Software Foundation; either version 2 of the License, or (at your
  8543. + * option) any later version.
  8544. + *
  8545. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  8546. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  8547. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  8548. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  8549. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  8550. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  8551. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  8552. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  8553. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  8554. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  8555. + *
  8556. + * You should have received a copy of the GNU General Public License along
  8557. + * with this program; if not, write to the Free Software Foundation, Inc.,
  8558. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  8559. + *
  8560. + *
  8561. + **************************************************************************
  8562. + * May 2004 P. Sadik.
  8563. + *
  8564. + * Initial Release
  8565. + *
  8566. + *
  8567. + *
  8568. + **************************************************************************
  8569. + */
  8570. +
  8571. +#ifndef __IDT_RC32438_H__
  8572. +#define __IDT_RC32438_H__
  8573. +#include <linux/autoconf.h>
  8574. +#include <linux/delay.h>
  8575. +#include <asm/io.h>
  8576. +#include <asm/idt-boards/rc32438/rc32438_timer.h>
  8577. +
  8578. +#define RC32438_REG_BASE 0x18000000
  8579. +
  8580. +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
  8581. +#define idttimer ((volatile TIM_t) TIM0_VirtualAddress)
  8582. +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
  8583. +
  8584. +#define IDT_CLOCK_MULT 2
  8585. +#define MIPS_CPU_TIMER_IRQ 7
  8586. +/* Interrupt Controller */
  8587. +#define IC_GROUP0_PEND (RC32438_REG_BASE + 0x38000)
  8588. +#define IC_GROUP0_MASK (RC32438_REG_BASE + 0x38008)
  8589. +#define IC_GROUP_OFFSET 0x0C
  8590. +#define RTC_BASE 0xAC0801FF0
  8591. +
  8592. +#define NUM_INTR_GROUPS 5
  8593. +/* 16550 UARTs */
  8594. +
  8595. +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
  8596. +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
  8597. +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
  8598. +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
  8599. +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
  8600. +
  8601. +#ifdef __MIPSEB__
  8602. +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
  8603. +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
  8604. +#else
  8605. +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
  8606. +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
  8607. +#endif
  8608. +
  8609. +#define RC32438_UART0_IRQ GROUP3_IRQ_BASE + 0
  8610. +#define RC32438_UART1_IRQ GROUP3_IRQ_BASE + 3
  8611. +
  8612. +#define RC32438_NR_IRQS (GROUP4_IRQ_BASE + 32)
  8613. +
  8614. +
  8615. +
  8616. +/* cpu pipeline flush */
  8617. +static inline void rc32438_sync(void)
  8618. +{
  8619. + __asm__ volatile ("sync");
  8620. +}
  8621. +
  8622. +static inline void rc32438_sync_udelay(int us)
  8623. +{
  8624. + __asm__ volatile ("sync");
  8625. + udelay(us);
  8626. +}
  8627. +
  8628. +static inline void rc32438_sync_delay(int ms)
  8629. +{
  8630. + __asm__ volatile ("sync");
  8631. + mdelay(ms);
  8632. +}
  8633. +
  8634. +/*
  8635. + * Macros to access internal RC32438 registers. No byte
  8636. + * swapping should be done when accessing the internal
  8637. + * registers.
  8638. + */
  8639. +
  8640. +#define rc32438_readb __raw_readb
  8641. +#define rc32438_readw __raw_readw
  8642. +#define rc32438_readl __raw_readl
  8643. +
  8644. +#define rc32438_writeb __raw_writeb
  8645. +#define rc32438_writew __raw_writew
  8646. +#define rc32438_writel __raw_writel
  8647. +
  8648. +/*
  8649. + * C access to CLZ and CLO instructions
  8650. + * (count leading zeroes/ones).
  8651. + */
  8652. +static inline int rc32438_clz(unsigned long val)
  8653. +{
  8654. + int ret;
  8655. + __asm__ volatile (
  8656. + ".set\tnoreorder\n\t"
  8657. + ".set\tnoat\n\t"
  8658. + ".set\tmips32\n\t"
  8659. + "clz\t%0,%1\n\t"
  8660. + ".set\tmips0\n\t"
  8661. + ".set\tat\n\t"
  8662. + ".set\treorder"
  8663. + : "=r" (ret)
  8664. + : "r" (val));
  8665. +
  8666. + return ret;
  8667. +}
  8668. +static inline int rc32438_clo(unsigned long val)
  8669. +{
  8670. + int ret;
  8671. + __asm__ volatile (
  8672. + ".set\tnoreorder\n\t"
  8673. + ".set\tnoat\n\t"
  8674. + ".set\tmips32\n\t"
  8675. + "clo\t%0,%1\n\t"
  8676. + ".set\tmips0\n\t"
  8677. + ".set\tat\n\t"
  8678. + ".set\treorder"
  8679. + : "=r" (ret)
  8680. + : "r" (val));
  8681. +
  8682. + return ret;
  8683. +}
  8684. +#endif //__IDT_RC32438_H__
  8685. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
  8686. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 1969-12-31 19:00:00.000000000 -0500
  8687. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2007-09-20 00:16:52.000000000 -0400
  8688. @@ -0,0 +1,231 @@
  8689. +/**************************************************************************
  8690. + *
  8691. + * BRIEF MODULE DESCRIPTION
  8692. + * Register definitions for IDT RC32438 DMA.
  8693. + *
  8694. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  8695. + *
  8696. + * This program is free software; you can redistribute it and/or modify it
  8697. + * under the terms of the GNU General Public License as published by the
  8698. + * Free Software Foundation; either version 2 of the License, or (at your
  8699. + * option) any later version.
  8700. + *
  8701. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  8702. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  8703. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  8704. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  8705. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  8706. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  8707. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  8708. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  8709. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  8710. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  8711. + *
  8712. + * You should have received a copy of the GNU General Public License along
  8713. + * with this program; if not, write to the Free Software Foundation, Inc.,
  8714. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  8715. + *
  8716. + *
  8717. + **************************************************************************
  8718. + * May 2004 P. Sadik.
  8719. + *
  8720. + * Initial Release
  8721. + *
  8722. + *
  8723. + *
  8724. + **************************************************************************
  8725. + */
  8726. +#ifndef __IDT_RC32438_DMA_H__
  8727. +#define __IDT_RC32438_DMA_H__
  8728. +enum
  8729. +{
  8730. + DMA0_PhysicalAddress = 0x18040000,
  8731. + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
  8732. +
  8733. + DMA0_VirtualAddress = 0xb8040000,
  8734. + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
  8735. +} ;
  8736. +
  8737. +/*
  8738. + * DMA descriptor (in physical memory).
  8739. + */
  8740. +
  8741. +typedef struct DMAD_s
  8742. +{
  8743. + u32 control ; // Control. use DMAD_*
  8744. + u32 ca ; // Current Address.
  8745. + u32 devcs ; // Device control and status.
  8746. + u32 link ; // Next descriptor in chain.
  8747. +} volatile *DMAD_t ;
  8748. +
  8749. +enum
  8750. +{
  8751. + DMAD_size = sizeof (struct DMAD_s),
  8752. + DMAD_count_b = 0, // in DMAD_t -> control
  8753. + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
  8754. + DMAD_ds_b = 20, // in DMAD_t -> control
  8755. + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
  8756. + DMAD_ds_extToMem0_v = 0,
  8757. + DMAD_ds_memToExt0_v = 1,
  8758. + DMAD_ds_extToMem1_v = 0,
  8759. + DMAD_ds_memToExt1_v = 1,
  8760. + DMAD_ds_ethRcv0_v = 0,
  8761. + DMAD_ds_ethXmt0_v = 0,
  8762. + DMAD_ds_ethRcv1_v = 0,
  8763. + DMAD_ds_ethXmt2_v = 0,
  8764. + DMAD_ds_memToFifo_v = 0,
  8765. + DMAD_ds_fifoToMem_v = 0,
  8766. + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
  8767. + DMAD_ds_pciToMem_v = 0,
  8768. + DMAD_ds_memToPci_v = 0,
  8769. + DMAD_ds_securityInput_v = 0,
  8770. + DMAD_ds_securityOutput_v = 0,
  8771. + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
  8772. +
  8773. + DMAD_devcmd_b = 22, // in DMAD_t -> control
  8774. + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
  8775. + DMAD_devcmd_byte_v = 0, //memory-to-memory
  8776. + DMAD_devcmd_halfword_v = 1, //memory-to-memory
  8777. + DMAD_devcmd_word_v = 2, //memory-to-memory
  8778. + DMAD_devcmd_2words_v = 3, //memory-to-memory
  8779. + DMAD_devcmd_4words_v = 4, //memory-to-memory
  8780. + DMAD_devcmd_6words_v = 5, //memory-to-memory
  8781. + DMAD_devcmd_8words_v = 6, //memory-to-memory
  8782. + DMAD_devcmd_16words_v = 7, //memory-to-memory
  8783. + DMAD_cof_b = 25, // chain on finished
  8784. + DMAD_cof_m = 0x02000000, //
  8785. + DMAD_cod_b = 26, // chain on done
  8786. + DMAD_cod_m = 0x04000000, //
  8787. + DMAD_iof_b = 27, // interrupt on finished
  8788. + DMAD_iof_m = 0x08000000, //
  8789. + DMAD_iod_b = 28, // interrupt on done
  8790. + DMAD_iod_m = 0x10000000, //
  8791. + DMAD_t_b = 29, // terminated
  8792. + DMAD_t_m = 0x20000000, //
  8793. + DMAD_d_b = 30, // done
  8794. + DMAD_d_m = 0x40000000, //
  8795. + DMAD_f_b = 31, // finished
  8796. + DMAD_f_m = 0x80000000, //
  8797. +} ;
  8798. +
  8799. +/*
  8800. + * DMA register (within Internal Register Map).
  8801. + */
  8802. +
  8803. +struct DMA_Chan_s
  8804. +{
  8805. + u32 dmac ; // Control.
  8806. + u32 dmas ; // Status.
  8807. + u32 dmasm ; // Mask.
  8808. + u32 dmadptr ; // Descriptor pointer.
  8809. + u32 dmandptr ; // Next descriptor pointer.
  8810. +};
  8811. +
  8812. +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
  8813. +
  8814. +//DMA_Channels use DMACH_count instead
  8815. +
  8816. +enum
  8817. +{
  8818. + DMAC_run_b = 0, //
  8819. + DMAC_run_m = 0x00000001, //
  8820. + DMAC_dm_b = 1, // done mask
  8821. + DMAC_dm_m = 0x00000002, //
  8822. + DMAC_mode_b = 2, //
  8823. + DMAC_mode_m = 0x0000000c, //
  8824. + DMAC_mode_auto_v = 0,
  8825. + DMAC_mode_burst_v = 1,
  8826. + DMAC_mode_transfer_v = 2, //usually used
  8827. + DMAC_mode_reserved_v = 3,
  8828. + DMAC_a_b = 4, //
  8829. + DMAC_a_m = 0x00000010, //
  8830. +
  8831. + DMAS_f_b = 0, // finished (sticky)
  8832. + DMAS_f_m = 0x00000001, //
  8833. + DMAS_d_b = 1, // done (sticky)
  8834. + DMAS_d_m = 0x00000002, //
  8835. + DMAS_c_b = 2, // chain (sticky)
  8836. + DMAS_c_m = 0x00000004, //
  8837. + DMAS_e_b = 3, // error (sticky)
  8838. + DMAS_e_m = 0x00000008, //
  8839. + DMAS_h_b = 4, // halt (sticky)
  8840. + DMAS_h_m = 0x00000010, //
  8841. +
  8842. + DMASM_f_b = 0, // finished (1=mask)
  8843. + DMASM_f_m = 0x00000001, //
  8844. + DMASM_d_b = 1, // done (1=mask)
  8845. + DMASM_d_m = 0x00000002, //
  8846. + DMASM_c_b = 2, // chain (1=mask)
  8847. + DMASM_c_m = 0x00000004, //
  8848. + DMASM_e_b = 3, // error (1=mask)
  8849. + DMASM_e_m = 0x00000008, //
  8850. + DMASM_h_b = 4, // halt (1=mask)
  8851. + DMASM_h_m = 0x00000010, //
  8852. +} ;
  8853. +
  8854. +/*
  8855. + * DMA channel definitions
  8856. + */
  8857. +
  8858. +enum
  8859. +{
  8860. + DMACH_extToMem0 = 0,
  8861. + DMACH_memToExt0 = 0,
  8862. + DMACH_extToMem1 = 1,
  8863. + DMACH_memToExt1 = 1,
  8864. + DMACH_ethRcv0 = 2,
  8865. + DMACH_ethXmt0 = 3,
  8866. + DMACH_ethRcv1 = 4,
  8867. + DMACH_ethXmt2 = 5,
  8868. + DMACH_memToFifo = 6,
  8869. + DMACH_fifoToMem = 7,
  8870. + DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
  8871. + DMACH_pciToMem = 8,
  8872. + DMACH_memToPci = 9,
  8873. + DMACH_securityInput = 10,
  8874. + DMACH_securityOutput = 11,
  8875. + DMACH_rng_se = 12, //randomNumberGenerator on SE
  8876. +
  8877. + DMACH_count //must be last
  8878. +};
  8879. +
  8880. +
  8881. +typedef struct DMAC_s
  8882. +{
  8883. + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
  8884. +} volatile *DMA_t ;
  8885. +
  8886. +
  8887. +/*
  8888. + * External DMA parameters
  8889. +*/
  8890. +
  8891. +enum
  8892. +{
  8893. + DMADEVCMD_ts_b = 0, // ts field in devcmd
  8894. + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
  8895. + DMADEVCMD_ts_byte_v = 0,
  8896. + DMADEVCMD_ts_halfword_v = 1,
  8897. + DMADEVCMD_ts_word_v = 2,
  8898. + DMADEVCMD_ts_2word_v = 3,
  8899. + DMADEVCMD_ts_4word_v = 4,
  8900. + DMADEVCMD_ts_6word_v = 5,
  8901. + DMADEVCMD_ts_8word_v = 6,
  8902. + DMADEVCMD_ts_16word_v = 7
  8903. +};
  8904. +
  8905. +
  8906. +#if 1 // aws - Compatibility.
  8907. +# define EXTDMA_ts_b DMADEVCMD_ts_b
  8908. +# define EXTDMA_ts_m DMADEVCMD_ts_m
  8909. +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
  8910. +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
  8911. +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
  8912. +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
  8913. +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
  8914. +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
  8915. +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
  8916. +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
  8917. +#endif // aws - Compatibility.
  8918. +
  8919. +#endif //__IDT_RC32438_DMA_H__
  8920. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
  8921. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 1969-12-31 19:00:00.000000000 -0500
  8922. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 2007-09-20 00:16:52.000000000 -0400
  8923. @@ -0,0 +1,82 @@
  8924. +/**************************************************************************
  8925. + *
  8926. + * BRIEF MODULE DESCRIPTION
  8927. + * DMA operations for IDT RC32438.
  8928. + *
  8929. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  8930. + *
  8931. + * This program is free software; you can redistribute it and/or modify it
  8932. + * under the terms of the GNU General Public License as published by the
  8933. + * Free Software Foundation; either version 2 of the License, or (at your
  8934. + * option) any later version.
  8935. + *
  8936. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  8937. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  8938. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  8939. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  8940. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  8941. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  8942. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  8943. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  8944. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  8945. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  8946. + *
  8947. + * You should have received a copy of the GNU General Public License along
  8948. + * with this program; if not, write to the Free Software Foundation, Inc.,
  8949. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  8950. + *
  8951. + *
  8952. + **************************************************************************
  8953. + * May 2004 P. Sadik.
  8954. + *
  8955. + * Initial Release
  8956. + *
  8957. + *
  8958. + *
  8959. + **************************************************************************
  8960. + */
  8961. +
  8962. +#ifndef __IDT_RC32438_DMA_V_H__
  8963. +#define __IDT_RC32438_DMA_V_H__
  8964. +#include <asm/idt-boards/rc32438/rc32438_dma.h>
  8965. +
  8966. +#define DMA_CHAN_OFFSET 0x14
  8967. +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
  8968. +#define DMA_COUNT(count) \
  8969. + ((count) & DMAD_count_m)
  8970. +
  8971. +#define DMA_HALT_TIMEOUT 500
  8972. +
  8973. +
  8974. +static inline int rc32438_halt_dma(DMA_Chan_t ch)
  8975. +{
  8976. + int timeout=1;
  8977. + if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
  8978. + rc32438_writel(0, &ch->dmac);
  8979. +
  8980. + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
  8981. + if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
  8982. + rc32438_writel(0, &ch->dmas);
  8983. + break;
  8984. + }
  8985. + }
  8986. +
  8987. + }
  8988. +
  8989. + return timeout ? 0 : 1;
  8990. +}
  8991. +
  8992. +
  8993. +
  8994. +
  8995. +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
  8996. +{
  8997. + rc32438_writel(0, &ch->dmandptr);
  8998. + rc32438_writel(dma_addr, &ch->dmadptr);
  8999. +}
  9000. +
  9001. +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
  9002. +{
  9003. + rc32438_writel(dma_addr, &ch->dmandptr);
  9004. +}
  9005. +#endif //__IDT_RC32438_DMA_V_H__
  9006. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
  9007. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 1969-12-31 19:00:00.000000000 -0500
  9008. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2007-09-20 00:16:52.000000000 -0400
  9009. @@ -0,0 +1,328 @@
  9010. +/**************************************************************************
  9011. + *
  9012. + * BRIEF MODULE DESCRIPTION
  9013. + * Definitions for IDT EB438 ethernet
  9014. + *
  9015. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  9016. + *
  9017. + * This program is free software; you can redistribute it and/or modify it
  9018. + * under the terms of the GNU General Public License as published by the
  9019. + * Free Software Foundation; either version 2 of the License, or (at your
  9020. + * option) any later version.
  9021. + *
  9022. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  9023. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  9024. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  9025. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  9026. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  9027. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  9028. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  9029. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  9030. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  9031. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  9032. + *
  9033. + * You should have received a copy of the GNU General Public License along
  9034. + * with this program; if not, write to the Free Software Foundation, Inc.,
  9035. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  9036. + *
  9037. + *
  9038. + **************************************************************************
  9039. + * May 2004 P. Sadik.
  9040. + *
  9041. + * Initial Release
  9042. + *
  9043. + *
  9044. + *
  9045. + **************************************************************************
  9046. + */
  9047. +
  9048. +#ifndef __IDT_RC32438_ETH_H__
  9049. +#define __IDT_RC32438_ETH_H__
  9050. +enum
  9051. +{
  9052. + ETH0_PhysicalAddress = 0x18058000,
  9053. + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
  9054. +
  9055. + ETH0_VirtualAddress = 0xb8058000,
  9056. + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
  9057. + ETH1_PhysicalAddress = 0x18060000,
  9058. + ETH1_VirtualAddress = 0xb8060000, // Default
  9059. +} ;
  9060. +
  9061. +typedef struct
  9062. +{
  9063. + u32 ethintfc ;
  9064. + u32 ethfifott ;
  9065. + u32 etharc ;
  9066. + u32 ethhash0 ;
  9067. + u32 ethhash1 ;
  9068. + u32 ethu0 [4] ; // Reserved.
  9069. + u32 ethpfs ;
  9070. + u32 ethmcp ;
  9071. + u32 eth_u1 [10] ; // Reserved.
  9072. + u32 ethspare ;
  9073. + u32 eth_u2 [42] ; // Reserved.
  9074. + u32 ethsal0 ;
  9075. + u32 ethsah0 ;
  9076. + u32 ethsal1 ;
  9077. + u32 ethsah1 ;
  9078. + u32 ethsal2 ;
  9079. + u32 ethsah2 ;
  9080. + u32 ethsal3 ;
  9081. + u32 ethsah3 ;
  9082. + u32 ethrbc ;
  9083. + u32 ethrpc ;
  9084. + u32 ethrupc ;
  9085. + u32 ethrfc ;
  9086. + u32 ethtbc ;
  9087. + u32 ethgpf ;
  9088. + u32 eth_u9 [50] ; // Reserved.
  9089. + u32 ethmac1 ;
  9090. + u32 ethmac2 ;
  9091. + u32 ethipgt ;
  9092. + u32 ethipgr ;
  9093. + u32 ethclrt ;
  9094. + u32 ethmaxf ;
  9095. + u32 eth_u10 ; // Reserved.
  9096. + u32 ethmtest ;
  9097. + u32 miimcfg ;
  9098. + u32 miimcmd ;
  9099. + u32 miimaddr ;
  9100. + u32 miimwtd ;
  9101. + u32 miimrdd ;
  9102. + u32 miimind ;
  9103. + u32 eth_u11 ; // Reserved.
  9104. + u32 eth_u12 ; // Reserved.
  9105. + u32 ethcfsa0 ;
  9106. + u32 ethcfsa1 ;
  9107. + u32 ethcfsa2 ;
  9108. +} volatile *ETH_t;
  9109. +
  9110. +enum
  9111. +{
  9112. + ETHINTFC_en_b = 0,
  9113. + ETHINTFC_en_m = 0x00000001,
  9114. + ETHINTFC_its_b = 1,
  9115. + ETHINTFC_its_m = 0x00000002,
  9116. + ETHINTFC_rip_b = 2,
  9117. + ETHINTFC_rip_m = 0x00000004,
  9118. + ETHINTFC_jam_b = 3,
  9119. + ETHINTFC_jam_m = 0x00000008,
  9120. + ETHINTFC_ovr_b = 4,
  9121. + ETHINTFC_ovr_m = 0x00000010,
  9122. + ETHINTFC_und_b = 5,
  9123. + ETHINTFC_und_m = 0x00000020,
  9124. +
  9125. + ETHFIFOTT_tth_b = 0,
  9126. + ETHFIFOTT_tth_m = 0x0000007f,
  9127. +
  9128. + ETHARC_pro_b = 0,
  9129. + ETHARC_pro_m = 0x00000001,
  9130. + ETHARC_am_b = 1,
  9131. + ETHARC_am_m = 0x00000002,
  9132. + ETHARC_afm_b = 2,
  9133. + ETHARC_afm_m = 0x00000004,
  9134. + ETHARC_ab_b = 3,
  9135. + ETHARC_ab_m = 0x00000008,
  9136. +
  9137. + ETHSAL_byte5_b = 0,
  9138. + ETHSAL_byte5_m = 0x000000ff,
  9139. + ETHSAL_byte4_b = 8,
  9140. + ETHSAL_byte4_m = 0x0000ff00,
  9141. + ETHSAL_byte3_b = 16,
  9142. + ETHSAL_byte3_m = 0x00ff0000,
  9143. + ETHSAL_byte2_b = 24,
  9144. + ETHSAL_byte2_m = 0xff000000,
  9145. +
  9146. + ETHSAH_byte1_b = 0,
  9147. + ETHSAH_byte1_m = 0x000000ff,
  9148. + ETHSAH_byte0_b = 8,
  9149. + ETHSAH_byte0_m = 0x0000ff00,
  9150. +
  9151. + ETHGPF_ptv_b = 0,
  9152. + ETHGPF_ptv_m = 0x0000ffff,
  9153. +
  9154. + ETHPFS_pfd_b = 0,
  9155. + ETHPFS_pfd_m = 0x00000001,
  9156. +
  9157. + ETHCFSA0_cfsa4_b = 0,
  9158. + ETHCFSA0_cfsa4_m = 0x000000ff,
  9159. + ETHCFSA0_cfsa5_b = 8,
  9160. + ETHCFSA0_cfsa5_m = 0x0000ff00,
  9161. +
  9162. + ETHCFSA1_cfsa2_b = 0,
  9163. + ETHCFSA1_cfsa2_m = 0x000000ff,
  9164. + ETHCFSA1_cfsa3_b = 8,
  9165. + ETHCFSA1_cfsa3_m = 0x0000ff00,
  9166. +
  9167. + ETHCFSA2_cfsa0_b = 0,
  9168. + ETHCFSA2_cfsa0_m = 0x000000ff,
  9169. + ETHCFSA2_cfsa1_b = 8,
  9170. + ETHCFSA2_cfsa1_m = 0x0000ff00,
  9171. +
  9172. + ETHMAC1_re_b = 0,
  9173. + ETHMAC1_re_m = 0x00000001,
  9174. + ETHMAC1_paf_b = 1,
  9175. + ETHMAC1_paf_m = 0x00000002,
  9176. + ETHMAC1_rfc_b = 2,
  9177. + ETHMAC1_rfc_m = 0x00000004,
  9178. + ETHMAC1_tfc_b = 3,
  9179. + ETHMAC1_tfc_m = 0x00000008,
  9180. + ETHMAC1_lb_b = 4,
  9181. + ETHMAC1_lb_m = 0x00000010,
  9182. + ETHMAC1_mr_b = 31,
  9183. + ETHMAC1_mr_m = 0x80000000,
  9184. +
  9185. + ETHMAC2_fd_b = 0,
  9186. + ETHMAC2_fd_m = 0x00000001,
  9187. + ETHMAC2_flc_b = 1,
  9188. + ETHMAC2_flc_m = 0x00000002,
  9189. + ETHMAC2_hfe_b = 2,
  9190. + ETHMAC2_hfe_m = 0x00000004,
  9191. + ETHMAC2_dc_b = 3,
  9192. + ETHMAC2_dc_m = 0x00000008,
  9193. + ETHMAC2_cen_b = 4,
  9194. + ETHMAC2_cen_m = 0x00000010,
  9195. + ETHMAC2_pe_b = 5,
  9196. + ETHMAC2_pe_m = 0x00000020,
  9197. + ETHMAC2_vpe_b = 6,
  9198. + ETHMAC2_vpe_m = 0x00000040,
  9199. + ETHMAC2_ape_b = 7,
  9200. + ETHMAC2_ape_m = 0x00000080,
  9201. + ETHMAC2_ppe_b = 8,
  9202. + ETHMAC2_ppe_m = 0x00000100,
  9203. + ETHMAC2_lpe_b = 9,
  9204. + ETHMAC2_lpe_m = 0x00000200,
  9205. + ETHMAC2_nb_b = 12,
  9206. + ETHMAC2_nb_m = 0x00001000,
  9207. + ETHMAC2_bp_b = 13,
  9208. + ETHMAC2_bp_m = 0x00002000,
  9209. + ETHMAC2_ed_b = 14,
  9210. + ETHMAC2_ed_m = 0x00004000,
  9211. +
  9212. + ETHIPGT_ipgt_b = 0,
  9213. + ETHIPGT_ipgt_m = 0x0000007f,
  9214. +
  9215. + ETHIPGR_ipgr2_b = 0,
  9216. + ETHIPGR_ipgr2_m = 0x0000007f,
  9217. + ETHIPGR_ipgr1_b = 8,
  9218. + ETHIPGR_ipgr1_m = 0x00007f00,
  9219. +
  9220. + ETHCLRT_maxret_b = 0,
  9221. + ETHCLRT_maxret_m = 0x0000000f,
  9222. + ETHCLRT_colwin_b = 8,
  9223. + ETHCLRT_colwin_m = 0x00003f00,
  9224. +
  9225. + ETHMAXF_maxf_b = 0,
  9226. + ETHMAXF_maxf_m = 0x0000ffff,
  9227. +
  9228. + ETHMTEST_tb_b = 2,
  9229. + ETHMTEST_tb_m = 0x00000004,
  9230. +
  9231. + ETHMCP_div_b = 0,
  9232. + ETHMCP_div_m = 0x000000ff,
  9233. +
  9234. + MIIMCFG_rsv_b = 0,
  9235. + MIIMCFG_rsv_m = 0x0000000c,
  9236. +
  9237. + MIIMCMD_rd_b = 0,
  9238. + MIIMCMD_rd_m = 0x00000001,
  9239. + MIIMCMD_scn_b = 1,
  9240. + MIIMCMD_scn_m = 0x00000002,
  9241. +
  9242. + MIIMADDR_regaddr_b = 0,
  9243. + MIIMADDR_regaddr_m = 0x0000001f,
  9244. + MIIMADDR_phyaddr_b = 8,
  9245. + MIIMADDR_phyaddr_m = 0x00001f00,
  9246. +
  9247. + MIIMWTD_wdata_b = 0,
  9248. + MIIMWTD_wdata_m = 0x0000ffff,
  9249. +
  9250. + MIIMRDD_rdata_b = 0,
  9251. + MIIMRDD_rdata_m = 0x0000ffff,
  9252. +
  9253. + MIIMIND_bsy_b = 0,
  9254. + MIIMIND_bsy_m = 0x00000001,
  9255. + MIIMIND_scn_b = 1,
  9256. + MIIMIND_scn_m = 0x00000002,
  9257. + MIIMIND_nv_b = 2,
  9258. + MIIMIND_nv_m = 0x00000004,
  9259. +
  9260. +} ;
  9261. +
  9262. +/*
  9263. + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
  9264. + */
  9265. +enum
  9266. +{
  9267. + ETHRX_fd_b = 0,
  9268. + ETHRX_fd_m = 0x00000001,
  9269. + ETHRX_ld_b = 1,
  9270. + ETHRX_ld_m = 0x00000002,
  9271. + ETHRX_rok_b = 2,
  9272. + ETHRX_rok_m = 0x00000004,
  9273. + ETHRX_fm_b = 3,
  9274. + ETHRX_fm_m = 0x00000008,
  9275. + ETHRX_mp_b = 4,
  9276. + ETHRX_mp_m = 0x00000010,
  9277. + ETHRX_bp_b = 5,
  9278. + ETHRX_bp_m = 0x00000020,
  9279. + ETHRX_vlt_b = 6,
  9280. + ETHRX_vlt_m = 0x00000040,
  9281. + ETHRX_cf_b = 7,
  9282. + ETHRX_cf_m = 0x00000080,
  9283. + ETHRX_ovr_b = 8,
  9284. + ETHRX_ovr_m = 0x00000100,
  9285. + ETHRX_crc_b = 9,
  9286. + ETHRX_crc_m = 0x00000200,
  9287. + ETHRX_cv_b = 10,
  9288. + ETHRX_cv_m = 0x00000400,
  9289. + ETHRX_db_b = 11,
  9290. + ETHRX_db_m = 0x00000800,
  9291. + ETHRX_le_b = 12,
  9292. + ETHRX_le_m = 0x00001000,
  9293. + ETHRX_lor_b = 13,
  9294. + ETHRX_lor_m = 0x00002000,
  9295. + ETHRX_ces_b = 14,
  9296. + ETHRX_ces_m = 0x00004000,
  9297. + ETHRX_length_b = 16,
  9298. + ETHRX_length_m = 0xffff0000,
  9299. +
  9300. + ETHTX_fd_b = 0,
  9301. + ETHTX_fd_m = 0x00000001,
  9302. + ETHTX_ld_b = 1,
  9303. + ETHTX_ld_m = 0x00000002,
  9304. + ETHTX_oen_b = 2,
  9305. + ETHTX_oen_m = 0x00000004,
  9306. + ETHTX_pen_b = 3,
  9307. + ETHTX_pen_m = 0x00000008,
  9308. + ETHTX_cen_b = 4,
  9309. + ETHTX_cen_m = 0x00000010,
  9310. + ETHTX_hen_b = 5,
  9311. + ETHTX_hen_m = 0x00000020,
  9312. + ETHTX_tok_b = 6,
  9313. + ETHTX_tok_m = 0x00000040,
  9314. + ETHTX_mp_b = 7,
  9315. + ETHTX_mp_m = 0x00000080,
  9316. + ETHTX_bp_b = 8,
  9317. + ETHTX_bp_m = 0x00000100,
  9318. + ETHTX_und_b = 9,
  9319. + ETHTX_und_m = 0x00000200,
  9320. + ETHTX_of_b = 10,
  9321. + ETHTX_of_m = 0x00000400,
  9322. + ETHTX_ed_b = 11,
  9323. + ETHTX_ed_m = 0x00000800,
  9324. + ETHTX_ec_b = 12,
  9325. + ETHTX_ec_m = 0x00001000,
  9326. + ETHTX_lc_b = 13,
  9327. + ETHTX_lc_m = 0x00002000,
  9328. + ETHTX_td_b = 14,
  9329. + ETHTX_td_m = 0x00004000,
  9330. + ETHTX_crc_b = 15,
  9331. + ETHTX_crc_m = 0x00008000,
  9332. + ETHTX_le_b = 16,
  9333. + ETHTX_le_m = 0x00010000,
  9334. + ETHTX_cc_b = 17,
  9335. + ETHTX_cc_m = 0x001E0000,
  9336. +} ;
  9337. +#endif //__IDT_RC32438_ETH_H__
  9338. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
  9339. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 1969-12-31 19:00:00.000000000 -0500
  9340. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 2007-09-20 00:16:52.000000000 -0400
  9341. @@ -0,0 +1,72 @@
  9342. +/**************************************************************************
  9343. + *
  9344. + * BRIEF MODULE DESCRIPTION
  9345. + * macros for IDT EB438 ethernet
  9346. + *
  9347. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  9348. + *
  9349. + * This program is free software; you can redistribute it and/or modify it
  9350. + * under the terms of the GNU General Public License as published by the
  9351. + * Free Software Foundation; either version 2 of the License, or (at your
  9352. + * option) any later version.
  9353. + *
  9354. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  9355. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  9356. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  9357. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  9358. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  9359. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  9360. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  9361. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  9362. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  9363. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  9364. + *
  9365. + * You should have received a copy of the GNU General Public License along
  9366. + * with this program; if not, write to the Free Software Foundation, Inc.,
  9367. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  9368. + *
  9369. + *
  9370. + **************************************************************************
  9371. + * May 2004 P. Sadik.
  9372. + *
  9373. + * Initial Release
  9374. + *
  9375. + *
  9376. + *
  9377. + **************************************************************************
  9378. + */
  9379. +
  9380. +#ifndef __IDT_RC32438_ETH_V_H__
  9381. +#define __IDT_RC32438_ETH_V_H__
  9382. +#include <asm/idt-boards/rc32438/rc32438_eth.h>
  9383. +
  9384. +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
  9385. +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
  9386. +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
  9387. +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
  9388. +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
  9389. +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
  9390. +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
  9391. +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
  9392. +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
  9393. +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
  9394. +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
  9395. +
  9396. +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
  9397. +
  9398. +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
  9399. +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
  9400. +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
  9401. +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
  9402. +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
  9403. +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
  9404. +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
  9405. +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
  9406. +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
  9407. +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
  9408. +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
  9409. +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
  9410. +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
  9411. +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
  9412. +
  9413. +#endif //__IDT_RC32438_ETH_V_H__
  9414. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
  9415. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 1969-12-31 19:00:00.000000000 -0500
  9416. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 2007-09-20 00:16:52.000000000 -0400
  9417. @@ -0,0 +1,257 @@
  9418. +/**************************************************************************
  9419. + *
  9420. + * BRIEF MODULE DESCRIPTION
  9421. + * Definitions for IDT RC32438 GPIO.
  9422. + *
  9423. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  9424. + *
  9425. + * This program is free software; you can redistribute it and/or modify it
  9426. + * under the terms of the GNU General Public License as published by the
  9427. + * Free Software Foundation; either version 2 of the License, or (at your
  9428. + * option) any later version.
  9429. + *
  9430. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  9431. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  9432. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  9433. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  9434. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  9435. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  9436. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  9437. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  9438. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  9439. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  9440. + *
  9441. + * You should have received a copy of the GNU General Public License along
  9442. + * with this program; if not, write to the Free Software Foundation, Inc.,
  9443. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  9444. + *
  9445. + *
  9446. + **************************************************************************
  9447. + * May 2004 P. Sadik.
  9448. + *
  9449. + * Initial Release
  9450. + *
  9451. + *
  9452. + *
  9453. + **************************************************************************
  9454. + */
  9455. +#ifndef __IDT_RC32438_GPIO_H__
  9456. +#define __IDT_RC32438_GPIO_H__
  9457. +enum
  9458. +{
  9459. + GPIO0_PhysicalAddress = 0x18048000,
  9460. + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
  9461. +
  9462. + GPIO0_VirtualAddress = 0xb8048000,
  9463. + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
  9464. +} ;
  9465. +
  9466. +typedef struct
  9467. +{
  9468. + u32 gpiofunc; /* GPIO Function Register
  9469. + * gpiofunc[x]==0 bit = gpio
  9470. + * func[x]==1 bit = altfunc
  9471. + */
  9472. + u32 gpiocfg; /* GPIO Configuration Register
  9473. + * gpiocfg[x]==0 bit = input
  9474. + * gpiocfg[x]==1 bit = output
  9475. + */
  9476. + u32 gpiod; /* GPIO Data Register
  9477. + * gpiod[x] read/write gpio pinX status
  9478. + */
  9479. + u32 gpioilevel; /* GPIO Interrupt Status Register
  9480. + * interrupt level (see gpioistat)
  9481. + */
  9482. + u32 gpioistat; /* Gpio Interrupt Status Register
  9483. + * istat[x] = (gpiod[x] == level[x])
  9484. + * cleared in ISR (STICKY bits)
  9485. + */
  9486. + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
  9487. +} volatile * GPIO_t ;
  9488. +
  9489. +typedef enum
  9490. +{
  9491. + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
  9492. + GPIO_alt_v = 1, // gpiofunc use pin as alt.
  9493. + GPIO_input_v = 0, // gpiocfg use pin as input.
  9494. + GPIO_output_v = 1, // gpiocfg use pin as output.
  9495. + GPIO_pin0_b = 0,
  9496. + GPIO_pin0_m = 0x00000001,
  9497. + GPIO_pin1_b = 1,
  9498. + GPIO_pin1_m = 0x00000002,
  9499. + GPIO_pin2_b = 2,
  9500. + GPIO_pin2_m = 0x00000004,
  9501. + GPIO_pin3_b = 3,
  9502. + GPIO_pin3_m = 0x00000008,
  9503. + GPIO_pin4_b = 4,
  9504. + GPIO_pin4_m = 0x00000010,
  9505. + GPIO_pin5_b = 5,
  9506. + GPIO_pin5_m = 0x00000020,
  9507. + GPIO_pin6_b = 6,
  9508. + GPIO_pin6_m = 0x00000040,
  9509. + GPIO_pin7_b = 7,
  9510. + GPIO_pin7_m = 0x00000080,
  9511. + GPIO_pin8_b = 8,
  9512. + GPIO_pin8_m = 0x00000100,
  9513. + GPIO_pin9_b = 9,
  9514. + GPIO_pin9_m = 0x00000200,
  9515. + GPIO_pin10_b = 10,
  9516. + GPIO_pin10_m = 0x00000400,
  9517. + GPIO_pin11_b = 11,
  9518. + GPIO_pin11_m = 0x00000800,
  9519. + GPIO_pin12_b = 12,
  9520. + GPIO_pin12_m = 0x00001000,
  9521. + GPIO_pin13_b = 13,
  9522. + GPIO_pin13_m = 0x00002000,
  9523. + GPIO_pin14_b = 14,
  9524. + GPIO_pin14_m = 0x00004000,
  9525. + GPIO_pin15_b = 15,
  9526. + GPIO_pin15_m = 0x00008000,
  9527. + GPIO_pin16_b = 16,
  9528. + GPIO_pin16_m = 0x00010000,
  9529. + GPIO_pin17_b = 17,
  9530. + GPIO_pin17_m = 0x00020000,
  9531. + GPIO_pin18_b = 18,
  9532. + GPIO_pin18_m = 0x00040000,
  9533. + GPIO_pin19_b = 19,
  9534. + GPIO_pin19_m = 0x00080000,
  9535. + GPIO_pin20_b = 20,
  9536. + GPIO_pin20_m = 0x00100000,
  9537. + GPIO_pin21_b = 21,
  9538. + GPIO_pin21_m = 0x00200000,
  9539. + GPIO_pin22_b = 22,
  9540. + GPIO_pin22_m = 0x00400000,
  9541. + GPIO_pin23_b = 23,
  9542. + GPIO_pin23_m = 0x00800000,
  9543. + GPIO_pin24_b = 24,
  9544. + GPIO_pin24_m = 0x01000000,
  9545. + GPIO_pin25_b = 25,
  9546. + GPIO_pin25_m = 0x02000000,
  9547. + GPIO_pin26_b = 26,
  9548. + GPIO_pin26_m = 0x04000000,
  9549. + GPIO_pin27_b = 27,
  9550. + GPIO_pin27_m = 0x08000000,
  9551. + GPIO_pin28_b = 28,
  9552. + GPIO_pin28_m = 0x10000000,
  9553. + GPIO_pin29_b = 29,
  9554. + GPIO_pin29_m = 0x20000000,
  9555. + GPIO_pin30_b = 30,
  9556. + GPIO_pin30_m = 0x40000000,
  9557. + GPIO_pin31_b = 31,
  9558. + GPIO_pin31_m = 0x80000000,
  9559. +
  9560. +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
  9561. +
  9562. + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
  9563. + GPIO_u0sout_m = GPIO_pin0_m,
  9564. + GPIO_u0sout_cfg_v = GPIO_output_v,
  9565. + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
  9566. + GPIO_u0sinp_m = GPIO_pin1_m,
  9567. + GPIO_u0sinp_cfg_v = GPIO_input_v,
  9568. + GPIO_u0rin_b = GPIO_pin2_b, // UART 0 ring indic.
  9569. + GPIO_u0rin_m = GPIO_pin2_m,
  9570. + GPIO_u0rin_cfg_v = GPIO_input_v,
  9571. + GPIO_u0dcdn_b = GPIO_pin3_b, // UART 0 data carr.det.
  9572. + GPIO_u0dcdn_m = GPIO_pin3_m,
  9573. + GPIO_u0dcdn_cfg_v = GPIO_input_v,
  9574. + GPIO_u0dtrn_b = GPIO_pin4_b, // UART 0 data term rdy.
  9575. + GPIO_u0dtrn_m = GPIO_pin4_m,
  9576. + GPIO_u0dtrn_cfg_v = GPIO_output_v,
  9577. + GPIO_u0dsrn_b = GPIO_pin5_b, // UART 0 data set rdy.
  9578. + GPIO_u0dsrn_m = GPIO_pin5_m,
  9579. + GPIO_u0dsrn_cfg_v = GPIO_input_v,
  9580. + GPIO_u0rtsn_b = GPIO_pin6_b, // UART 0 req. to send.
  9581. + GPIO_u0rtsn_m = GPIO_pin6_m,
  9582. + GPIO_u0rtsn_cfg_v = GPIO_output_v,
  9583. + GPIO_u0ctsn_b = GPIO_pin7_b, // UART 0 clear to send.
  9584. + GPIO_u0ctsn_m = GPIO_pin7_m,
  9585. + GPIO_u0ctsn_cfg_v = GPIO_input_v,
  9586. +
  9587. + GPIO_u1sout_b = GPIO_pin8_b, // UART 1 serial out.
  9588. + GPIO_u1sout_m = GPIO_pin8_m,
  9589. + GPIO_u1sout_cfg_v = GPIO_output_v,
  9590. + GPIO_u1sinp_b = GPIO_pin9_b, // UART 1 serial in.
  9591. + GPIO_u1sinp_m = GPIO_pin9_m,
  9592. + GPIO_u1sinp_cfg_v = GPIO_input_v,
  9593. + GPIO_u1dtrn_b = GPIO_pin10_b, // UART 1 data term rdy.
  9594. + GPIO_u1dtrn_m = GPIO_pin10_m,
  9595. + GPIO_u1dtrn_cfg_v = GPIO_output_v,
  9596. + GPIO_u1dsrn_b = GPIO_pin11_b, // UART 1 data set rdy.
  9597. + GPIO_u1dsrn_m = GPIO_pin11_m,
  9598. + GPIO_u1dsrn_cfg_v = GPIO_input_v,
  9599. + GPIO_u1rtsn_b = GPIO_pin12_b, // UART 1 req. to send.
  9600. + GPIO_u1rtsn_m = GPIO_pin12_m,
  9601. + GPIO_u1rtsn_cfg_v = GPIO_output_v,
  9602. + GPIO_u1ctsn_b = GPIO_pin13_b, // UART 1 clear to send.
  9603. + GPIO_u1ctsn_m = GPIO_pin13_m,
  9604. + GPIO_u1ctsn_cfg_v = GPIO_input_v,
  9605. +
  9606. + GPIO_dmareqn0_b = GPIO_pin14_b, // Ext. DMA 0 request
  9607. + GPIO_dmareqn0_m = GPIO_pin14_m,
  9608. + GPIO_dmareqn0_cfg_v = GPIO_input_v,
  9609. +
  9610. + GPIO_dmareqn1_b = GPIO_pin15_b, // Ext. DMA 1 request
  9611. + GPIO_dmareqn1_m = GPIO_pin15_m,
  9612. + GPIO_dmareqn1_cfg_v = GPIO_input_v,
  9613. +
  9614. + GPIO_dmadonen0_b = GPIO_pin16_b, // Ext. DMA 0 done
  9615. + GPIO_dmadonen0_m = GPIO_pin16_m,
  9616. + GPIO_dmadonen0_cfg_v = GPIO_input_v,
  9617. +
  9618. + GPIO_dmadonen1_b = GPIO_pin17_b, // Ext. DMA 1 done
  9619. + GPIO_dmadonen1_m = GPIO_pin17_m,
  9620. + GPIO_dmadonen1_cfg_v = GPIO_input_v,
  9621. +
  9622. + GPIO_dmafinn0_b = GPIO_pin18_b, // Ext. DMA 0 finished
  9623. + GPIO_dmafinn0_m = GPIO_pin18_m,
  9624. + GPIO_dmafinn0_cfg_v = GPIO_output_v,
  9625. +
  9626. + GPIO_dmafinn1_b = GPIO_pin19_b, // Ext. DMA 1 finished
  9627. + GPIO_dmafinn1_m = GPIO_pin19_m,
  9628. + GPIO_dmafinn1_cfg_v = GPIO_output_v,
  9629. +
  9630. + GPIO_maddr22_b = GPIO_pin20_b, // M&P bus bit 22.
  9631. + GPIO_maddr22_m = GPIO_pin20_m,
  9632. + GPIO_maddr22_cfg_v = GPIO_output_v,
  9633. +
  9634. + GPIO_maddr23_b = GPIO_pin21_b, // M&P bus bit 23.
  9635. + GPIO_maddr23_m = GPIO_pin21_m,
  9636. + GPIO_maddr23_cfg_v = GPIO_output_v,
  9637. +
  9638. + GPIO_maddr24_b = GPIO_pin22_b, // M&P bus bit 24.
  9639. + GPIO_maddr24_m = GPIO_pin22_m,
  9640. + GPIO_maddr24_cfg_v = GPIO_output_v,
  9641. +
  9642. + GPIO_maddr25_b = GPIO_pin23_b, // M&P bus bit 25.
  9643. + GPIO_maddr25_m = GPIO_pin23_m,
  9644. + GPIO_maddr25_cfg_v = GPIO_output_v,
  9645. +
  9646. + GPIO_afspare6_b = GPIO_pin24_b, // reserved.
  9647. + GPIO_afspare6_m = GPIO_pin24_m,
  9648. + GPIO_afspare6_cfg_v = GPIO_input_v,
  9649. + GPIO_afspare5_b = GPIO_pin25_b, // reserved.
  9650. + GPIO_afspare5_m = GPIO_pin25_m,
  9651. + GPIO_afspare5_cfg_v = GPIO_input_v,
  9652. + GPIO_afspare4_b = GPIO_pin26_b, // reserved.
  9653. + GPIO_afspare4_m = GPIO_pin26_m,
  9654. + GPIO_afspare4_cfg_v = GPIO_input_v,
  9655. + GPIO_afspare3_b = GPIO_pin27_b, // reserved.
  9656. + GPIO_afspare3_m = GPIO_pin27_m,
  9657. + GPIO_afspare3_cfg_v = GPIO_input_v,
  9658. + GPIO_afspare2_b = GPIO_pin28_b, // reserved.
  9659. + GPIO_afspare2_m = GPIO_pin28_m,
  9660. + GPIO_afspare2_cfg_v = GPIO_input_v,
  9661. + GPIO_afspare1_b = GPIO_pin29_b, // reserved.
  9662. + GPIO_afspare1_m = GPIO_pin29_m,
  9663. + GPIO_afspare1_cfg_v = GPIO_input_v,
  9664. +
  9665. + GPIO_pcimuintn_b = GPIO_pin30_b, // PCI messaging int.
  9666. + GPIO_pcimuintn_m = GPIO_pin30_m,
  9667. + GPIO_pcimuintn_cfg_v = GPIO_output_v,
  9668. +
  9669. + GPIO_rngclk_b = GPIO_pin31_b, // RNG external clock
  9670. + GPIO_rngclk_m = GPIO_pin31_m,
  9671. + GPIO_rncclk_cfg_v = GPIO_input_v,
  9672. +} GPIO_DEFS_t;
  9673. +
  9674. +#endif //__IDT_RC32438_GPIO_H__
  9675. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
  9676. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 1969-12-31 19:00:00.000000000 -0500
  9677. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2007-09-20 00:16:52.000000000 -0400
  9678. @@ -0,0 +1,510 @@
  9679. +/**************************************************************************
  9680. + *
  9681. + * BRIEF MODULE DESCRIPTION
  9682. + * Definitions for IDT RC32438 PCI.
  9683. + *
  9684. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  9685. + *
  9686. + * This program is free software; you can redistribute it and/or modify it
  9687. + * under the terms of the GNU General Public License as published by the
  9688. + * Free Software Foundation; either version 2 of the License, or (at your
  9689. + * option) any later version.
  9690. + *
  9691. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  9692. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  9693. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  9694. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  9695. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  9696. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  9697. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  9698. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  9699. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  9700. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  9701. + *
  9702. + * You should have received a copy of the GNU General Public License along
  9703. + * with this program; if not, write to the Free Software Foundation, Inc.,
  9704. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  9705. + *
  9706. + *
  9707. + **************************************************************************
  9708. + * May 2004 P. Sadik
  9709. + *
  9710. + * Initial Release
  9711. + *
  9712. + *
  9713. + *
  9714. + **************************************************************************
  9715. + */
  9716. +
  9717. +enum
  9718. +{
  9719. + PCI0_PhysicalAddress = 0x18080000,
  9720. + PCI_PhysicalAddress = PCI0_PhysicalAddress,
  9721. +
  9722. + PCI0_VirtualAddress = 0xb8080000,
  9723. + PCI_VirtualAddress = PCI0_VirtualAddress,
  9724. +} ;
  9725. +
  9726. +enum
  9727. +{
  9728. + PCI_LbaCount = 4, // Local base addresses.
  9729. +} ;
  9730. +
  9731. +typedef struct
  9732. +{
  9733. + u32 a ; // Address.
  9734. + u32 c ; // Control.
  9735. + u32 m ; // mapping.
  9736. +} PCI_Map_s ;
  9737. +
  9738. +typedef struct
  9739. +{
  9740. + u32 pcic ;
  9741. + u32 pcis ;
  9742. + u32 pcism ;
  9743. + u32 pcicfga ;
  9744. + u32 pcicfgd ;
  9745. + PCI_Map_s pcilba [PCI_LbaCount] ;
  9746. + u32 pcidac ;
  9747. + u32 pcidas ;
  9748. + u32 pcidasm ;
  9749. + u32 pcidad ;
  9750. + u32 pcidma8c ;
  9751. + u32 pcidma9c ;
  9752. + u32 pcitc ;
  9753. +} volatile *PCI_t ;
  9754. +
  9755. +// PCI messaging unit.
  9756. +enum
  9757. +{
  9758. + PCIM_Count = 2,
  9759. +} ;
  9760. +typedef struct
  9761. +{
  9762. + u32 pciim [PCIM_Count] ;
  9763. + u32 pciom [PCIM_Count] ;
  9764. + u32 pciid ;
  9765. + u32 pciiic ;
  9766. + u32 pciiim ;
  9767. + u32 pciiod ;
  9768. + u32 pciioic ;
  9769. + u32 pciioim ;
  9770. +} volatile *PCIM_t ;
  9771. +
  9772. +/*******************************************************************************
  9773. + *
  9774. + * PCI Control Register
  9775. + *
  9776. + ******************************************************************************/
  9777. +enum
  9778. +{
  9779. + PCIC_en_b = 0,
  9780. + PCIC_en_m = 0x00000001,
  9781. + PCIC_tnr_b = 1,
  9782. + PCIC_tnr_m = 0x00000002,
  9783. + PCIC_sce_b = 2,
  9784. + PCIC_sce_m = 0x00000004,
  9785. + PCIC_ien_b = 3,
  9786. + PCIC_ien_m = 0x00000008,
  9787. + PCIC_aaa_b = 4,
  9788. + PCIC_aaa_m = 0x00000010,
  9789. + PCIC_eap_b = 5,
  9790. + PCIC_eap_m = 0x00000020,
  9791. + PCIC_pcim_b = 6,
  9792. + PCIC_pcim_m = 0x000001c0,
  9793. + PCIC_pcim_disabled_v = 0,
  9794. + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
  9795. + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
  9796. + PCIC_pcim_extern_v = 3, // Host - external arbiter.
  9797. + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
  9798. + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
  9799. + PCIC_pcim_reserved6_v = 6,
  9800. + PCIC_pcim_reserved7_v = 7,
  9801. + PCIC_igm_b = 9,
  9802. + PCIC_igm_m = 0x00000200,
  9803. +} ;
  9804. +
  9805. +/*******************************************************************************
  9806. + *
  9807. + * PCI Status Register
  9808. + *
  9809. + ******************************************************************************/
  9810. +enum {
  9811. + PCIS_eed_b = 0,
  9812. + PCIS_eed_m = 0x00000001,
  9813. + PCIS_wr_b = 1,
  9814. + PCIS_wr_m = 0x00000002,
  9815. + PCIS_nmi_b = 2,
  9816. + PCIS_nmi_m = 0x00000004,
  9817. + PCIS_ii_b = 3,
  9818. + PCIS_ii_m = 0x00000008,
  9819. + PCIS_cwe_b = 4,
  9820. + PCIS_cwe_m = 0x00000010,
  9821. + PCIS_cre_b = 5,
  9822. + PCIS_cre_m = 0x00000020,
  9823. + PCIS_mdpe_b = 6,
  9824. + PCIS_mdpe_m = 0x00000040,
  9825. + PCIS_sta_b = 7,
  9826. + PCIS_sta_m = 0x00000080,
  9827. + PCIS_rta_b = 8,
  9828. + PCIS_rta_m = 0x00000100,
  9829. + PCIS_rma_b = 9,
  9830. + PCIS_rma_m = 0x00000200,
  9831. + PCIS_sse_b = 10,
  9832. + PCIS_sse_m = 0x00000400,
  9833. + PCIS_ose_b = 11,
  9834. + PCIS_ose_m = 0x00000800,
  9835. + PCIS_pe_b = 12,
  9836. + PCIS_pe_m = 0x00001000,
  9837. + PCIS_tae_b = 13,
  9838. + PCIS_tae_m = 0x00002000,
  9839. + PCIS_rle_b = 14,
  9840. + PCIS_rle_m = 0x00004000,
  9841. + PCIS_bme_b = 15,
  9842. + PCIS_bme_m = 0x00008000,
  9843. + PCIS_prd_b = 16,
  9844. + PCIS_prd_m = 0x00010000,
  9845. + PCIS_rip_b = 17,
  9846. + PCIS_rip_m = 0x00020000,
  9847. +} ;
  9848. +
  9849. +/*******************************************************************************
  9850. + *
  9851. + * PCI Status Mask Register
  9852. + *
  9853. + ******************************************************************************/
  9854. +enum {
  9855. + PCISM_eed_b = 0,
  9856. + PCISM_eed_m = 0x00000001,
  9857. + PCISM_wr_b = 1,
  9858. + PCISM_wr_m = 0x00000002,
  9859. + PCISM_nmi_b = 2,
  9860. + PCISM_nmi_m = 0x00000004,
  9861. + PCISM_ii_b = 3,
  9862. + PCISM_ii_m = 0x00000008,
  9863. + PCISM_cwe_b = 4,
  9864. + PCISM_cwe_m = 0x00000010,
  9865. + PCISM_cre_b = 5,
  9866. + PCISM_cre_m = 0x00000020,
  9867. + PCISM_mdpe_b = 6,
  9868. + PCISM_mdpe_m = 0x00000040,
  9869. + PCISM_sta_b = 7,
  9870. + PCISM_sta_m = 0x00000080,
  9871. + PCISM_rta_b = 8,
  9872. + PCISM_rta_m = 0x00000100,
  9873. + PCISM_rma_b = 9,
  9874. + PCISM_rma_m = 0x00000200,
  9875. + PCISM_sse_b = 10,
  9876. + PCISM_sse_m = 0x00000400,
  9877. + PCISM_ose_b = 11,
  9878. + PCISM_ose_m = 0x00000800,
  9879. + PCISM_pe_b = 12,
  9880. + PCISM_pe_m = 0x00001000,
  9881. + PCISM_tae_b = 13,
  9882. + PCISM_tae_m = 0x00002000,
  9883. + PCISM_rle_b = 14,
  9884. + PCISM_rle_m = 0x00004000,
  9885. + PCISM_bme_b = 15,
  9886. + PCISM_bme_m = 0x00008000,
  9887. + PCISM_prd_b = 16,
  9888. + PCISM_prd_m = 0x00010000,
  9889. + PCISM_rip_b = 17,
  9890. + PCISM_rip_m = 0x00020000,
  9891. +} ;
  9892. +
  9893. +/*******************************************************************************
  9894. + *
  9895. + * PCI Configuration Address Register
  9896. + *
  9897. + ******************************************************************************/
  9898. +enum {
  9899. + PCICFGA_reg_b = 2,
  9900. + PCICFGA_reg_m = 0x000000fc,
  9901. + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
  9902. + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
  9903. + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
  9904. + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
  9905. + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
  9906. + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
  9907. + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
  9908. + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
  9909. + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
  9910. + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
  9911. + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
  9912. + PCICFGA_reg_pba0m_v = 0x48>>2,
  9913. + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
  9914. + PCICFGA_reg_pba1m_v = 0x50>>2,
  9915. + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
  9916. + PCICFGA_reg_pba2m_v = 0x58>>2,
  9917. + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
  9918. + PCICFGA_reg_pba3m_v = 0x60>>2,
  9919. + PCICFGA_reg_pmgt_v = 0x64>>2,
  9920. + PCICFGA_func_b = 8,
  9921. + PCICFGA_func_m = 0x00000700,
  9922. + PCICFGA_dev_b = 11,
  9923. + PCICFGA_dev_m = 0x0000f800,
  9924. + PCICFGA_dev_internal_v = 0,
  9925. + PCICFGA_bus_b = 16,
  9926. + PCICFGA_bus_m = 0x00ff0000,
  9927. + PCICFGA_bus_type0_v = 0, //local bus
  9928. + PCICFGA_en_b = 31, // read only
  9929. + PCICFGA_en_m = 0x80000000,
  9930. +} ;
  9931. +
  9932. +enum {
  9933. + PCFGID_vendor_b = 0,
  9934. + PCFGID_vendor_m = 0x0000ffff,
  9935. + PCFGID_vendor_IDT_v = 0x111d,
  9936. + PCFGID_device_b = 16,
  9937. + PCFGID_device_m = 0xffff0000,
  9938. + PCFGID_device_Acaciade_v = 0x0207,
  9939. +
  9940. + PCFG04_command_ioena_b = 1,
  9941. + PCFG04_command_ioena_m = 0x00000001,
  9942. + PCFG04_command_memena_b = 2,
  9943. + PCFG04_command_memena_m = 0x00000002,
  9944. + PCFG04_command_bmena_b = 3,
  9945. + PCFG04_command_bmena_m = 0x00000004,
  9946. + PCFG04_command_mwinv_b = 5,
  9947. + PCFG04_command_mwinv_m = 0x00000010,
  9948. + PCFG04_command_parena_b = 7,
  9949. + PCFG04_command_parena_m = 0x00000040,
  9950. + PCFG04_command_serrena_b = 9,
  9951. + PCFG04_command_serrena_m = 0x00000100,
  9952. + PCFG04_command_fastbbena_b = 10,
  9953. + PCFG04_command_fastbbena_m = 0x00000200,
  9954. + PCFG04_status_b = 16,
  9955. + PCFG04_status_m = 0xffff0000,
  9956. + PCFG04_status_66MHz_b = 21, // 66 MHz enable
  9957. + PCFG04_status_66MHz_m = 0x00200000,
  9958. + PCFG04_status_fbb_b = 23,
  9959. + PCFG04_status_fbb_m = 0x00800000,
  9960. + PCFG04_status_mdpe_b = 24,
  9961. + PCFG04_status_mdpe_m = 0x01000000,
  9962. + PCFG04_status_dst_b = 25,
  9963. + PCFG04_status_dst_m = 0x06000000,
  9964. + PCFG04_status_sta_b = 27,
  9965. + PCFG04_status_sta_m = 0x08000000,
  9966. + PCFG04_status_rta_b = 28,
  9967. + PCFG04_status_rta_m = 0x10000000,
  9968. + PCFG04_status_rma_b = 29,
  9969. + PCFG04_status_rma_m = 0x20000000,
  9970. + PCFG04_status_sse_b = 30,
  9971. + PCFG04_status_sse_m = 0x40000000,
  9972. + PCFG04_status_pe_b = 31,
  9973. + PCFG04_status_pe_m = 0x40000000,
  9974. +
  9975. + PCFG08_revId_b = 0,
  9976. + PCFG08_revId_m = 0x000000ff,
  9977. + PCFG08_classCode_b = 0,
  9978. + PCFG08_classCode_m = 0xffffff00,
  9979. + PCFG08_classCode_bridge_v = 06,
  9980. + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
  9981. + PCFG0C_cacheline_b = 0,
  9982. + PCFG0C_cacheline_m = 0x000000ff,
  9983. + PCFG0C_masterLatency_b = 8,
  9984. + PCFG0C_masterLatency_m = 0x0000ff00,
  9985. + PCFG0C_headerType_b = 16,
  9986. + PCFG0C_headerType_m = 0x00ff0000,
  9987. + PCFG0C_bist_b = 24,
  9988. + PCFG0C_bist_m = 0xff000000,
  9989. +
  9990. + PCIPBA_msi_b = 0,
  9991. + PCIPBA_msi_m = 0x00000001,
  9992. + PCIPBA_p_b = 3,
  9993. + PCIPBA_p_m = 0x00000004,
  9994. + PCIPBA_baddr_b = 8,
  9995. + PCIPBA_baddr_m = 0xffffff00,
  9996. +
  9997. + PCFGSS_vendorId_b = 0,
  9998. + PCFGSS_vendorId_m = 0x0000ffff,
  9999. + PCFGSS_id_b = 16,
  10000. + PCFGSS_id_m = 0xffff0000,
  10001. +
  10002. + PCFG3C_interruptLine_b = 0,
  10003. + PCFG3C_interruptLine_m = 0x000000ff,
  10004. + PCFG3C_interruptPin_b = 8,
  10005. + PCFG3C_interruptPin_m = 0x0000ff00,
  10006. + PCFG3C_minGrant_b = 16,
  10007. + PCFG3C_minGrant_m = 0x00ff0000,
  10008. + PCFG3C_maxLat_b = 24,
  10009. + PCFG3C_maxLat_m = 0xff000000,
  10010. +
  10011. + PCIPBAC_msi_b = 0,
  10012. + PCIPBAC_msi_m = 0x00000001,
  10013. + PCIPBAC_p_b = 1,
  10014. + PCIPBAC_p_m = 0x00000002,
  10015. + PCIPBAC_size_b = 2,
  10016. + PCIPBAC_size_m = 0x0000007c,
  10017. + PCIPBAC_sb_b = 7,
  10018. + PCIPBAC_sb_m = 0x00000080,
  10019. + PCIPBAC_pp_b = 8,
  10020. + PCIPBAC_pp_m = 0x00000100,
  10021. + PCIPBAC_mr_b = 9,
  10022. + PCIPBAC_mr_m = 0x00000600,
  10023. + PCIPBAC_mr_read_v =0, //no prefetching
  10024. + PCIPBAC_mr_readLine_v =1,
  10025. + PCIPBAC_mr_readMult_v =2,
  10026. + PCIPBAC_mrl_b = 11,
  10027. + PCIPBAC_mrl_m = 0x00000800,
  10028. + PCIPBAC_mrm_b = 12,
  10029. + PCIPBAC_mrm_m = 0x00001000,
  10030. + PCIPBAC_trp_b = 13,
  10031. + PCIPBAC_trp_m = 0x00002000,
  10032. +
  10033. + PCFG40_trdyTimeout_b = 0,
  10034. + PCFG40_trdyTimeout_m = 0x000000ff,
  10035. + PCFG40_retryLim_b = 8,
  10036. + PCFG40_retryLim_m = 0x0000ff00,
  10037. +};
  10038. +
  10039. +/*******************************************************************************
  10040. + *
  10041. + * PCI Local Base Address [0|1|2|3] Register
  10042. + *
  10043. + ******************************************************************************/
  10044. +enum {
  10045. + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
  10046. + PCILBA_baddr_m = 0xffffff00,
  10047. +} ;
  10048. +/*******************************************************************************
  10049. + *
  10050. + * PCI Local Base Address Control Register
  10051. + *
  10052. + ******************************************************************************/
  10053. +enum {
  10054. + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
  10055. + PCILBAC_msi_m = 0x00000001,
  10056. + PCILBAC_msi_mem_v = 0,
  10057. + PCILBAC_msi_io_v = 1,
  10058. + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
  10059. + PCILBAC_size_m = 0x0000007c,
  10060. + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
  10061. + PCILBAC_sb_m = 0x00000080,
  10062. + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
  10063. + PCILBAC_rt_m = 0x00000100,
  10064. + PCILBAC_rt_noprefetch_v = 0, // mem read
  10065. + PCILBAC_rt_prefetch_v = 1, // mem readline
  10066. +} ;
  10067. +
  10068. +/*******************************************************************************
  10069. + *
  10070. + * PCI Local Base Address [0|1|2|3] Mapping Register
  10071. + *
  10072. + ******************************************************************************/
  10073. +enum {
  10074. + PCILBAM_maddr_b = 8,
  10075. + PCILBAM_maddr_m = 0xffffff00,
  10076. +} ;
  10077. +
  10078. +/*******************************************************************************
  10079. + *
  10080. + * PCI Decoupled Access Control Register
  10081. + *
  10082. + ******************************************************************************/
  10083. +enum {
  10084. + PCIDAC_den_b = 0,
  10085. + PCIDAC_den_m = 0x00000001,
  10086. +} ;
  10087. +
  10088. +/*******************************************************************************
  10089. + *
  10090. + * PCI Decoupled Access Status Register
  10091. + *
  10092. + ******************************************************************************/
  10093. +enum {
  10094. + PCIDAS_d_b = 0,
  10095. + PCIDAS_d_m = 0x00000001,
  10096. + PCIDAS_b_b = 1,
  10097. + PCIDAS_b_m = 0x00000002,
  10098. + PCIDAS_e_b = 2,
  10099. + PCIDAS_e_m = 0x00000004,
  10100. + PCIDAS_ofe_b = 3,
  10101. + PCIDAS_ofe_m = 0x00000008,
  10102. + PCIDAS_off_b = 4,
  10103. + PCIDAS_off_m = 0x00000010,
  10104. + PCIDAS_ife_b = 5,
  10105. + PCIDAS_ife_m = 0x00000020,
  10106. + PCIDAS_iff_b = 6,
  10107. + PCIDAS_iff_m = 0x00000040,
  10108. +} ;
  10109. +
  10110. +/*******************************************************************************
  10111. + *
  10112. + * PCI DMA Channel 8 Configuration Register
  10113. + *
  10114. + ******************************************************************************/
  10115. +enum
  10116. +{
  10117. + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
  10118. + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
  10119. + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
  10120. + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
  10121. +} ;
  10122. +
  10123. +/*******************************************************************************
  10124. + *
  10125. + * PCI DMA Channel 9 Configuration Register
  10126. + *
  10127. + ******************************************************************************/
  10128. +enum
  10129. +{
  10130. + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
  10131. + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
  10132. +} ;
  10133. +
  10134. +/*******************************************************************************
  10135. + *
  10136. + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
  10137. + *
  10138. + ******************************************************************************/
  10139. +enum {
  10140. + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
  10141. + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
  10142. + // These are for reads (DMA channel 8)
  10143. + PCIDMAD_devcmd_mr_v = 0, //memory read
  10144. + PCIDMAD_devcmd_mrl_v = 1, //memory read line
  10145. + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
  10146. + PCIDMAD_devcmd_ior_v = 3, //I/O read
  10147. + // These are for writes (DMA channel 9)
  10148. + PCIDMAD_devcmd_mw_v = 0, //memory write
  10149. + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
  10150. + PCIDMAD_devcmd_iow_v = 3, //I/O write
  10151. +
  10152. + // Swap byte field applies to both DMA channel 8 and 9
  10153. + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
  10154. + PCIDMAD_sb_m = 0x01000000, // swap byte field
  10155. +} ;
  10156. +
  10157. +
  10158. +/*******************************************************************************
  10159. + *
  10160. + * PCI Target Control Register
  10161. + *
  10162. + ******************************************************************************/
  10163. +enum
  10164. +{
  10165. + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
  10166. + PCITC_rtimer_m = 0x000000ff,
  10167. + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
  10168. + PCITC_dtimer_m = 0x0000ff00,
  10169. + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
  10170. + PCITC_rdr_m = 0x00040000,
  10171. + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
  10172. + PCITC_ddt_m = 0x00080000,
  10173. +} ;
  10174. +/*******************************************************************************
  10175. + *
  10176. + * PCI messaging unit [applies to both inbound and outbound registers ]
  10177. + *
  10178. + ******************************************************************************/
  10179. +enum
  10180. +{
  10181. + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
  10182. + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
  10183. + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
  10184. + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
  10185. + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
  10186. + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
  10187. +};
  10188. +
  10189. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
  10190. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 1969-12-31 19:00:00.000000000 -0500
  10191. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 2007-09-20 00:16:52.000000000 -0400
  10192. @@ -0,0 +1,190 @@
  10193. +/**************************************************************************
  10194. + *
  10195. + * BRIEF MODULE DESCRIPTION
  10196. + * Definitions for IDT RC32438 PCI setup.
  10197. + *
  10198. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  10199. + *
  10200. + * This program is free software; you can redistribute it and/or modify it
  10201. + * under the terms of the GNU General Public License as published by the
  10202. + * Free Software Foundation; either version 2 of the License, or (at your
  10203. + * option) any later version.
  10204. + *
  10205. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  10206. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  10207. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  10208. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  10209. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  10210. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  10211. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  10212. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  10213. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  10214. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  10215. + *
  10216. + * You should have received a copy of the GNU General Public License along
  10217. + * with this program; if not, write to the Free Software Foundation, Inc.,
  10218. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  10219. + *
  10220. + *
  10221. + **************************************************************************
  10222. + * May 2004 P. Sadik
  10223. + *
  10224. + * Initial Release
  10225. + *
  10226. + *
  10227. + *
  10228. + **************************************************************************
  10229. + */
  10230. +
  10231. +#define PCI_MSG_VirtualAddress 0xB8088010
  10232. +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
  10233. +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
  10234. +
  10235. +#define PCIM_SHFT 0x6
  10236. +#define PCIM_BIT_LEN 0x7
  10237. +#define PCIM_H_EA 0x3
  10238. +#define PCIM_H_IA_FIX 0x4
  10239. +#define PCIM_H_IA_RR 0x5
  10240. +
  10241. +#define PCI_ADDR_START 0x50000000
  10242. +
  10243. +#define CPUTOPCI_MEM_WIN 0x02000000
  10244. +#define CPUTOPCI_IO_WIN 0x00100000
  10245. +#define PCILBA_SIZE_SHFT 2
  10246. +#define PCILBA_SIZE_MASK 0x1F
  10247. +#define SIZE_256MB 0x1C
  10248. +#define SIZE_128MB 0x1B
  10249. +#define SIZE_64MB 0x1A
  10250. +#define SIZE_32MB 0x19
  10251. +#define SIZE_16MB 0x18
  10252. +#define SIZE_4MB 0x16
  10253. +#define SIZE_2MB 0x15
  10254. +#define SIZE_1MB 0x14
  10255. +#define ACACIA_CONFIG0_ADDR 0x80000000
  10256. +#define ACACIA_CONFIG1_ADDR 0x80000004
  10257. +#define ACACIA_CONFIG2_ADDR 0x80000008
  10258. +#define ACACIA_CONFIG3_ADDR 0x8000000C
  10259. +#define ACACIA_CONFIG4_ADDR 0x80000010
  10260. +#define ACACIA_CONFIG5_ADDR 0x80000014
  10261. +#define ACACIA_CONFIG6_ADDR 0x80000018
  10262. +#define ACACIA_CONFIG7_ADDR 0x8000001C
  10263. +#define ACACIA_CONFIG8_ADDR 0x80000020
  10264. +#define ACACIA_CONFIG9_ADDR 0x80000024
  10265. +#define ACACIA_CONFIG10_ADDR 0x80000028
  10266. +#define ACACIA_CONFIG11_ADDR 0x8000002C
  10267. +#define ACACIA_CONFIG12_ADDR 0x80000030
  10268. +#define ACACIA_CONFIG13_ADDR 0x80000034
  10269. +#define ACACIA_CONFIG14_ADDR 0x80000038
  10270. +#define ACACIA_CONFIG15_ADDR 0x8000003C
  10271. +#define ACACIA_CONFIG16_ADDR 0x80000040
  10272. +#define ACACIA_CONFIG17_ADDR 0x80000044
  10273. +#define ACACIA_CONFIG18_ADDR 0x80000048
  10274. +#define ACACIA_CONFIG19_ADDR 0x8000004C
  10275. +#define ACACIA_CONFIG20_ADDR 0x80000050
  10276. +#define ACACIA_CONFIG21_ADDR 0x80000054
  10277. +#define ACACIA_CONFIG22_ADDR 0x80000058
  10278. +#define ACACIA_CONFIG23_ADDR 0x8000005C
  10279. +#define ACACIA_CONFIG24_ADDR 0x80000060
  10280. +#define ACACIA_CONFIG25_ADDR 0x80000064
  10281. +#define ACACIA_CMD (PCFG04_command_ioena_m | \
  10282. + PCFG04_command_memena_m | \
  10283. + PCFG04_command_bmena_m | \
  10284. + PCFG04_command_mwinv_m | \
  10285. + PCFG04_command_parena_m | \
  10286. + PCFG04_command_serrena_m )
  10287. +
  10288. +#define ACACIA_STAT (PCFG04_status_mdpe_m | \
  10289. + PCFG04_status_sta_m | \
  10290. + PCFG04_status_rta_m | \
  10291. + PCFG04_status_rma_m | \
  10292. + PCFG04_status_sse_m | \
  10293. + PCFG04_status_pe_m)
  10294. +
  10295. +#define ACACIA_CNFG1 ((ACACIA_STAT<<16)|ACACIA_CMD)
  10296. +
  10297. +#define ACACIA_REVID 0
  10298. +#define ACACIA_CLASS_CODE 0
  10299. +#define ACACIA_CNFG2 ((ACACIA_CLASS_CODE<<8) | \
  10300. + ACACIA_REVID)
  10301. +
  10302. +#define ACACIA_CACHE_LINE_SIZE 4
  10303. +#define ACACIA_MASTER_LAT 0x3c
  10304. +#define ACACIA_HEADER_TYPE 0
  10305. +#define ACACIA_BIST 0
  10306. +
  10307. +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
  10308. + (ACACIA_HEADER_TYPE<<16) | \
  10309. + (ACACIA_MASTER_LAT<<8) | \
  10310. + ACACIA_CACHE_LINE_SIZE )
  10311. +
  10312. +#define ACACIA_BAR0 0x00000008 /* 128 MB Memory */
  10313. +#define ACACIA_BAR1 0x18800001 /* 1 MB IO */
  10314. +#define ACACIA_BAR2 0x18000001 /* 2 MB IO window for Acacia
  10315. + internal Registers */
  10316. +#define ACACIA_BAR3 0x48000008 /* Spare 128 MB Memory */
  10317. +
  10318. +#define ACACIA_CNFG4 ACACIA_BAR0
  10319. +#define ACACIA_CNFG5 ACACIA_BAR1
  10320. +#define ACACIA_CNFG6 ACACIA_BAR2
  10321. +#define ACACIA_CNFG7 ACACIA_BAR3
  10322. +
  10323. +#define ACACIA_SUBSYS_VENDOR_ID 0
  10324. +#define ACACIA_SUBSYSTEM_ID 0
  10325. +#define ACACIA_CNFG8 0
  10326. +#define ACACIA_CNFG9 0
  10327. +#define ACACIA_CNFG10 0
  10328. +#define ACACIA_CNFG11 ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
  10329. + ACACIA_SUBSYSTEM_ID)
  10330. +#define ACACIA_INT_LINE 1
  10331. +#define ACACIA_INT_PIN 1
  10332. +#define ACACIA_MIN_GNT 8
  10333. +#define ACACIA_MAX_LAT 0x38
  10334. +#define ACACIA_CNFG12 0
  10335. +#define ACACIA_CNFG13 0
  10336. +#define ACACIA_CNFG14 0
  10337. +#define ACACIA_CNFG15 ((ACACIA_MAX_LAT<<24) | \
  10338. + (ACACIA_MIN_GNT<<16) | \
  10339. + (ACACIA_INT_PIN<<8) | \
  10340. + ACACIA_INT_LINE)
  10341. +#define ACACIA_RETRY_LIMIT 0x80
  10342. +#define ACACIA_TRDY_LIMIT 0x80
  10343. +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
  10344. + ACACIA_TRDY_LIMIT)
  10345. +#define PCI_PBAxC_R 0x0
  10346. +#define PCI_PBAxC_RL 0x1
  10347. +#define PCI_PBAxC_RM 0x2
  10348. +#define SIZE_SHFT 2
  10349. +
  10350. +#define ACACIA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
  10351. + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
  10352. + PCIPBAC_pp_m | \
  10353. + (SIZE_128MB<<SIZE_SHFT) | \
  10354. + PCIPBAC_p_m)
  10355. +
  10356. +#define ACACIA_CNFG17 ACACIA_PBA0C
  10357. +#define ACACIA_PBA0M 0x0
  10358. +#define ACACIA_CNFG18 ACACIA_PBA0M
  10359. +
  10360. +#define ACACIA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
  10361. + PCIPBAC_msi_m)
  10362. +
  10363. +#define ACACIA_CNFG19 ACACIA_PBA1C
  10364. +#define ACACIA_PBA1M 0x0
  10365. +#define ACACIA_CNFG20 ACACIA_PBA1M
  10366. +
  10367. +#define ACACIA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
  10368. + PCIPBAC_msi_m)
  10369. +
  10370. +#define ACACIA_CNFG21 ACACIA_PBA2C
  10371. +#define ACACIA_PBA2M 0x18000000
  10372. +#define ACACIA_CNFG22 ACACIA_PBA2M
  10373. +#define ACACIA_PBA3C 0
  10374. +#define ACACIA_CNFG23 ACACIA_PBA3C
  10375. +#define ACACIA_PBA3M 0
  10376. +#define ACACIA_CNFG24 ACACIA_PBA3M
  10377. +
  10378. +
  10379. +
  10380. +#define PCITC_DTIMER_VAL 8
  10381. +#define PCITC_RTIMER_VAL 0x10
  10382. +
  10383. diff -Nur linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
  10384. --- linux-2.6.21.5-pristine/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 1969-12-31 19:00:00.000000000 -0500
  10385. +++ linux-2.6.21.5/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 2007-09-20 00:16:52.000000000 -0400
  10386. @@ -0,0 +1,91 @@
  10387. +/**************************************************************************
  10388. + *
  10389. + * BRIEF MODULE DESCRIPTION
  10390. + * Timer register definition IDT RC32438 CPU.
  10391. + *
  10392. + * Copyright 2004 IDT Inc. (rischelp@idt.com)
  10393. + *
  10394. + * This program is free software; you can redistribute it and/or modify it
  10395. + * under the terms of the GNU General Public License as published by the
  10396. + * Free Software Foundation; either version 2 of the License, or (at your
  10397. + * option) any later version.
  10398. + *
  10399. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  10400. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  10401. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  10402. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  10403. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  10404. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  10405. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  10406. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  10407. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  10408. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  10409. + *
  10410. + * You should have received a copy of the GNU General Public License along
  10411. + * with this program; if not, write to the Free Software Foundation, Inc.,
  10412. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  10413. + *
  10414. + *
  10415. + **************************************************************************
  10416. + * May 2004 P. Sadik.
  10417. + *
  10418. + * Initial Release
  10419. + *
  10420. + *
  10421. + *
  10422. + **************************************************************************
  10423. + */
  10424. +
  10425. +#ifndef __IDT_RC32438_TIM_H__
  10426. +#define __IDT_RC32438_TIM_H__
  10427. +
  10428. +enum
  10429. +{
  10430. + TIM0_PhysicalAddress = 0x18028000,
  10431. + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
  10432. +
  10433. + TIM0_VirtualAddress = 0xb8028000,
  10434. + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
  10435. +} ;
  10436. +
  10437. +enum
  10438. +{
  10439. + TIM_Count = 3,
  10440. +} ;
  10441. +
  10442. +struct TIM_CNTR_s
  10443. +{
  10444. + u32 count ;
  10445. + u32 compare ;
  10446. + u32 ctc ; //use CTC_
  10447. +} ;
  10448. +
  10449. +typedef struct TIM_s
  10450. +{
  10451. + struct TIM_CNTR_s tim [TIM_Count] ;
  10452. + u32 rcount ; //use RCOUNT_
  10453. + u32 rcompare ; //use RCOMPARE_
  10454. + u32 rtc ; //use RTC_
  10455. +} volatile * TIM_t ;
  10456. +
  10457. +enum
  10458. +{
  10459. + CTC_en_b = 0,
  10460. + CTC_en_m = 0x00000001,
  10461. + CTC_to_b = 1,
  10462. + CTC_to_m = 0x00000002,
  10463. +
  10464. + RCOUNT_count_b = 0,
  10465. + RCOUNT_count_m = 0x0000ffff,
  10466. + RCOMPARE_compare_b = 0,
  10467. + RCOMPARE_compare_m = 0x0000ffff,
  10468. + RTC_ce_b = 0,
  10469. + RTC_ce_m = 0x00000001,
  10470. + RTC_to_b = 1,
  10471. + RTC_to_m = 0x00000002,
  10472. + RTC_rqe_b = 2,
  10473. + RTC_rqe_m = 0x00000004,
  10474. +
  10475. +} ;
  10476. +#endif //__IDT_RC32438_TIM_H__
  10477. +
  10478. --- a/arch/mips/include/asm/mach-generic/irq.h
  10479. +++ b/arch/mips/include/asm/mach-generic/irq.h
  10480. @@ -9,7 +9,7 @@
  10481. #define __ASM_MACH_GENERIC_IRQ_H
  10482.  
  10483. #ifndef NR_IRQS
  10484. -#define NR_IRQS 128
  10485. +#define NR_IRQS 256
  10486. #endif
  10487.  
  10488. #ifdef CONFIG_I8259
  10489. --- a/include/linux/kernel.h
  10490. +++ b/include/linux/kernel.h
  10491. @@ -672,6 +672,7 @@
  10492. };
  10493.  
  10494. /* Force a compilation error if condition is true */
  10495. +extern void BUILD_BUG(void);
  10496. #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
  10497.  
  10498. /* Force a compilation error if condition is true, but also produce a
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!