$ sudo ./flashrom -p internal --noverify-all --wp-enable -V
flashrom v1.5.0-devel on Linux 6.8.0-38-generic (x86_64)
flashrom is free software, get the source code at https://flashrom.org

flashrom was built with GCC 13.2.0, little endian
Command line (5 args): ./flashrom -p internal --noverify-all --wp-enable -V
Acquiring lock (timeout=180 sec)...
Opened file lock "/run/lock/firmware_utility_lock"
Lock acquired.
Initializing internal programmer
get_mtd_info: device_name: "BIOS", is_writeable: 0, numeraseregions: 0, total_size: 16777216, erasesize: 4096
Cannot open file stream for /dev/mtd0
Found candidate at: 00000500-00000528
Found coreboot table at 0x00000500.
Found candidate at: 00000000-00000548
Found coreboot table at 0x00000000.
coreboot table found at 0x7aa9c000.
coreboot header(24) checksum: 89a2 table(1328) checksum: df52 entries: 45
Vendor ID: Google, part ID: Caroline
Using Internal DMI decoder.
DMI string chassis-type: "Laptop"
Laptop detected via DMI.
DMI string system-manufacturer: "Google"
DMI string system-product-name: "Caroline"
DMI string system-version: "1.0"
DMI string baseboard-manufacturer: "Google"
DMI string baseboard-product-name: "Caroline"
DMI string baseboard-version: "1.0"
Found chipset "Intel Skylake Y Premium" with PCI ID 8086:9d46.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with it,
then please email a report to [email protected] including a verbose (-V) log.
Thank you!
Enabling flash write... Using libpci PCI_ACCESS_I386_TYPE1
BIOS_SPI_BC = 0x8b: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI)
Top Swap: not enabled
SPI Read Configuration: prefetching enabled, caching enabled,
BIOS_CNTL = 0x8b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled
Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed.
New value is 0x8b.
SPIBAR = 0x000070a6566a9000 (phys = 0xfe010000)
0x04: 0xf800 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=1, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=1
SPI Configuration is locked down.
Reading OPCODES... done
0x06: 0x020c (HSFC)
HSFC: FGO=0, FCYCLE=6, WET=0, FDBC=2, SME=0
0x0c: 0x00001f00 (DLOCK)
DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0,
       PR0_LOCKDN=1, PR1_LOCKDN=1, PR2_LOCKDN=1, PR3_LOCKDN=1, PR4_LOCKDN=1,
       SSEQ_LOCKDN=0
0x50: 0x00004acb (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x4a, BRRA 0xcb
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
0x58: 0x0fff0200 FREG1: BIOS region (0x00200000-0x00ffffff) is read-write.
0x5C: 0x01ff0001 FREG2: Management Engine region (0x00001000-0x001fffff) is locked.
Not all flash regions are freely accessible by flashrom. This is most likely
due to an active ME. Please see https://flashrom.org/ME for details.
At least some flash regions are read protected. You have to use a flash
layout and include only accessible regions. For write operations, you'll
additionally need the --noverify-all switch. See manpage for more details.
0xa0: 0x80 (SSFS)
SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
0xa1: 0xfe0000 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6
0xa4: 0x5006 (PREOP)
0xa6: 0xb32d (OPTYPE)
0xa8: 0x05030201 (OPMENU)
0xac: 0x0bd89f20 (OPMENU+4)
0xc4: 0xf3d82004 (LVSCC)
LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xc8: 0x00002000 (UVSCC)
UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20
Enabling hardware sequencing by default for 100+ series PCH.
OK.
The following protocols are supported: Programmer-specific.
Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB.
HSFC: FGO=1, FCYCLE=6, WET=0, FDBC=2, SME=0
Chip identified: GD25Q127C/GD25Q128E
Added layout entry 00000000 - 00ffffff named complete flash
Found GigaDevice flash chip "GD25Q127C/GD25Q128E" (16384 kB, Programmer-specific) on internal.
Found GigaDevice flash chip "GD25Q127C/GD25Q128E" (16384 kB, Programmer-specific).
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
ich_hwseq_read_status: only supports STATUS1
wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00.
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
ich_hwseq_read_status: only supports STATUS1
wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00.
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
ich_hwseq_read_status: only supports STATUS1
wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00.
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
ich_hwseq_read_status: only supports STATUS1
wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00.
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
ich_hwseq_read_status: only supports STATUS1
wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00.
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
ich_hwseq_read_status: only supports STATUS1
wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00.
Reading Status register
HSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0
Writing status register
HSFC: FGO=1, FCYCLE=7, WET=0, FDBC=0, SME=0
Transaction error between offset 0x00000001 and 0x00000001 (= 0x00000001 + 0)!
HSFS: FDONE=1, FCERR=1, AEL=0, SCIP=0, PRR34_LOCKDN=1, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=1
HSFC: FGO=0, FCYCLE=7, WET=0, FDBC=0, SME=0
Writing Status register failed
!!Failed to apply new WP settings: failed to write the new WP configuration
Restoring PCI config space for 00:1f:5 reg 0xdc