module zadanko(
    input [7:0] SW,
    input [2:0] KEY,
    output [9:0] LEDR,
    output [0:6] HEX0,HEX1,HEX2,HEX3);
    wire [3:0] AH,AL,SH,SL;

    assign LEDR[7:0] = SW;
    assign {AH,AL} = SW;

    add_sub_N_bits  #(8)    ex(SW,KEY[2],KEY[1],KEY[0],{SH,SL},LEDR[8],LEDR[9]);

    decoder_hex_16 d3(AH,HEX3);
    decoder_hex_16 d2(AL,HEX2);
    decoder_hex_16 d1(SH,HEX1);
    decoder_hex_16 d0(SL,HEX0);
endmodule


module register_N_bits
    #(N=8)
    (input [N-1:0] D,
    input clk,
    output reg [N-1:0] Q);

    always @(posedge clk)
        Q <= D;
endmodule

module adder_N_bits
    #(parameter N=8)
    (input [N-1:0] A,B,
    input cin,
    output [N-1:0] S,
    output cout);

    assign {cout,S} = A + B + cin;

endmodule


module FFD_posedge(
    input D,clk,
    output reg Q);

    always @(posedge clk)
        Q <= D;
endmodule

module accumulator_N_bits_struct
    #(N=8)
    (input [N-1:0] A,
    input clk,
    output [N-1:0] S,
    output overflow, carry);

    (* keep *) wire [N-1:0] B,C;
    (* keep *) wire cout,over;

    register_N_bits #(8) ex_A(A,clk,B);

    adder_N_bits #(8) ex_add(B,S,1'b0,C,cout);

    register_N_bits #(8) ex_S(C,clk,S);
    FFD_posedge ex_cout(cout,clk,carry);
    assign over = cout ^ C[N-1];
    FFD_posedge ex_over(over,clk,overflow);
endmodule

module accumulator_N_bits_always_aclr
    #(N=8)
    (input [N-1:0] A,
    input clk,aclr,
    output reg [N-1:0] S,
    output reg overflow,carry);
    reg [N-1:0] B;

    always @(posedge clk, negedge aclr)
        if (!aclr)          B <= {N{1'b0}};
        else            B <= A;
    always @(posedge clk, negedge aclr)
        if (!aclr)          {carry,S} <= {(N+1){1'b0}};
        else            {carry,S} <= B + S;
    always @(posedge clk, negedge aclr)
        if (!aclr)          overflow <= 1'b0;
        else            overflow <= carry ^ S[N-1];
endmodule

// zadanie 2

module add_sub_N_bits
    #(N=8)
    (input [N-1:0] A,
    input add_sub,
    input clk,aclr,
    output reg [N-1:0] S,
    output reg overflow,carry);
    reg [N-1:0] B;
    always @(posedge clk, negedge aclr)
        if (aclr)      B <= {N{1'b0}};
        else        B <= A;
    always @(posedge clk, negedge aclr)
        if (aclr)      {carry,S} <= {(N+1){1'b0}};
        else if (add_sub)   {carry,S} <= S + B;
        else        {carry,S} <= S - B;
    always @(posedge clk, negedge aclr)
        if (aclr)      overflow <= 1'b0;
        else        overflow <= carry ^ S[N-1];
endmodule


module decoder_hex_16(
    input [3:0] liczba,
    output reg [0:6] H);
    always @(*)
        case (liczba)
            0: H = 7'b0000001;
            1: H = 7'b1001111;
            2: H = 7'b0010010;
            3: H = 7'b0000110;
            4: H = 7'b1001100;
            5: H = 7'b0100100;
            6: H = 7'b0100000;
            7: H = 7'b0001111;
            8: H = 7'b0000000;
            9: H = 7'b0000100;
            10: H = 7'b0001000;
            11: H = 7'b1100000;
            12: H = 7'b0110001;
            13: H = 7'b1000010;
            14: H = 7'b0110000;
            15: H = 7'b0111000;
            default: H = 7'b1111111;
            endcase
endmodule

// zadanie 3

module array_multiplier_4x4 (
	output [7:0] z,
	input [3:0] a, b);

	wire [2:0] c1,c2,c3,c4;
	wire [2:0] s1,s2,s3;
	wire [3:0] P0,P1,P2,P3;
	// Partial Product Generation
	PP pp1 (P3, P2, P1, P0, a, b);
	// Partial Product Reduction
	ha HA1_2 (c1[2],s1[2],P1[2],P0[3]);
	ha HA1_1 (c1[1],s1[1],P1[1],P0[2]);
	ha HA1_0 (c1[0],s1[0],P1[0],P0[1]);
	fa FA2_2 (c2[2],s2[2],P2[2],P1[3],c1[2]);
	fa FA2_1 (c2[1],s2[1],P2[1],s1[2],c1[1]);
	fa FA2_0 (c2[0],s2[0],P2[0],s1[1],c1[0]);
	fa FA3_2 (c3[2],s3[2],P3[2],P2[3],c2[2]);
	fa FA3_1 (c3[1],s3[1],P3[1],s2[2],c2[1]);
	fa FA3_0 (c3[0],s3[0],P3[0],s2[1],c2[0]);

	// Generate lower product bits
	assign z[0] = P0[0];
	assign z[1] = s1[0];
	assign z[2] = s2[0];
	assign z[3] = s3[0];

	// Final Carry Propagate Addition (CPA)
	ha CPA1 (c4[0],z[4],c3[0],s3[1]);
	fa CPA2 (c4[1],z[5],c3[1],c4[0],s3[2]);
	fa CPA3 (z[7], z[6], c3[2], c4[1], P3[3]);
endmodule

// zadanie 4

module multiplier_4_bits(
	input [3:0] a,b,
	output [7:0] p);

	wire [3:0] m[3:0];
	wire [3:0] s[1:3];
	wire cout[1:3];

	assign m[0] = a & {4{b[0]}};
	assign m[1] = a & {4{b[1]}};
	assign m[2] = a & {4{b[2]}};
	assign m[3] = a & {4{b[3]}};

	adder_N_bits #(4) ex1({1'b0,m[0][3:1]},m[1],1'b0,s[1],cout[1]);
	adder_N_bits #(4) ex2({cout[1],s[1][3:1]},m[2],1'b0,s[2],cout[2]);
	adder_N_bits #(4) ex3({cout[2],s[2][3:1]},m[3],1'b0,s[3],cout[3]);

	assign p[0] = m[0][0];
	assign p[1] = s[1][0];
	assign p[2] = s[2][0];
	assign p[6:3] = s[3];
	assign p[7] = cout[3];
endmodule

module PP (	// Partial Product Generation
	output	[3:0] P3, P2, P1, P0,
	input 	[3:0] a,b);
	and pp1(P0[3], a[3], b[0]);
	and pp2(P0[2], a[2], b[0]);
	and pp3(P0[1], a[1], b[0]);
	and pp4(P0[0], a[0], b[0]);
	and pp5(P1[3], a[3], b[1]);
	and pp6(P1[2], a[2], b[1]);
	and pp7(P1[1], a[1], b[1]);
	and pp8(P1[0], a[0], b[1]);
	and pp9(P2[3], a[3], b[2]);
	and pp10(P2[2], a[2], b[2]);
	and pp11(P2[1], a[1], b[2]);
	and pp12(P2[0], a[0], b[2]);
	and pp13(P3[3], a[3], b[3]);
	and pp14(P3[2], a[2], b[3]);
	and pp15(P3[1], a[1], b[3]);
	and pp16(P3[0], a[0], b[3]);
endmodule

module ha(
	output sout,cout,
	input a,b
);

	assign sout=a^b;
	assign cout=(a&b);
endmodule

module fa(sout,cout,a,b,cin);
	output sout,cout;
	input a,b,cin;

	assign sout=(a^b^cin);
	assign cout=((a&b)|(a&cin)|(b&cin));
endmodule

// zadanie 5

module multiply4bits(product,inp1,inp2);
	output [7:0]product;
	input [3:0]inp1;
	input [3:0]inp2;

	assign product[0]=(inp1[0]&inp2[0]);

	wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;

	ha HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
	fa FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
	fa FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
	ha HA2(x6,x7,(inp1[1]&inp2[3]),x5);
	ha HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
	fa FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
	fa FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
	fa FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
	ha HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
	fa FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
	fa FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
	fa FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule