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- MACRO-80 3.44 09-Dec-81 PAGE 1
- ;****************************
- ;* *
- ;* Serial servo interface *
- ;* *
- ;****************************
- ; Z80-A CPU
- ; CY=250 ns
- ; /no ram use/
- ;PHERIPHERIALS&CONTROLS
- ;======================
- ;8255
- 1000 APORT EQU 1000H ;io data bus buffer
- 1001 BPORT EQU 1001H ;input: b0=SD
- ; b1=SCCLK
- 0000 LAPORT EQU 0 ;aport low byte
- 1002 CPORT EQU 1002H ;output:b0=NSD
- 1003 CREG EQU 1003H ;command register
- 1002 SREG EQU CPORT ;status register
- ;b0..b2 =PC0..2
- ;b3 =INTR A not used
- ;b4 =INTE 2 not used
- ;b5 =IBF A
- ;b6 =INTE 1 not used
- ;b7 =NOBF A
- 00C2 CW EQU 0C2H ;mode 2
- ;B group mode 0
- ;PB input
- ;PC 0..2 output
- 0003 SCLK0 EQU 3 ;SET SCLK=0
- 0002 SCLK1 EQU 2 ;SET SCLK=1
- 0001 SD0 EQU 1 ;SET SD=0&MASK
- 0000 SD1 EQU 0 ;SET SD=1
- 0001 SDMSK EQU 1 ;SD MASK
- 00FF ACK EQU 0FFH ;ACK TO CPU
- 000E DEL50 EQU 14 ;50uS DELAY
- SSCLK MACRO XXX
- EX DE,HL
- LD (HL),XXX
- EX DE,HL
- ENDM
- ORG 0
- 0000' F3 SERIAL: DI
- 0001' 21 1003 LD HL,CREG
- 0004' 36 C2 LD (HL),CW;init. 8255
- 0006' ED 56 IM 1 ;restart 38h
- 0008' 21 1001 LD HL,BPORT
- 000B' 11 1003 LD DE,CREG
- SSCLK SCLK1 ;force SCLK=1
- 000E' EB + EX DE,HL
- 000F' 36 02 + LD (HL),SCLK1
- 0011' EB + EX DE,HL
- MACRO-80 3.44 09-Dec-81 PAGE 1-1
- SSCLK SD1 ;SD=1
- 0012' EB + EX DE,HL
- 0013' 36 00 + LD (HL),SD1
- 0015' EB + EX DE,HL
- 0016' 3A 1000 LD A,(APORT);clear APORT interrupt
- 0019' CB 56 NEN: BIT 2,(HL) ;SERVO ENABLE=HIGH?
- 001B' 28 FC JR Z,NEN
- 001D' 06 20 LD B,20H ;servo reset executing
- 001F' 00 INI0: NOP
- 0020' 10 FD DJNZ INI0
- U 0022' C3 0000 JP MAIN00
- ORG 38H ;RST 7 INPUT FROM CPU
- ;HL=BPORT
- ;DE=CREG
- 0038' A7 AND A ;RE-TEST SD=0
- U 0039' CA 0000 JP Z,REC ;SD LOW
- SSCLK SCLK0 ;SET SCLK=0
- 003C' EB + EX DE,HL
- 003D' 36 03 + LD (HL),SCLK0
- 003F' EB + EX DE,HL
- 0040' 2D DEC L ;HL=APORT
- 0041' 4E LD C,(HL) ;FIRST BYTE TO C
- 0042' EB EX DE,HL ;CREG TO HL mod
- 0043' 2D DEC L ;POINT SREG *
- 0044' CB 7E OFULL: BIT 7,(HL) ;NOBF A *
- 0046' 28 FC JR Z,OFULL ;WAIT WHILE READING LAST OUTPUT *
- 0048' 2C INC L ;POINT CREG *
- 0049' EB EX DE,HL ;APORT TO HL mod
- 004A' 36 FF LD (HL),ACK;ACK TO CPU
- 004C' 2C INC L ;HL=BPORT
- 004D' CB 46 WD10: BIT 0,(HL) ;SD=0?
- 004F' 20 FC JR NZ,WD10
- U 0051' 06 00 LD B,STBL/100H
- 0053' 0A LD A,(BC) ;LENGTH FROM STBL
- 0054' 07 RLCA
- 0055' 07 RLCA
- 0056' 07 RLCA
- 0057' 47 LD B,A ;BIT COUNT
- SSCLK SCLK1 ;SET SCLK=1
- 0058' EB + EX DE,HL
- 0059' 36 02 + LD (HL),SCLK1
- 005B' EB + EX DE,HL
- 005C' CB 46 WD01: BIT 0,(HL) ;SD=1 ?
- 005E' 28 FC JR Z,WD01
- U 0060' C3 0000 JP TRANS
- 0063' 2D TRANS0: DEC L ;HL=APORT
- 0064' 4E LD C,(HL) ;load new data
- 0065' 71 LD (HL),C ;ack
- 0066' 2C INC L ;HL=BPORT
- 0067' AF TRANS: XOR A ;A=0&CLEAR FLAGS
- 0068' CB 19 RR C ;BIT TO CY
- 006A' 3F CCF ;NEG DATA
- 006B' 17 RLA ;BIT TO A/b0
- 006C' 12 LD (DE),A ;SET DATA
- 006D' CB 4E W102: BIT 1,(HL) ;SCLK=0 ?
- MACRO-80 3.44 09-Dec-81 PAGE 1-2
- 006F' 20 FC JR NZ,W102
- 0071' 05 DEC B
- 0072' 3E 07 LD A,7
- 0074' A0 AND B ;MOD 8
- U 0075' 20 00 JR NZ,RTRANS
- 0077' CB 4E W012: BIT 1,(HL) ;SCLK=1 ?;
- 0079' 28 FC JR Z,W012
- 007B' B0 OR B
- 007C' C2 0063' JP NZ,TRANS0
- U 007F' C3 0000 JP ARET
- 0082' CB 4E RTRANS: BIT 1,(HL) ;SCLK=1?
- 0084' 28 FC JR Z,RTRANS
- 0086' C3 0067' JP TRANS
- 0089' CB 4E ARET: BIT 1,(HL) ;SCLK=1?
- 008B' 28 FC JR Z,ARET
- SSCLK SD1 ;SD=1
- 008D' EB + EX DE,HL
- 008E' 36 00 + LD (HL),SD1
- 0090' EB + EX DE,HL
- U 0091' 31 0000 MAIN00: LD SP,STACKP ;return address=main0
- 0094' 11 1003 LD DE,CREG
- 0097' 3E 01 LD A,SDMSK
- 0099' FB EI
- 009A' A6 MAIN: AND (HL) ;SD=0?
- 009B' 20 FD JR NZ,MAIN
- 009D' F3 DI ;disable INPUT interrupt
- 009E' 06 02 REC: LD B,2 ;hold=20us
- 00A0' 10 FE REC1: DJNZ REC1
- 00A2' 06 0E LD B,DEL50
- SSCLK SCLK0 ;SET SCLK=0
- 00A4' EB + EX DE,HL
- 00A5' 36 03 + LD (HL),SCLK0
- 00A7' EB + EX DE,HL
- 00A8' 10 FE K00: DJNZ K00 ;~50us delay
- 00AA' CB 46 WD011: BIT 0,(HL) ;SD=1?
- 00AC' 28 FC JR Z,WD011
- SSCLK SCLK1 ;set SCLK=1
- 00AE' EB + EX DE,HL
- 00AF' 36 02 + LD (HL),SCLK1
- 00B1' EB + EX DE,HL
- U 00B2' 01 0080 LD BC,RECTBL+80H
- 00B5' 1E 00 LD E,LAPORT
- 00B7' CB 4E W100: BIT 1,(HL) ;SCLK=0?
- 00B9' 20 FC JR NZ,W100
- 00BB' CB 4E W010: BIT 1,(HL) ;SCLK=1?
- 00BD' 28 FC JR Z,W010
- 00BF' 7E LD A,(HL) ;data in b0
- 00C0' 1F RRA ;data in CY
- 00C1' CB 19 RR C ;data to b7
- 00C3' 30 F2 JR NC,W100
- 00C5' 79 LD A,C ;data
- MACRO-80 3.44 09-Dec-81 PAGE 1-3
- 00C6' 12 LD (DE),A;output
- 00C7' 0A LD A,(BC) ;command length-1
- 00C8' A7 AND A
- U 00C9' 28 00 JR Z,W1 ;1 byte command
- 00CB' 47 LD B,A ;byte count
- 00CC' 0E 80 W000: LD C,80H ;bit flag
- 00CE' CB 4E W101: BIT 1,(HL) ;SCLK=0?
- 00D0' 20 FC JR NZ,W101
- 00D2' CB 4E W011: BIT 1,(HL) ;SCLK=1?
- 00D4' 28 FC JR Z,W011
- 00D6' 7E LD A,(HL) ;data in b0
- 00D7' 1F RRA ;data in CY
- 00D8' CB 19 RR C ;data to b7
- 00DA' 30 F2 JR NC,W101
- 00DC' 79 LD A,C ;data
- 00DD' 12 LD (DE),A;output
- 00DE' 10 EC DJNZ W000
- 00E0' CB 46 W1: BIT 0,(HL) ;test data line<>0
- 00E2' 28 FC JR Z,W1
- 00E4' C3 0091' JP MAIN00
- ORG 100H
- 0100' 07 07 07 07 RECTBL: DEFB 7,7,7,7,5,2,0,0,0,0,0,0,0,0,0,0 ;00
- 0104' 05 02 00 00
- 0108' 00 00 00 00
- 010C' 00 00 00 00
- 0110' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;10
- 0114' 00 00 00 00
- 0118' 00 00 00 00
- 011C' 00 00 00 00
- 0120' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;20
- 0124' 00 00 00 00
- 0128' 00 00 00 00
- 012C' 00 00 00 00
- 0130' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;30
- 0134' 00 00 00 00
- 0138' 00 00 00 00
- 013C' 00 00 00 00
- 0140' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;40
- 0144' 00 00 00 00
- 0148' 00 00 00 00
- 014C' 00 00 00 00
- 0150' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;50
- 0154' 00 00 00 00
- 0158' 00 00 00 00
- 015C' 00 00 00 00
- 0160' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;60
- 0164' 00 00 00 00
- 0168' 00 00 00 00
- 016C' 00 00 00 00
- 0170' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;70
- 0174' 00 00 00 00
- 0178' 00 00 00 00
- 017C' 00 00 00 00
- 0180' 07 07 07 07 DEFB 7,7,7,7,0,2,0,0,0,0,0,0,0,0,0,0 ;80
- 0184' 00 02 00 00
- 0188' 00 00 00 00
- MACRO-80 3.44 09-Dec-81 PAGE 1-4
- 018C' 00 00 00 00
- 0190' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;90
- 0194' 00 00 00 00
- 0198' 00 00 00 00
- 019C' 00 00 00 00
- 01A0' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;A0
- 01A4' 00 00 00 00
- 01A8' 00 00 00 00
- 01AC' 00 00 00 00
- 01B0' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;B0
- 01B4' 00 00 00 00
- 01B8' 00 00 00 00
- 01BC' 00 00 00 00
- 01C0' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;C0
- 01C4' 00 00 00 00
- 01C8' 00 00 00 00
- 01CC' 00 00 00 00
- 01D0' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;D0
- 01D4' 00 00 00 00
- 01D8' 00 00 00 00
- 01DC' 00 00 00 00
- 01E0' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;E0
- 01E4' 00 00 00 00
- 01E8' 00 00 00 00
- 01EC' 00 00 00 00
- 01F0' 07 07 07 07 DEFB 7,7,7,7,0,0,0,0,0,0,0,0,0,0,0,0 ;F0
- 01F4' 00 00 00 00
- 01F8' 00 00 00 00
- 01FC' 00 00 00 00
- 0200' 00 03 00 00 STBL: DEFB 0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;00
- 0204' 00 00 00 00
- 0208' 00 00 00 00
- 020C' 00 00 00 00
- 0210' 01 04 00 00 DEFB 1,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;10
- 0214' 00 00 00 00
- 0218' 00 00 00 00
- 021C' 00 00 00 00
- 0220' 01 05 00 00 DEFB 1,5,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;20
- 0224' 00 00 00 00
- 0228' 00 00 00 00
- 022C' 00 00 00 00
- 0230' 01 01 00 00 DEFB 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;30
- 0234' 00 00 00 00
- 0238' 00 00 00 00
- 023C' 00 00 00 00
- 0240' 01 04 00 00 DEFB 1,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;40
- 0244' 00 00 00 00
- 0248' 00 00 00 00
- 024C' 00 00 00 00
- 0250' 01 02 00 00 DEFB 1,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;50
- 0254' 00 00 00 00
- 0258' 00 00 00 00
- 025C' 00 00 00 00
- 0260' 01 04 00 00 DEFB 1,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;60
- 0264' 00 00 00 00
- MACRO-80 3.44 09-Dec-81 PAGE 1-5
- 0268' 00 00 00 00
- 026C' 00 00 00 00
- 0270' 01 04 00 00 DEFB 1,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;70
- 0274' 00 00 00 00
- 0278' 00 00 00 00
- 027C' 00 00 00 00
- 0280' 01 02 00 00 DEFB 1,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;80
- 0284' 00 00 00 00
- 0288' 00 00 00 00
- 028C' 00 00 00 00
- 0290' 01 01 00 00 DEFB 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;90
- 0294' 00 00 00 00
- 0298' 00 00 00 00
- 029C' 00 00 00 00
- 02A0' 01 03 00 00 DEFB 1,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;A0
- 02A4' 00 00 00 00
- 02A8' 00 00 00 00
- 02AC' 00 00 00 00
- 02B0' 01 03 02 00 DEFB 1,3,2,0,0,0,0,0,0,0,0,0,0,0,0,0 ;B0
- 02B4' 00 00 00 00
- 02B8' 00 00 00 00
- 02BC' 00 00 00 00
- 02C0' 01 01 02 00 DEFB 1,1,2,0,0,0,0,0,0,0,0,0,0,0,0,0 ;C0
- 02C4' 00 00 00 00
- 02C8' 00 00 00 00
- 02CC' 00 00 00 00
- 02D0' 01 01 02 00 DEFB 1,1,2,0,0,0,0,0,0,0,0,0,0,0,0,0 ;D0
- 02D4' 00 00 00 00
- 02D8' 00 00 00 00
- 02DC' 00 00 00 00
- 02E0' 01 01 02 00 DEFB 1,1,2,0,0,0,0,0,0,0,0,0,0,0,0,0 ;E0
- 02E4' 00 00 00 00
- 02E8' 00 00 00 00
- 02EC' 00 00 00 00
- MACRO-80 3.44 09-Dec-81 PAGE S
- Macros:
- SSCLK
- Symbols:
- 00FF ACK 1000 APORT 0089' ARET
- 1001 BPORT 1002 CPORT 1003 CREG
- 00C2 CW 000E DEL50 001F' INI0
- 00A8' K00 0000 LAPORT 009A' MAIN
- 0091' MAIN00 0019' NEN 0044' OFULL
- 009E' REC 00A0' REC1 0100' RECTBL
- 0082' RTRANS 0003 SCLK0 0002 SCLK1
- 0001 SD0 0000 SD1 0001 SDMSK
- 0000' SERIAL 1002 SREG 0000U STACKP
- 0200' STBL 0067' TRANS 0063' TRANS0
- 00CC' W000 00BB' W010 00D2' W011
- 0077' W012 00E0' W1 00B7' W100
- 00CE' W101 006D' W102 005C' WD01
- 00AA' WD011 004D' WD10
- 9 Fatal error(s)
- 0002 SCLK1
- 0001 SD0 0000 SD1 0001 SDMSK
- 0000' SE
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