[azl@fedora demo]$ lxsim
INFO:SoC:        __   _ __      _  __
INFO:SoC:       / /  (_) /____ | |/_/
INFO:SoC:      / /__/ / __/ -_)>  <
INFO:SoC:     /____/_/\__/\__/_/|_|
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2021-08-30 12:56:37)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 1.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU overriding rom mapping from 0x0 to 0x0.
INFO:SoC:CPU overriding sram mapping from 0x1000000 to 0x10000000.
INFO:SoC:CPU overriding main_ram mapping from 0x40000000 to 0x40000000.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:RAM main_ram added Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 2.
INFO:SoCCSRHandler:uart CSR allocated at Location 3.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (4)
rom                 : Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False
sram                : Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
main_ram            : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr                 : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (4)
- rom
- sram
- main_ram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (4)
- ctrl           : 0
- identifier_mem : 1
- timer0         : 2
- uart           : 3
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart   : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libcompiler_rt'
 CC       umodsi3.o
 CC       udivsi3.o
 CC       divsi3.o
 CC       modsi3.o
 CC       comparesf2.o
/home/azl/Code/litex/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparesf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
 FNALIAS(__cmpsf2, __lesf2);
 ^~~~~~~
 CC       comparedf2.o
/home/azl/Code/litex/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparedf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
 FNALIAS(__cmpdf2, __ledf2);
 ^~~~~~~
 CC       negsf2.o
 CC       negdf2.o
 CC       addsf3.o
 CC       subsf3.o
 CC       mulsf3.o
 CC       divsf3.o
 CC       lshrdi3.o
 CC       muldi3.o
 CC       divdi3.o
 CC       ashldi3.o
 CC       ashrdi3.o
 CC       udivmoddi4.o
 CC       floatsisf.o
 CC       floatunsisf.o
 CC       fixsfsi.o
 CC       fixdfdi.o
 CC       fixunssfsi.o
 CC       fixunsdfdi.o
 CC       adddf3.o
 CC       subdf3.o
 CC       muldf3.o
 CC       divdf3.o
 CC       floatsidf.o
 CC       floatunsidf.o
 CC       floatdidf.o
 CC       fixdfsi.o
 CC       fixunsdfsi.o
 CC       clzsi2.o
 CC       ctzsi2.o
 CC       udivdi3.o
 CC       umoddi3.o
 CC       moddi3.o
 CC       ucmpdi2.o
 CC       mulsi3.o
 AR       libcompiler_rt.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libcompiler_rt'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libbase'
 CC       crt0.o
 CC       exception.o
 CC       libc.o
 CC       errno.o
 CC       crc16.o
 CC       crc32.o
 CC       console.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       qsort.o
 CC       strtod.o
 CC       spiflash.o
 CC       strcasecmp.o
 CC       i2c.o
 CC       div64.o
 CC       progress.o
 CC       memtest.o
 CC       sim_debug.o
 CC       vsnprintf.o
 AR       libbase.a
 CC       vsnprintf-nofloat.o
 AR       libbase-nofloat.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libbase'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libfatfs'
 CC       ffunicode.o
 CC       ff.o
 AR       libfatfs.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libfatfs'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitespi'
 CC       spiflash.o
 AR       liblitespi.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitespi'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitedram'
 CC       sdram.o
 CC       bist.o
 CC       sdram_dbg.o
 AR       liblitedram.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitedram'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libliteeth'
 CC       udp.o
 CC       tftp.o
 CC       mdio.o
 AR       libliteeth.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libliteeth'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitesdcard'
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitesdcard'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitesata'
 CC       sata.o
 AR       liblitesata.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitesata'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/bios'
 CC       isr.o
 CC       boot-helper.o
 CC       boot.o
 CC       helpers.o
 CC       cmd_bios.o
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       cmd_litesata.o
 CC       main.o
 CC       complete.o
 CC       readline.o
 CC       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 22.25KiB     (17.39%)
RAM usage: 1.62KiB  (20.21%)

make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0x5908).
INFO:SoC:Auto-Resizing ROM rom from 0x20000 to 0x5908.
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libcompiler_rt'
 CC       umodsi3.o
 CC       udivsi3.o
 CC       divsi3.o
 CC       modsi3.o
 CC       comparesf2.o
/home/azl/Code/litex/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparesf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
 FNALIAS(__cmpsf2, __lesf2);
 ^~~~~~~
 CC       comparedf2.o
/home/azl/Code/litex/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparedf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
 FNALIAS(__cmpdf2, __ledf2);
 ^~~~~~~
 CC       negsf2.o
 CC       negdf2.o
 CC       addsf3.o
 CC       subsf3.o
 CC       mulsf3.o
 CC       divsf3.o
 CC       lshrdi3.o
 CC       muldi3.o
 CC       divdi3.o
 CC       ashldi3.o
 CC       ashrdi3.o
 CC       udivmoddi4.o
 CC       floatsisf.o
 CC       floatunsisf.o
 CC       fixsfsi.o
 CC       fixdfdi.o
 CC       fixunssfsi.o
 CC       fixunsdfdi.o
 CC       adddf3.o
 CC       subdf3.o
 CC       muldf3.o
 CC       divdf3.o
 CC       floatsidf.o
 CC       floatunsidf.o
 CC       floatdidf.o
 CC       fixdfsi.o
 CC       fixunsdfsi.o
 CC       clzsi2.o
 CC       ctzsi2.o
 CC       udivdi3.o
 CC       umoddi3.o
 CC       moddi3.o
 CC       ucmpdi2.o
 CC       mulsi3.o
 AR       libcompiler_rt.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libcompiler_rt'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libbase'
 CC       crt0.o
 CC       exception.o
 CC       libc.o
 CC       errno.o
 CC       crc16.o
 CC       crc32.o
 CC       console.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       qsort.o
 CC       strtod.o
 CC       spiflash.o
 CC       strcasecmp.o
 CC       i2c.o
 CC       div64.o
 CC       progress.o
 CC       memtest.o
 CC       sim_debug.o
 CC       vsnprintf.o
 AR       libbase.a
 CC       vsnprintf-nofloat.o
 AR       libbase-nofloat.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libbase'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libfatfs'
 CC       ffunicode.o
 CC       ff.o
 AR       libfatfs.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libfatfs'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitespi'
 CC       spiflash.o
 AR       liblitespi.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitespi'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitedram'
 CC       sdram.o
 CC       bist.o
 CC       sdram_dbg.o
 AR       liblitedram.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitedram'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libliteeth'
 CC       udp.o
 CC       tftp.o
 CC       mdio.o
 AR       libliteeth.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/libliteeth'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitesdcard'
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitesdcard'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitesata'
 CC       sata.o
 AR       liblitesata.a
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/liblitesata'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/bios'
 CC       isr.o
 CC       boot-helper.o
 CC       boot.o
 CC       helpers.o
 CC       cmd_bios.o
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       cmd_litesata.o
 CC       main.o
 CC       complete.o
 CC       readline.o
 CC       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 22.25KiB     (17.39%)
RAM usage: 1.62KiB  (20.21%)

make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/bios'
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/bios'
python3 -m litex.soc.software.memusage bios.elf /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 22.25KiB     (17.39%)
RAM usage: 1.62KiB  (20.21%)

make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0x5908).
INFO:SoC:Auto-Resizing ROM rom from 0x20000 to 0x5908.
ALAIN WAS HEREbuild_sim.sh
Traceback (most recent call last):
  File "/home/azl/.local/bin/lxsim", line 33, in <module>
    sys.exit(load_entry_point('litex', 'console_scripts', 'lxsim')())
  File "/home/azl/Code/litex/litex/litex/tools/litex_sim.py", line 375, in main
    vns = builder.build(
  File "/home/azl/Code/litex/litex/litex/soc/integration/builder.py", line 310, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/azl/Code/litex/litex/litex/soc/integration/soc.py", line 1127, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/azl/Code/litex/litex/litex/build/sim/platform.py", line 54, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/azl/Code/litex/litex/litex/build/sim/verilator.py", line 237, in build
    _compile_sim(build_name, verbose)
  File "/home/azl/Code/litex/litex/litex/build/sim/verilator.py", line 155, in _compile_sim
    raise OSError("Subprocess failed with {}\n{}".format(p.returncode, "\n".join(error_messages)))
OSError: Subprocess failed with 2
make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware'
mkdir -p modules
make -C modules -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/Makefile
make[1]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules'
mkdir -p xgmii_ethernet
make MOD=xgmii_ethernet -C xgmii_ethernet -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile
make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/xgmii_ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/xgmii_ethernet'
cp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so
mkdir -p ethernet
make MOD=ethernet -C ethernet -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/ethernet/Makefile
make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/ethernet'
cp ethernet/ethernet.so ethernet.so
mkdir -p serial2console
make MOD=serial2console -C serial2console -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/serial2console/Makefile
make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/serial2console'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/serial2console'
cp serial2console/serial2console.so serial2console.so
mkdir -p serial2tcp
make MOD=serial2tcp -C serial2tcp -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/serial2tcp/Makefile
make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/serial2tcp'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/serial2tcp'
cp serial2tcp/serial2tcp.so serial2tcp.so
mkdir -p clocker
make MOD=clocker -C clocker -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/clocker/Makefile
make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/clocker'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/clocker'
cp clocker/clocker.so clocker.so
mkdir -p spdeeprom
make MOD=spdeeprom -C spdeeprom -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/spdeeprom/Makefile
make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/spdeeprom'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/spdeeprom'
cp spdeeprom/spdeeprom.so spdeeprom.so
make[1]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules'
mkdir -p /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir
cc -c -ggdb -Wall -O3   -o /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir/libdylib.o /home/azl/Code/litex/litex/litex/build/sim/core/libdylib.c
cc -c -ggdb -Wall -O3   -o /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir/modules.o /home/azl/Code/litex/litex/litex/build/sim/core/modules.c
In file included from /home/azl/Code/litex/litex/litex/build/sim/core/modules.c:6:
In function ‘tinydir_readfile’,
    inlined from ‘litex_sim_load_ext_modules’ at /home/azl/Code/litex/litex/litex/build/sim/core/modules.c:68:14:
/home/azl/Code/litex/litex/litex/build/sim/core/tinydir.h:81:25: warning: ‘strcat’ accessing 4097 or more bytes at offsets 0 and 4096 may overlap 1 byte at offset 4096 [-Wrestrict]
   81 | #define _tinydir_strcat strcat
      |                         ^
/home/azl/Code/litex/litex/litex/build/sim/core/tinydir.h:532:9: note: in expansion of macro ‘_tinydir_strcat’
  532 |         _tinydir_strcat(file->path, file->name);
      |         ^~~~~~~~~~~~~~~
cc -c -ggdb -Wall -O3   -o /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir/pads.o /home/azl/Code/litex/litex/litex/build/sim/core/pads.c
cc -c -ggdb -Wall -O3   -o /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir/parse.o /home/azl/Code/litex/litex/litex/build/sim/core/parse.c
cc -c -ggdb -Wall -O3   -o /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir/sim.o /home/azl/Code/litex/litex/litex/build/sim/core/sim.c
verilator -Wno-fatal -O3 --cc /home/azl/Code/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/sim.v  --top-module sim --exe \
    -DPRINTF_COND=0 \
    sim_init.cpp /home/azl/Code/litex/litex/litex/build/sim/core/veril.cpp libdylib.o modules.o pads.o parse.o sim.o \
    --top-module sim \
     \
    -CFLAGS "-ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core" \
    -LDFLAGS "-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent" \
    --trace \
     \
     \
    --unroll-count 256 \
    --output-split 5000 \
    --output-split-cfuncs 500 \
    --output-split-ctrace 500 \
     \
    -Wno-BLKANDNBLK \
    -Wno-WIDTH
%Warning-CASEINCOMPLETE: /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/sim.v:1257:3: Case values incompletely covered (example pattern 0x3)
                                                                                                           : ... In instance sim
 1257 |   case (csr_bankarray_interface0_bank_bus_adr[8:0])
      |   ^~~~
                         ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
%Warning-CASEINCOMPLETE: /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/sim.v:1281:3: Case values incompletely covered (example pattern 0x8)
                                                                                                           : ... In instance sim
 1281 |   case (csr_bankarray_interface1_bank_bus_adr[8:0])
      |   ^~~~
%Warning-CASEINCOMPLETE: /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/sim.v:1336:3: Case values incompletely covered (example pattern 0x8)
                                                                                                           : ... In instance sim
 1336 |   case (csr_bankarray_interface2_bank_bus_adr[8:0])
      |   ^~~~
make -j -C /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir -f Vsim.mk Vsim
make[1]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir'
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o veril.o /home/azl/Code/litex/litex/litex/build/sim/core/veril.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o sim_init.o ../sim_init.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o verilated.o /usr/share/verilator/include/verilated.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o Vsim.o Vsim.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o Vsim_sim.o Vsim_sim.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o Vsim_VexRiscv.o Vsim_VexRiscv.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o Vsim_VexRiscv__1.o Vsim_VexRiscv__1.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o Vsim_VexRiscv__2.o Vsim_VexRiscv__2.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o Vsim__Dpi.o Vsim__Dpi.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o Vsim__Trace.o Vsim__Trace.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14  -c -o Vsim__Slow.o Vsim__Slow.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14  -c -o Vsim_sim__Slow.o Vsim_sim__Slow.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14  -c -o Vsim_VexRiscv__Slow.o Vsim_VexRiscv__Slow.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14  -c -o Vsim_VexRiscv__1__Slow.o Vsim_VexRiscv__1__Slow.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14  -c -o Vsim__Syms.o Vsim__Syms.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14  -c -o Vsim__Trace__Slow.o Vsim__Trace__Slow.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14  -c -o Vsim__Trace__1__Slow.o Vsim__Trace__1__Slow.cpp
Vsim_sim.cpp: In static member function ‘static void Vsim_sim::_sequent__TOP__sim__11(Vsim__Syms*)’:
Vsim_sim.cpp:558:50: warning: ‘__Vdlyvdim0__mem_1__v3’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  558 |                 & vlSymsp->TOP__sim.__PVT__mem_1[__Vdlyvdim0__mem_1__v3])
      |                                                  ^~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:559:19: warning: ‘__Vdlyvval__mem_1__v3’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  559 |                | ((IData)(__Vdlyvval__mem_1__v3) << (IData)(__Vdlyvlsb__mem_1__v3)));
      |                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:552:50: warning: ‘__Vdlyvdim0__mem_1__v2’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  552 |                 & vlSymsp->TOP__sim.__PVT__mem_1[__Vdlyvdim0__mem_1__v2])
      |                                                  ^~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:553:19: warning: ‘__Vdlyvval__mem_1__v2’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  553 |                | ((IData)(__Vdlyvval__mem_1__v2) << (IData)(__Vdlyvlsb__mem_1__v2)));
      |                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:546:50: warning: ‘__Vdlyvdim0__mem_1__v1’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  546 |                 & vlSymsp->TOP__sim.__PVT__mem_1[__Vdlyvdim0__mem_1__v1])
      |                                                  ^~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:547:19: warning: ‘__Vdlyvval__mem_1__v1’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  547 |                | ((IData)(__Vdlyvval__mem_1__v1) << (IData)(__Vdlyvlsb__mem_1__v1)));
      |                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:540:50: warning: ‘__Vdlyvdim0__mem_1__v0’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  540 |                 & vlSymsp->TOP__sim.__PVT__mem_1[__Vdlyvdim0__mem_1__v0])
      |                                                  ^~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:541:19: warning: ‘__Vdlyvval__mem_1__v0’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  541 |                | ((IData)(__Vdlyvval__mem_1__v0) << (IData)(__Vdlyvlsb__mem_1__v0)));
      |                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:534:72: warning: ‘__Vdlyvdim0__mem_2__v3’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  534 |                 & vlSymsp->TOP__sim.__PVT__mem_2[__Vdlyvdim0__mem_2__v3])
      |                   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^
Vsim_sim.cpp:535:19: warning: ‘__Vdlyvval__mem_2__v3’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  535 |                | ((IData)(__Vdlyvval__mem_2__v3) << (IData)(__Vdlyvlsb__mem_2__v3)));
      |                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:528:72: warning: ‘__Vdlyvdim0__mem_2__v2’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  528 |                 & vlSymsp->TOP__sim.__PVT__mem_2[__Vdlyvdim0__mem_2__v2])
      |                   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^
Vsim_sim.cpp:529:19: warning: ‘__Vdlyvval__mem_2__v2’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  529 |                | ((IData)(__Vdlyvval__mem_2__v2) << (IData)(__Vdlyvlsb__mem_2__v2)));
      |                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:522:72: warning: ‘__Vdlyvdim0__mem_2__v1’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  522 |                 & vlSymsp->TOP__sim.__PVT__mem_2[__Vdlyvdim0__mem_2__v1])
      |                   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^
Vsim_sim.cpp:523:19: warning: ‘__Vdlyvval__mem_2__v1’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  523 |                | ((IData)(__Vdlyvval__mem_2__v1) << (IData)(__Vdlyvlsb__mem_2__v1)));
      |                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vsim_sim.cpp:516:72: warning: ‘__Vdlyvdim0__mem_2__v0’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  516 |                 & vlSymsp->TOP__sim.__PVT__mem_2[__Vdlyvdim0__mem_2__v0])
      |                   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^
Vsim_sim.cpp:517:19: warning: ‘__Vdlyvval__mem_2__v0’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  517 |                | ((IData)(__Vdlyvval__mem_2__v0) << (IData)(__Vdlyvlsb__mem_2__v0)));
      |                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/share/verilator/include/verilated.cpp: In function ‘IData VL_FGETS_NI(std::string&, IData)’:
/usr/share/verilator/include/verilated.cpp:1318:36: error: ‘numeric_limits’ is not a member of ‘std’
 1318 |     return getLine(dest, fpi, std::numeric_limits<size_t>::max());
      |                                    ^~~~~~~~~~~~~~
/usr/share/verilator/include/verilated.cpp:1318:57: error: expected primary-expression before ‘>’ token
 1318 |     return getLine(dest, fpi, std::numeric_limits<size_t>::max());
      |                                                         ^
/usr/share/verilator/include/verilated.cpp:1318:60: error: ‘::max’ has not been declared; did you mean ‘std::max’?
 1318 |     return getLine(dest, fpi, std::numeric_limits<size_t>::max());
      |                                                            ^~~
      |                                                            std::max
In file included from /usr/include/c++/11/algorithm:62,
                 from /usr/share/verilator/include/verilated_heavy.h:29,
                 from /usr/share/verilator/include/verilated_imp.h:29,
                 from /usr/share/verilator/include/verilated.cpp:25:
/usr/include/c++/11/bits/stl_algo.h:3467:5: note: ‘std::max’ declared here
 3467 |     max(initializer_list<_Tp> __l, _Compare __comp)
      |     ^~~
make[1]: *** [/usr/share/verilator/include/verilated.mk:241: verilated.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir'
make: *** [/home/azl/Code/litex/litex/litex/build/sim/core/Makefile:39: sim] Error 2
make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware'