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-- Company:
-- Engineer:
--
-- Create Date: 03/09/2018 11:50:18 AM
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
    Port ( a : in std_logic_vector(15 downto 0);
           b : in std_logic_vector(15 downto 0);
           sa: in std_logic;
           OP : in STD_LOGIC_VECTOR(3 downto 0);
           AluRes : out STD_LOGIC_VECTOR (15 downto 0);
           zero : out STD_LOGIC);
end ALU;

architecture Behavioral of ALU is

signal lshift : std_logic_vector(15 downto 0);
signal rshift : std_logic_vector(15 downto 0);

signal result : std_logic_vector(15 downto 0);

begin

process(a,b,sa)
begin

    if(sa = '1')then
        lshift <= a(14 downto 0) & "0";
        rshift <= "0" & a(15 downto 1);

    else
        lshift <= a ;
        rshift <= a ;
    end if;
end;


process(OP)
begin
   case (OP) is
   when "0000" => result <= a + b;
   when "0001" => result <=  a - b;
   when "0010" => result <= lshift;
   when "0011" => result <= rshift;
   when "0100" => result <=  a and b; -- for load / store
   when "0101" => result <=  a or b;
   when "0110" => result <= a xor b;
   when "0111" => result <= a * b;
   when "1000" => result <= b;
   when others => result <=x"0000";
end case;
end process;

zero <= '1' when result  = "0000000000000000" else '0';
AluRes <= result;
end Behavioral;