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Sep 10th, 2012
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  1. .include "macros.inc"
  2.  
  3. initial_page:
  4. start
  5.  
  6. mvhi r1, hi(data2)
  7. ori r1, r1, lo(data2)
  8. mvhi r2, hi(data1)
  9. ori r2, r2, lo(data1)
  10. calli update_dtlb
  11.  
  12. test_name MMU_DTLB_OFF
  13. lw r3, (r1+0)
  14. check_r3 0xc0cac01a
  15.  
  16. test_name MMU_DTLB_ON
  17. calli enable_dtlb
  18. lw r3, (r1+0)
  19. calli disable_dtlb
  20. check_r3 0xdeadbabe
  21.  
  22. test_name MMU_DTLB_MISS_1
  23. calli enable_dtlb
  24. lw r3, (r1+0x1004)
  25. calli disable_dtlb
  26. check_excp 128
  27.  
  28. test_name MMU_DTLB_MISS_2
  29. check_reg r24 data2+0x1004
  30.  
  31. test_name MMU_DTLB_FLUSH
  32. calli enable_dtlb
  33. calli flush_dtlb
  34. lw r3, (r1+0)
  35. calli disable_dtlb
  36. check_excp 128
  37.  
  38. test_name MMU_DTLB_INV
  39. mvhi r1, hi(data2)
  40. ori r1, r1, lo(data2)
  41. mvhi r2, hi(data1)
  42. ori r2, r2, lo(data1)
  43. calli update_dtlb
  44.  
  45. calli enable_dtlb
  46. calli invalidate_dtlb
  47. lw r3, (r1+0)
  48. calli disable_dtlb
  49. check_excp 128
  50.  
  51. # make sure we have a mapping for the current code
  52. mvhi r1, hi(initial_page)
  53. ori r1, r1, lo(initial_page)
  54. mv r2, r1
  55. calli update_itlb
  56.  
  57. mvhi r1, hi(code2)
  58. ori r1, r1, lo(code2)
  59. mvhi r2, hi(code1)
  60. ori r2, r2, lo(code1)
  61. calli update_itlb
  62.  
  63. test_name MMU_ITLB_OFF
  64. bi code2
  65. check_r3 0xaa
  66.  
  67. test_name MMU_ITLB_ON
  68. calli enable_itlb
  69. bi code2
  70. check_r3 0x55
  71.  
  72. end
  73.  
  74. enable_itlb:
  75. rcsr r10, PSW
  76. ori r10, r10, 0x10
  77. wcsr PSW, r10
  78. nop
  79. nop
  80. nop
  81. ret
  82.  
  83. disable_itlb:
  84. rcsr r10, PSW
  85. andi r10, r10, 0xffef
  86. wcsr PSW, r10
  87. nop
  88. nop
  89. nop
  90. ret
  91.  
  92. flush_itlb:
  93. mvi r10, 2
  94. wcsr TLBVADDR, r10
  95. ret
  96.  
  97. invalidate_itlb:
  98. ori r10, r1, 4
  99. wcsr TLBVADDR, r10
  100. ret
  101.  
  102. update_itlb:
  103. ori r10, r1, 1
  104. wcsr TLBVADDR, r10
  105. wcsr TLBPADDR, r2
  106. ret
  107.  
  108. enable_dtlb:
  109. rcsr r10, PSW
  110. ori r10, r10, 0x80
  111. wcsr PSW, r10
  112. ret
  113.  
  114. disable_dtlb:
  115. rcsr r10, PSW
  116. andi r10, r10, 0xff7f
  117. wcsr PSW, r10
  118. ret
  119.  
  120. flush_dtlb:
  121. mvi r10, 3
  122. wcsr TLBVADDR, r10
  123. ret
  124.  
  125. update_dtlb:
  126. wcsr TLBVADDR, r1
  127. wcsr TLBPADDR, r2
  128. ret
  129.  
  130. invalidate_dtlb:
  131. ori r10, r1, 5
  132. wcsr TLBVADDR, r10
  133. ret
  134.  
  135. .align 0x1000
  136. code1:
  137. mvi r3, 0xaa
  138. rcsr r10, PSW
  139. andi r10, r10, 0xffef
  140. wcsr PSW, r10
  141. nop
  142. ret
  143. .align 0x1000
  144. code2:
  145. mvi r3, 0x55
  146. rcsr r10, PSW
  147. andi r10, r10, 0xffef
  148. wcsr PSW, r10
  149. nop
  150. ret
  151.  
  152. .data
  153. .align 0x1000
  154. data1: .long 0xdeadbabe
  155. .align 0x1000
  156. data2: .long 0xc0cac01a
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