----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21.08.2019 15:22:10
-- Design Name:
-- Module Name: Design - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;


entity Ect_v3 is
generic (   CHARGE_TIME_NS          : integer := 144405;
            DISCHARGE_TIME_NS       : integer := 4545;
            START_READ_NS           : integer := 10000;
            PERIOD_NS               : integer := 400000
         );
--  Port ( );
port    (
            S           : inout std_logic;
            SS          : out std_logic
         );
end Ect_v3;

architecture Behavioral of Ect_v3 is

constant clock_cycle : integer := 21;
constant one_time : integer := CHARGE_TIME_NS / clock_cycle;
constant zero_time : integer := (CHARGE_TIME_NS + DISCHARGE_TIME_NS) / clock_cycle;
constant read_time : integer := (START_READ_NS + CHARGE_TIME_NS + DISCHARGE_TIME_NS) / clock_cycle;
constant max_time : integer := PERIOD_NS / clock_cycle;

--signal counter      : std_logic_vector(25 downto 0):=(others=>'0');
signal i_clk        : std_logic;
signal buf_i_clk    : std_logic;
signal r_led_value  : std_logic := '0';

SIGNAL b : STD_LOGIC; --DFF that stores feedback value
shared variable counter : integer range 0 to PERIOD_NS/clock_cycle :=0;
signal dir : std_logic;

begin

    STARTUPE2_inst : STARTUPE2
   generic map (
      PROG_USR => "FALSE",
      SIM_CCLK_FREQ => 0.0
   )
   port map (
      CFGCLK => open,
      CFGMCLK => i_clk,
      EOS => open,
      PREQ => open,
      CLK => '0',
      GSR => '0',
      GTS => '0',
      KEYCLEARB => '0',
      PACK => '0',
      USRCCLKO => '0',
      USRCCLKTS => '0',
      USRDONEO => '1',
      USRDONETS => '0'
   );

	BUFG_i: component BUFG
        port map(
            I => i_clk ,
            O => buf_i_clk
        );

	-- buf_i_clk has around 65MHz

    process(buf_i_clk)
    begin
        if rising_edge(buf_i_clk) then
            if counter < max_time then
                counter := counter + 1;
                if counter < zero_time then
                    dir <= '1';
                else
                    dir <= '0';
                end if;
            else
                dir <= '0';
                counter := 0;
            end if;
        end if;

        SS <= b;

        if (dir = '0') then
            if counter = zero_time then
                S <= 'Z';
            else
                if counter = read_time then
                    b <= S;
                end if;
            end if;
        else
            if counter < one_time then
                S <= '1';
            elsif counter >= one_time and counter < zero_time then
                S <= '0';
            end if;
        end if;
    end process;


end Behavioral;