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Jan 30th, 2023
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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /* Copyright (c) 2023, Lenar Mahmutov <lenz1986@gmail.com> */
  3.  
  4. /dts-v1/;
  5.  
  6. #include "ipq8074.dtsi"
  7. #include "ipq8074-hk-cpu.dtsi"
  8. #include "ipq8074-ess.dtsi"
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/input/input.h>
  11. #include <dt-bindings/leds/common.h>
  12.  
  13. / {
  14. model = "Custom IPQ";
  15. compatible = "custom,ipq8072", "qcom,ipq8074";
  16.  
  17. aliases {
  18. serial0 = &blsp1_uart5;
  19. led-boot = &led_system;
  20. led-failsafe = &led_system;
  21. led-running = &led_system;
  22. led-upgrade = &led_system;
  23. /* Aliases as required by u-boot to patch MAC addresses */
  24. ethernet0 = &dp5;
  25. ethernet1 = &dp6;
  26. label-mac-device = &dp5;
  27. };
  28.  
  29. chosen {
  30. stdout-path = "serial0:115200n8";
  31. bootargs-append = " root=/dev/ubiblock0_1";
  32. };
  33.  
  34. keys {
  35. compatible = "gpio-keys";
  36. pinctrl-0 = <&button_pins>;
  37. pinctrl-names = "default";
  38.  
  39. reset {
  40. label = "reset";
  41. gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
  42. linux,code = <KEY_RESTART>;
  43. };
  44. };
  45.  
  46. leds {
  47. compatible = "gpio-leds";
  48.  
  49. led_system: system {
  50. label = "red:system";
  51. gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
  52. };
  53.  
  54. led_wlan2g {
  55. label = "green:wlan2g";
  56. gpio = <&tlmm 2 GPIO_ACTIVE_HIGH>;
  57. linux,default-trigger = "phy1radio";
  58. };
  59.  
  60. led_wlan5g {
  61. label = "green:wlan5g";
  62. gpio = <&tlmm 9 GPIO_ACTIVE_HIGH>;
  63. linux,default-trigger = "phy0radio";
  64. };
  65.  
  66. };
  67. };
  68.  
  69. &tlmm {
  70. mdio_pins: mdio-pins {
  71. mdc {
  72. pins = "gpio68";
  73. function = "mdc";
  74. drive-strength = <8>;
  75. bias-pull-up;
  76. };
  77.  
  78. mdio {
  79. pins = "gpio69";
  80. function = "mdio";
  81. drive-strength = <8>;
  82. bias-pull-up;
  83. };
  84. };
  85.  
  86. button_pins: button_pins {
  87. reset_button {
  88. pins = "gpio57";
  89. function = "gpio";
  90. drive-strength = <8>;
  91. bias-pull-up;
  92. };
  93. };
  94. };
  95.  
  96. &blsp1_spi1 {
  97. status = "okay";
  98.  
  99. flash@0 {
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. reg = <0>;
  103. compatible = "jedec,spi-nor";
  104. spi-max-frequency = <50000000>;
  105.  
  106. partitions {
  107. compatible = "fixed-partitions";
  108. #address-cells = <1>;
  109. #size-cells = <1>;
  110.  
  111. partition@0 {
  112. label = "0:sbl1";
  113. reg = <0x0 0x50000>;
  114. read-only;
  115. };
  116.  
  117. partition@50000 {
  118. label = "0:mibib";
  119. reg = <0x50000 0x10000>;
  120. read-only;
  121. };
  122.  
  123. partition@60000 {
  124. label = "0:bootconfig";
  125. reg = <0x60000 0x20000>;
  126. read-only;
  127. };
  128.  
  129. partition@80000 {
  130. label = "0:bootconfig1";
  131. reg = <0x80000 0x20000>;
  132. read-only;
  133. };
  134.  
  135. partition@a0000 {
  136. label = "0:qsee";
  137. reg = <0xa0000 0x180000>;
  138. read-only;
  139. };
  140.  
  141. partition@220000 {
  142. label = "0:qsee_1";
  143. reg = <0x220000 0x180000>;
  144. read-only;
  145. };
  146.  
  147. partition@3a0000 {
  148. label = "0:devcfg";
  149. reg = <0x3a0000 0x10000>;
  150. read-only;
  151. };
  152.  
  153. partition@3b0000 {
  154. label = "0:devcfg_1";
  155. reg = <0x3b0000 0x10000>;
  156. read-only;
  157. };
  158.  
  159. partition@3c0000 {
  160. label = "0:apdp";
  161. reg = <0x3c0000 0x10000>;
  162. read-only;
  163. };
  164.  
  165. partition@3d0000 {
  166. label = "0:apdp_1";
  167. reg = <0x3d0000 0x10000>;
  168. read-only;
  169. };
  170.  
  171. partition@3e0000 {
  172. label = "0:rpm";
  173. reg = <0x3e0000 0x40000>;
  174. read-only;
  175. };
  176.  
  177. partition@420000 {
  178. label = "0:rpm_1";
  179. reg = <0x420000 0x40000>;
  180. read-only;
  181. };
  182.  
  183. partition@460000 {
  184. label = "0:cdt";
  185. reg = <0x460000 0x10000>;
  186. read-only;
  187. };
  188.  
  189. partition@470000 {
  190. label = "0:cdt_1";
  191. reg = <0x470000 0x10000>;
  192. read-only;
  193. };
  194.  
  195. partition@480000 {
  196. label = "0:appsblenv";
  197. reg = <0x480000 0x10000>;
  198. };
  199.  
  200. partition@490000 {
  201. label = "0:appsbl";
  202. reg = <0x490000 0xc0000>;
  203. read-only;
  204. };
  205.  
  206. partition@550000 {
  207. label = "0:appsbl_1";
  208. reg = <0x530000 0xa0000>;
  209. read-only;
  210. };
  211.  
  212. partition@610000 {
  213. label = "0:art";
  214. reg = <0x5d0000 0x40000>;
  215. read-only;
  216. };
  217.  
  218. partition@650000 {
  219. label = "0:ethphyfw";
  220. reg = <0x610000 0x80000>;
  221. read-only;
  222. };
  223. };
  224. };
  225. };
  226.  
  227. &blsp1_uart5 {
  228. status = "okay";
  229. };
  230.  
  231. &crypto {
  232. status = "okay";
  233. };
  234.  
  235. &cryptobam {
  236. status = "okay";
  237. };
  238.  
  239. &prng {
  240. status = "okay";
  241. };
  242.  
  243. &qpic_bam {
  244. status = "okay";
  245. };
  246.  
  247. &qusb_phy_0 {
  248. status = "okay";
  249. };
  250.  
  251. &ssphy_0 {
  252. status = "okay";
  253. };
  254.  
  255. &usb_0 {
  256. status = "okay";
  257. };
  258.  
  259. &qpic_nand {
  260. status = "okay";
  261.  
  262. nand@0 {
  263. reg = <0>;
  264. nand-bus-width = <8>;
  265.  
  266. partitions {
  267. compatible = "fixed-partitions";
  268. #address-cells = <1>;
  269. #size-cells = <1>;
  270.  
  271. partition@0 {
  272. label = "rootfs";
  273. reg = <0x0000000 0x3400000>;
  274. };
  275.  
  276. partition@3400000 {
  277. label = "0:wififw";
  278. reg = <0x3400000 0x800000>;
  279. read-only;
  280. };
  281.  
  282. partition@3c00000 {
  283. label = "rootfs_1";
  284. reg = <0x3c00000 0x3400000>;
  285. };
  286.  
  287. partition@7000000 {
  288. label = "0:wififw_1";
  289. reg = <0x7000000 0x800000>;
  290. read-only;
  291. };
  292. };
  293. };
  294. };
  295.  
  296. &mdio {
  297. status = "okay";
  298.  
  299. pinctrl-0 = <&mdio_pins>;
  300. pinctrl-names = "default";
  301. reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
  302.  
  303. qca8081_24: ethernet-phy@24 {
  304. compatible = "ethernet-phy-id004d.d101";
  305. reg = <24>;
  306. };
  307.  
  308. qca8081_28: ethernet-phy@28 {
  309. compatible = "ethernet-phy-id004d.d101";
  310. reg = <28>;
  311. };
  312. };
  313.  
  314. &switch {
  315. status = "okay";
  316.  
  317. switch_cpu_bmp = <0x1>; /* cpu port bitmap */
  318. switch_lan_bmp = <0x20>; /* lan port bitmap */
  319. switch_wan_bmp = <0x40>; /* wan port bitmap */
  320. switch_mac_mode = <0x00>; /* mac mode for uniphy instance0 */
  321. switch_mac_mode1 = <0x0f>; /* mac mode for uniphy instance1 */
  322. switch_mac_mode2 = <0x0f>; /* mac mode for uniphy instance2 */
  323. bm_tick_mode = <0>; /* bm tick mode */
  324. tm_tick_mode = <0>; /* tm tick mode */
  325.  
  326. qcom,port_phyinfo {
  327. port@4 {
  328. port_id = <5>;
  329. phy_address = <24>;
  330. port_mac_sel = "QGMAC_PORT";
  331. };
  332. port@5 {
  333. port_id = <6>;
  334. phy_address = <28>;
  335. port_mac_sel = "QGMAC_PORT";
  336. };
  337. };
  338. };
  339.  
  340. &edma {
  341. status = "okay";
  342. };
  343.  
  344. &dp5 {
  345. status = "okay";
  346. phy-handle = <&qca8081_28>;
  347. label = "wan";
  348. };
  349.  
  350. &dp6 {
  351. status = "okay";
  352. phy-handle = <&qca8081_24>;
  353. label = "lan";
  354. };
  355.  
  356. &wifi {
  357. status = "okay";
  358. qcom,ath11k-calibration-variant = "custom-IPQ";
  359. };
  360.  
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