module clocks (
    input  wire   mclk,     // 25MHz input clock.
    output wire [7:0] segments, // сегменты, включая точку.
    output wire [5:0] digits    // общие катоды, 6 шт.
);

// Переменные:
    reg [24:0]  tima;
    reg [06:0]  sec;
    reg [06:0]  min;
    reg [05:0]  hr;
    reg [05:0]  digit;
    reg [06:0]  seg;
    reg [03:0]  num;
    reg dot;
    reg s_en = 1'b0;

// Получаем 1Гц.:
always @ (posedge mclk) begin
    if (tima==25'd24999999) begin tima <= 25'd0; s_en <= 1'b1; end
        else begin tima <= tima + 1; s_en <= 1'b0;  end
end

// Обработка секунд, минут, часов:
always @ (posedge s_en)
begin
    if (sec < 8'h59) sec <= (sec[3:0] == 4'd9) ? sec+7 : sec+1;
        else begin
            sec <= 7'd0;
            if (min < 8'h59) min <= (min[3:0] == 4'd9) ? min+7 : min+1;
                else begin
                    min <= 7'd0;
                    if(hr==6'd23) hr <= 0;
                        else begin
                            hr <= (hr[3:0] == 4'd9) ? hr+7 : hr+1;
                        end
                end
        end
end
//
always @ (posedge mclk) begin
    case (num)
        4'd0:    seg[6:0] <= 7'b0000001;
        4'd1:    seg[6:0] <= 7'b1001111;
        4'd2:    seg[6:0] <= 7'b0010010;
        4'd3:    seg[6:0] <= 7'b0000110;
        4'd4:    seg[6:0] <= 7'b1001100;
        4'd5:    seg[6:0] <= 7'b0100100;
        4'd6:    seg[6:0] <= 7'b0100000;
        4'd7:    seg[6:0] <= 7'b0001111;
        4'd8:    seg[6:0] <= 7'b0000000;
        4'd9:    seg[6:0] <= 7'b0000100;
        default: seg[6:0] <= 7'b1111111;
    endcase
end

always @ (posedge mclk) begin
    if (tima[4]) begin
        case (tima[7:5])
            3'd0:   begin digit <= 6'b000001; num <= sec[3:0]; dot <= 1; end
            3'd1:   begin digit <= 6'b000010; num <= {1'b0,sec[6:4]}; dot <= 1; end
            3'd2:   begin digit <= 6'b000100; num <= min[3:0]; dot <= 0; end
            3'd3:   begin digit <= 6'b001000; num <= {1'b0,min[6:4]}; dot <= 1; end
            3'd4:   begin digit <= 6'b010000; num <= hr[3:0]; dot <= 0; end
            3'd5:   begin digit <= 6'b100000; num <= {2'b00,hr[5:4]}; dot <= 1; end
            default: digit <= 6'b000000;
        endcase
    end
    else begin digit <= 6'b000000; num <= 4'd10; end
end

assign segments[7:0] = {seg [6:0], dot};
assign digits[5:0] = digit[5:0];
endmodule