kekellner

Lab07 - Ej07 - Completo

Oct 14th, 2021
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  1. module FSM (input A, clk, reset, output Y, output [1:0] state, next_state);
  2.  
  3.     reg [1:0] rstate, rnext_state;
  4.     reg rY;
  5.     parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
  6.  
  7.     // Next State Logic
  8.     always @ (A or rstate) begin
  9.         case (rstate)
  10.             S0:
  11.                 if (A)
  12.                     rnext_state <= S1;
  13.                 else
  14.                     rnext_state <= S0;
  15.             S1:
  16.                 if (A)
  17.                     rnext_state <= S1;
  18.                 else
  19.                     rnext_state <= S2;
  20.             S2:
  21.                 if (A)
  22.                     rnext_state <= S3;
  23.                 else
  24.                     rnext_state <= S0;
  25.             S3:
  26.                 if (A)
  27.                     rnext_state <= S1;
  28.                 else
  29.                     rnext_state <= S0;
  30.         endcase
  31.     end
  32.  
  33.     // Flip flops
  34.     always @ (posedge clk or posedge reset)
  35.         if (reset)
  36.             rstate <= S0;
  37.         else
  38.             rstate <= rnext_state;
  39.  
  40.     // Outputs Logic
  41.     always @ (rstate)
  42.         case (rstate)
  43.             S0: rY = 0;
  44.             S1: rY = 0;
  45.             S2: rY = 0;
  46.             S3: rY = 1;
  47.             default: rY = 0;
  48.         endcase
  49.  
  50.  
  51.  
  52.     // Wire output assignment
  53.     assign state = rstate;
  54.     assign next_state = rnext_state;
  55.     assign Y = rY;
  56.  
  57. endmodule
  58.  
  59.  
  60.  
  61. module tb();
  62.  
  63.     // Inputs
  64.     reg A, clk, reset;
  65.     // Outputs
  66.     wire Y;
  67.     wire [1:0] state, next_state;
  68.  
  69.     // Module instantiation
  70.     FSM U1 (A, clk, reset, y, state, next_state);
  71.  
  72.     initial begin
  73.         A = 0; clk = 1; reset = 0;
  74.         #2 reset = 1;
  75.         #2 reset = 0;
  76.         #18 A = 1;
  77.         #10 A = 0;
  78.         #10 A = 1;
  79.         #40 A = 0;
  80.         #40 A = 1;
  81.         #10 A = 0;
  82.         #10 A = 1;
  83.         #10 A = 0;
  84.         #10 A = 1;
  85.         #10 A = 0;
  86.         #10 A = 1;
  87.     end
  88.  
  89.     initial
  90.         #200 $finish;
  91.  
  92.     initial begin
  93.         $dumpfile("timing.vcd");
  94.         $dumpvars(0, tb);
  95.     end
  96.  
  97.     always
  98.         #5 clk = ~clk;
  99.  
  100. endmodule
  101.  
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