module cw1(KEY, SW, LEDR, HEX0, HEX1, HEX2, HEX3, REX0, REX1, REX2, REX3);
input [3:0] KEY;
input [9:0] SW;
output reg [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3;
output reg [9:0] REX0, REX1, REX2, REX3;

    dec_to_hex y0 (REX0, HEX0);
    dec_to_hex y1 (REX1, HEX1);
    dec_to_hex y2 (REX2, HEX2);
    dec_to_hex y3 (REX3, HEX3);

    always
        if(KEY[0] == 0) begin
            LEDR[9:0] = SW[9:5] + SW[4:0];
            REX0 = LEDR % 10;
            REX1 = LEDR / 10 % 10;
            REX2 = LEDR / 100 % 10;
            REX3 = LEDR / 1000 % 10;
        end

        else if (KEY[1] == 0) begin
            if (SW[9:5] < SW[4:0]) begin
                LEDR[9:0] = SW[4:0] - SW[9:5];
                REX3 = 10;
            end
            else begin
                LEDR[9:0] = SW[9:5] - SW[4:0];
                REX3 = 0;
            end
            REX0 = LEDR % 10;
            REX1 = LEDR / 10 % 10;
            REX2 = LEDR / 100 % 10;
        end

        else if (KEY[2] == 0) begin
            LEDR[9:0] = SW[9:5] * SW[4:0];
            REX0 = LEDR % 10;
            REX1 = LEDR / 10 % 10;
            REX2 = LEDR / 100 % 10;
            REX3 = LEDR / 1000 % 10;
        end
        else begin
            LEDR[9:5] = SW[9:5];
            LEDR[4:0] = SW[4:0];

            REX0 = LEDR[4:0] % 10;
            REX1 = LEDR[4:0] / 10 % 10;
            REX2 = LEDR[9:5] % 10;
            REX3 = LEDR[9:5] / 10 % 10;
        end

endmodule


module dec_to_hex(dec, hex);
    input [3:0] dec;
    output reg [6:0] hex;

    always
    case (dec)
        11: hex = 7'b1111111; // [nic]
        10: hex = 7'b0111111; // -
        0: hex = 7'b1000000; // 0
        1: hex = 7'b1111001; // 1
        2: hex = 7'b0100100; // 2
        3: hex = 7'b0110000; // 3
        4: hex = 7'b0011001; // 4
        5: hex = 7'b0010010; // 5
        6: hex = 7'b0000010; // 6
        7: hex = 7'b1111000; // 7
        8: hex = 7'b0000000; // 8
        9: hex = 7'b0010000; // 9
        default: hex = 7'b1000000; // 0
    endcase

endmodule