ulx3s memory relocation

diff --git a/litex_boards/targets/radiona_ulx3s.py b/litex_boards/targets/radiona_ulx3s.py
index 925a427..2feda33 100755
--- a/litex_boards/targets/radiona_ulx3s.py
+++ b/litex_boards/targets/radiona_ulx3s.py
@@ -86,6 +86,12 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------

 class BaseSoC(SoCCore):
+    mem_map = {
+        "rom"  : 0x00000000,
+        "sram" : 0x40000000,
+        "main_ram" : 0x80000000,
+        "csr"  : 0xf0000000,
+    }
     def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
         sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1",
         with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,


diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 083e0726..7573c70c 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -105,7 +105,7 @@ class VexRiscv(CPU, AutoCSR):
     gcc_triple           = CPU_GCC_TRIPLE_RISCV32
     linker_output_format = "elf32-littleriscv"
     nop                  = "nop"
-    io_regions           = {0x80000000: 0x80000000} # Origin, Length
+    io_regions           = {0xF0000000: 0x10000000} # Origin, Length

     # Memory Mapping.
     @property
@@ -113,7 +113,7 @@ class VexRiscv(CPU, AutoCSR):
         return {
             "rom":            0x00000000,
             "sram":           0x10000000,
-            "main_ram":       0x40000000,
+            "main_ram":       0x80000000,
             "csr":            0xf0000000,
             "vexriscv_debug": 0xf00f0000,
         }