module swfsj6(input [7:0]SW,
                    input KEY1, KEY0, KEY2,
                    output[6:0]HEX3, HEX2, HEX1, HEX0,
                    output [9:0]LEDR);

        wire [7:0]sum;

        assign LEDR[7:0] = sum;

        multiplier_N_bits #(4) ex(SW[7:4], SW[3:0], sum);

        decoder_hex_16 ex1(sum[7:4], HEX1);
        decoder_hex_16 ex2(sum[3:0], HEX0);
        decoder_hex_16 ex3(SW[7:4], HEX3);
        decoder_hex_16 ex4(SW[3:0], HEX2);

endmodule

module multiplier_N_bits
    #(parameter N=4)
    (input [N-1:0] a,b,
    output [2*N-1:0] p);

    wire [3:0] m[3:0];
    wire [3:0] s[1:3];
    wire cout[1:3];
    genvar i;

    generate
        for(i=0; i<N; i=i+1) begin:bl1
            assign m[i] = a & {N{b[i]}};
        end
    endgenerate

    adder_N #(N) ex1({1'b0,m[0][N-1:1]},m[1],1'b0,s[1],cout[1]);
    generate
        for(i=2; i<N; i=i+1) begin:bl2
            adder_N #(N)
            exi({cout[i-1],s[i-1][N-1:1]},m[i],1'b0,s[i],cout[i]);
        end
    endgenerate
    assign p[0] = m[0][0];
    generate
        for(i=1;i<N-1;i=i+1) begin:bl3
            assign p[i] = s[i][0];
        end
    endgenerate

    assign p[2*N-2:N-1] = s[N-1];
    assign p[2*N-1] = cout[N-1];
endmodule

module array_multiplier_4_bits(input [3:0] a,b, output [7:0] p);
    wire    c_1_1,c_2_1,c_3_1,c_4_1,
            c_2_2,c_3_2,c_4_2,c_5_2,
            c_3_3, c_4_3,c_5_3,
            s_2_1,s_3_1,s_4_1,s_3_2,s_4_2,s_5_2;

    assign p[0] = a[0] & b[0];
    adder_1_bits ex_1_1(a[1]&b[0],a[0]&b[1],1'b0,p[1],c_1_1);
    adder_1_bits ex_2_1(a[2]&b[0],a[1]&b[1],c_1_1,s_2_1,c_2_1);
    adder_1_bits ex_3_1(a[3]&b[0],a[2]&b[1],c_2_1,s_3_1,c_3_1);
    adder_1_bits ex_4_1(1'b0,a[3]&b[1],c_3_1,s_4_1,c_4_1);
    adder_1_bits ex_2_2(s_2_1,a[0]&b[2],1'b0,p[2],c_2_2);
    adder_1_bits ex_3_2(s_3_1,a[1]&b[2],c_2_2,s_3_2,c_3_2);
    adder_1_bits ex_4_2(s_4_1,a[2]&b[2],c_3_2,s_4_2,c_4_2);
    adder_1_bits ex_5_2(c_4_1,a[3]&b[2],c_4_2,s_5_2,c_5_2);
    adder_1_bits ex_3_3(s_3_2,a[0]&b[3],1'b0,p[3],c_3_3);
    adder_1_bits ex_4_3(s_4_2,a[1]&b[3],c_3_3,p[4],c_4_3);
    adder_1_bits ex_5_3(s_5_2,a[2]&b[3],c_4_3,p[5],c_5_3);
    adder_1_bits ex_6_3(c_5_2,a[3]&b[3],c_5_3,p[6],p[7]);
endmodule

module add_sub_N_bits
    #(N=8)
    (input [N-1:0] A,
    input add_sub,
    input clk,aclr,
    output reg [N-1:0] S,
    output reg overflow,carry);
    reg [N-1:0] B;
    always @(posedge clk, negedge aclr)
        if (!aclr)      B <= {N{1'b0}};
        else        B <= A;
    always @(posedge clk, negedge aclr)
        if (!aclr)      {carry,S} <= {(N+1){1'b0}};
        else if (add_sub)   {carry,S} <= S + B;
        else        {carry,S} <= S - B;
    always @(posedge clk, negedge aclr)
        if (!aclr)      overflow <= 1'b0;
        else        overflow <= carry ^ S[N-1];
endmodule

module accumulator_N_bits_always
    #(N=8)
    (input [N-1:0] A,
    input clk,
    output reg [N-1:0] S,
    output reg overflow,carry);

    reg [N-1:0] B;

    always @(posedge clk)
        B <= A;

    always @(posedge clk)
        {carry,S} <= B + S;

    always @(posedge clk)
        overflow <= carry ^ S[N-1];
endmodule

module accumulator_N_bits_struct    #(N=8)
    (input [N-1:0] A,
    input clk,
    output [N-1:0] S,
    output ov, ca);

    wire [N-1:0] B, C /* synthesis keep */;
    wire a, x /* synthesis keep */;

    register_N #(8) ex(A,clk,B);

    adder_N #(8) ex0(B,S,1'b0,C,a);
    register_N #(8) ex1(C,clk,S);
    FFD ex2(a,clk,ca);
    assign x = a ^ C[N-1];
    FFD ex3(x,clk,ov);

endmodule

module register_N
    #(N=8)
    (input [N-1:0] D,
    input clk,
    output reg [N-1:0] Q);

    always @(posedge clk)
        Q <= D;
endmodule

module adder_1_bits(
    input a,b,cin,
    output s,cout);

    assign s = a ^ b ^ cin;
    assign cout = a & b & (a ^ b) & cin;

endmodule

module adder_N
    #(parameter N=8)
    (input [N-1:0] A,B,
    input cin,
    output [N-1:0] S,
    output cout);

    assign {cout,S} = A + B + cin;

endmodule

module adder_ripple_carry_N_bits
    #(parameter N=4)
    (input [N-1:0] A, B, input CI,
    output [N-1:0] S, output CO);
    wire [N-1:0] c;
    generate
        genvar i;
        for (i=0; i<N; i=i+1)
        begin: ad
                case(i)
                    0:  adder_1_bits x(A[i], B[i], CI, S[i], c[i]);
                    N-1:    adder_1_bits x(A[i], B[i], c[i-1], S[i], CO);
                    default:    adder_1_bits x(A[i], B[i], c[i-1], S[i], c[i]);
                endcase
        end
    endgenerate
endmodule

module FFD(input D, clk,
                output reg Q);
        always @(posedge clk)
            Q <= D;
endmodule

module decoder_hex_16(input [3:0]x, output reg [0:6]h);
    always @*

    case(x)
    4'b0000: h = 7'b0000001;
    4'b0001: h = 7'b1001111;
    4'b0010: h = 7'b0010010;
    4'b0011: h = 7'b0000110;
    4'b0100: h = 7'b1001100;
    4'b0101: h = 7'b0100100;
    4'b0110: h = 7'b0100000;
    4'b0111: h = 7'b0001111;
    4'b1000: h = 7'b0000000;
    4'b1001: h = 7'b0000100;
    4'b1010: h = 7'b0001000;
    4'b1011: h = 7'b1100000;
    4'b1100: h = 7'b0011000;
    4'b1101: h = 7'b1000010;
    4'b1110: h = 7'b0110000;
    4'b1111: h = 7'b0111000;

    endcase

endmodule