CeciliaCamimura_Somador4bits_Iverilog

/* Somador completo de 1-bit */
module somador_1_bit(y,co,a,b,ci);
output y,co;
input a,b,ci;
wire y,co,a,b,ci;

assign y = (a^b)^ci;
assign co = (a&b)|(a&ci)|(b&ci);
endmodule

/*Somador de 4-bit */

module somador_4_bits(y,c,a,b);
output [3:0]y;
output c;
input [3:0]a;
input [3:0]b;
wire [3:0]y;
wire c,c1,c2,c3;
wire [3:0]a;
wire [3:0]b;

somador_1_bit s1(y[0],c1,a[0],b[0],c);
somador_1_bit s2(y[1],c2,a[1],b[1],c1);
somador_1_bit s3(y[2],c3,a[2],b[2],c2);
somador_1_bit s4(y[3],c,a[3],b[3],c3);

endmodule

/* Complemento de 2 1-bit */
module comp_2(y,sco,a,sub,sci);
output y,sco;
input a,sub,sci;
wire y,sco,a,sub,sci,x;

assign x = a^sub;
assign y = x^sci;
assign sco = x&sci;

endmodule

/* Test-bench do somador de 1-bit */
module tb();

reg [3:0]a;
reg [3:0]b;		// entradas de controle comuns e D do flip-flop
wire [3:0]y;
wire c;		// saídas

initial begin
	$dumpfile("somador.vcd");
	$dumpvars(0,tb);

	/* Initial values */
	a = 4'b0000;
	b = 4'b0000;

	#10 a = 4'b0001;
	#10 b = 4'b0001;
	#10 a = 4'b1000;
	#10 b = 4'b0010;
	#10 b = 4'b0011; a = 4'b0100;
    #10 b = 4'b1111; a = 4'b1111;
	#10  $finish;
end

somador_4_bits s(y,c,a,b);

endmodule