//////////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////////

module restreamer_retransmiter(clk, reset, data, out, data_in_counter);

input clk;              //Counter clock, must be 3*input data clock
input reset;            //Reset input active high
input wire [3:0] data;    //Input data
input wire [2:0] data_in_counter;

output logic out;

logic [3:0] bit_quantity;


//////////////////////////////////////////////////////////////////////////////////


always @ * begin
    bit_quantity <= data[0] + data[1] + data[2] + data[3];
end

always @ (posedge clk) begin
  if(reset) begin
      out <= 1'b0;
  end else begin
      if(bit_quantity > data_in_counter) begin
          out <= 1'b1;
      end else begin
          out <= 1'b0;
      end
  end
end

endmodule