SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;RE;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected
L0:00000000
L1:00000703
L2:00008067
L3:15000000
S1:00000000
B2:20282000
B1:a0f83180

TE: 260782

BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz

Board ID = 8
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
board id: 8
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part:0
fw parse done
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 266
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 4, cur: 2. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==87 ps 9
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==29
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==29
DeviceVref_Margin_A0==29
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0


channel==1
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==97 ps 10
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==30
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==26
DeviceVref_Margin_A0==29
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004

soc_vref_reg_value 0x 00000024 00000027 00000024 00000024 00000025 00000027 0002
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:53:31
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass

100bdlr_step_size ps== 437
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part:0
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x000a4000, part: 0
bl2z: ptr: 05129330, size: 00001e40
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
OPS=0x04
ring efuse init
2b 0c 04 00 01 11 30 00 00 01 37 38 57 4b 52 50
[0.017320 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE:  BL31: v1.3(release):4fc40b1
NOTICE:  BL31: Built : 15:57:33, May 22 2019
NOTICE:  BL31: G12A normal boot!
NOTICE:  BL31: BL33 decompress pass
ERROR:   Error initializing runtime service opteed_fast


U-Boot 2020.04 (Oct 13 2020 - 13:13:35 +0800) khadas-vim3l

Model: Khadas VIM3L
SoC:   Amlogic Meson SM1 (Unknown) Revision 2b:c (4:2)
DRAM:  2 GiB
MMC:   sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2
Loading Environment from FAT... detect... booted from sd...
OK
In:    serial
Out:   serial
Err:   serial
fusb302_init: Device ID: 0x91
CC connected in 1 as UFP
fusb302 detect chip.port_num = 0
Net:   eth0: ethernet@ff3f0000
** Unrecognized filesystem type **
** No partition table - mmc 2 **
starting USB...
Bus usb@ff500000: Register 3000140 NbrPorts 3
Starting the controller
USB XHCI 1.10
scanning bus usb@ff500000 for devices... Failed to get keyboard state from devi3
3 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found
Setting bus to 0
Hit SPACE in 1 seconds to stop autoboot=>                                      '
Unknown command '' - try 'help'
=>
Unknown command '' - try 'help'
=>
Unknown command '' - try 'help'
=> printenv
arch=arm
baudrate=115200
board=w400
board_name=w400
boot_a_script=load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${pref
boot_efi_binary=if fdt addr ${fdt_addr_r}; then bootefi bootmgr ${fdt_addr_r};e
boot_extlinux=sysboot ${devtype} ${devnum}:${distro_bootpart} any ${scriptaddr}}
boot_net_usb_start=;
boot_prefixes=/ /boot/
boot_script_dhcp=boot.scr.uimg
boot_scripts=boot.cmd boot.ini boot.scr.uimg boot.scr
boot_source=sd
boot_syslinux_conf=extlinux/extlinux.conf
boot_targets=spi usb0 mmc0 mmc1 mmc2  pxe dhcp
bootcmd=run distro_bootcmd
bootcmd_dhcp=run boot_net_usb_start; if dhcp ${scriptaddr} ${boot_script_dhcp};;
bootcmd_mmc0=devnum=0; run mmc_boot
bootcmd_mmc1=devnum=1; run mmc_boot
bootcmd_mmc2=devnum=2; run mmc_boot
bootcmd_pxe=run boot_net_usb_start; dhcp; if pxe get; then pxe boot; fi
bootcmd_romusb=if test "${boot_source}" = "usb" && test -n "${scriptaddr}"; thei
bootcmd_spi=test "$boot_source" = "spi" && sf probe && sf read $loadaddr 0x16001
bootcmd_usb0=devnum=0; run usb_boot
bootdelay=1
bootfile=boot.scr.uimg
cpu=armv8
distro_bootcmd=for target in ${boot_targets}; do run bootcmd_${target}; done
efi_dtb_prefixes=/ /dtb/ /dtb/current/
ethaddr=d6:f0:e7:10:de:c9
fdt_addr_r=0x08008000
fdt_size=b72b
fdtcontroladdr=7bf10690
fdtcontroladdr_end=7bf1bdbb
fdtfile=amlogic/meson-sm1-khadas-vim3l.dtb
hostname=meson-sm1-khadas-vim3l
kernel_addr_r=0x08080000
load_efi_dtb=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${prefi}
load_logo=ll=0; test $boot_source = spi && sf probe && sf read $loadaddr 0x1700
loadaddr=0x01000000
mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi
preboot=run load_logo; usb start; kbi init; sleep 1;
pxefile_addr_r=0x01080000
ramdisk_addr_r=0x13000000
scan_dev_for_boot=echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for;
scan_dev_for_boot_part=part list ${devtype} ${devnum} -bootable devplist; env et
scan_dev_for_efi=setenv efi_fdtfile ${fdtfile}; for prefix in ${efi_dtb_prefixee
scan_dev_for_extlinux=if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefi
scan_dev_for_scripts=for script in ${boot_scripts}; do if test -e ${devtype} ${e
scriptaddr=0x08000000
soc=meson
stderr=vidconsole,serial
stdin=usbkbd,serial
stdout=vidconsole,serial
usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boi
vendor=amlogic

Environment size: 4741/8188 bytes
=> mmc help
mmc - MMC sub system

Usage:
mmc info - display info of the current MMC device
mmc read addr blk# cnt
mmc write addr blk# cnt
mmc erase blk# cnt
mmc rescan
mmc part - lists available partition on current mmc device
mmc dev [dev] [part] - show or set current mmc device [partition]
mmc list - lists available devices
mmc wp - power on write protect booot partitions
mmc hwpartition [args...] - does hardware partitioning
  arguments (sizes in 512-byte blocks):
    [user [enh start cnt] [wrrel {on|off}]] - sets user data area attributes
    [gp1|gp2|gp3|gp4 cnt [enh] [wrrel {on|off}]] - general purpose partition
    [check|set|complete] - mode, complete set partitioning completed
  WARNING: Partitioning is a write-once setting once it is set to complete.
  Power cycling is required to initialize partitions after set to complete.
mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode
 - Set the BOOT_BUS_WIDTH field of the specified device
mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>
 - Change sizes of boot and RPMB partitions of specified device
mmc partconf dev [boot_ack boot_partition partition_access]
 - Show or change the bits of the PARTITION_CONFIG field of the specified device
mmc rst-function dev value
 - Change the RST_n_FUNCTION field of the specified device
   WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.
mmc rpmb read addr blk# cnt [address of auth-key] - block size is 256 bytes
mmc rpmb write addr blk# cnt <address of auth-key> - block size is 256 bytes
mmc rpmb key <address of auth-key> - program the RPMB authentication key.
mmc rpmb counter - read the value of the write counter
mmc setdsr <value> - set DSR register value

=> mmcinfo
Card did not respond to voltage select!
=> mmc info
Card did not respond to voltage select!
=> mmc list
sd@ffe03000: 0
sd@ffe05000: 1 (eMMC)
mmc@ffe07000: 2 (eMMC)
=> mmc part
Card did not respond to voltage select!
=> mmc dev 0:1
Card did not respond to voltage select!
=> mmc dev 0:1
Card did not respond to voltage select!
=> mmc dev 1:1
switch to partitions #0, OK
mmc1(part 0) is current device
=> mmc dev 1:0
switch to partitions #0, OK
mmc1(part 0) is current device
=> mmc list
sd@ffe03000: 0
sd@ffe05000: 1 (eMMC)
mmc@ffe07000: 2 (eMMC)
=> mmcinfo
Device: sd@ffe05000
Manufacturer ID: 88
OEM: 103
Name: SLD32
Bus Speed: 52000000
Mode: MMC High Speed (52MHz)
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: 28.9 GiB
Bus Width: 4-bit
Erase Group Size: 512 KiB
HC WP Group Size: 4 MiB
User Capacity: 28.9 GiB WRREL
Boot Capacity: 4 MiB ENH
RPMB Capacity: 4 MiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected
=> mmc dev 2:1
switch to partitions #0, OK
mmc2(part 0) is current device
=> mmcinfo
Device: mmc@ffe07000
Manufacturer ID: 15
OEM: 100
Name: AJTD4
Bus Speed: 25000000
Mode: MMC legacy
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: 14.6 GiB
Bus Width: 8-bit
Erase Group Size: 512 KiB
HC WP Group Size: 8 MiB
User Capacity: 14.6 GiB WRREL
Boot Capacity: 4 MiB ENH
RPMB Capacity: 4 MiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected
=> mmc dev 1:1
switch to partitions #0, OK
mmc1(part 0) is current device
=> mmc part

Partition Map for MMC device 1  --   Partition Type: DOS

Part    Start Sector    Num Sectors     UUID            Type
  1     62500           437501          48ae7808-01     0c
  2     500001          10583775        48ae7808-02     83
=>