library IEEE ;
use IEEE.STD_LOGIC_1164.ALL;
entity spec_register is
port (
clk , rst : in std_logic ;
A0 , A1 : in std_logic ;
Data : in std_logic_vector (7 downto 0);
Q : out std_logic_vector (7 downto 0)
);
end spec_register ;
architecture beh of spec_register is
signal Qreg : std_logic_vector (7 downto 0);
begin
Q <= Qreg ;
process (clk , rst)
begin
if rst = '0' then
Qreg <= "00000000";
elsif clk ' event and clk = '1' then
if A0 = '0' and A1 = '0' then
Qreg <= Data ;
elsif A0 = '0' and A1 = '1' then
Qreg <= Qreg (7 downto 0) & "00";
elsif A0 = '1' and A1 = '0' then
Qreg <= Qreg (0) & Qreg (4 downto 1);
elsif A0 = '1' and A1 = '1' then
Qreg <= Qreg (7) & "0" & Qreg (6 downto 0);
end if;
end if;
end process ;
end beh ;