module numarator(output reg [3:0]num_out, input clk, input nrst,input en);

always @(posedge clk) begin
if(rst == 0) num_out=0;
else if(en==1)  num_out<=num_out+1;
end

endmodule



module mux(output [7:0]out, input sel, input [7:0]in0, input [7:0]in1);
always @*() begin
if(sel==0) out<=in0;
else out<=in1;
end
endmodule


module alu(output [7:0] result, input [2:0]op, input [7:0]opleft, input [7:0] opright);
always @(*) begin
case(op)
000: result<=opright;
001: result<=opright+opleft;
010: result<=opright^opleft;
011: result<=opright&opleft;
endcase
end
endmodule

module RF(output [7:0] ldata, output [7:0]rdata, input clk, input [3:0]laddr, input [3:0]raddr, input[3:0]destaddr, input we,input [7:0]wdata);
reg [7:0] mem[0:7];
assign ldata=mem[laddr];
assign rdata=mem[raddr];
always @(posedge clk) begin
if(we==1)
mem[destaddr]<=wdata;

end

endmodule