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- // MCU v2.0 firmware bootup code documentation
- // for hardware reg names/documentation, see
- //http://courses.ee.sun.ac.za/Computer_Systems_245/Dokumentasie/RL78%20hardware%20manual%20(registers).pdf
- [Select Register Bank 0]
- SP = 0xFE00 (== 0xFFE00)
- call 1AF:
- di
- CMC = 0x10
- CSC = 0x80
- OSMC = 1
- CKX = 8
- LVIS = 0
- LVIM = 0
- ax = 0
- b = 0xC0
- while (b)
- {
- b -= 2;
- *(0xFFE20+b) = ax // zero_out(0xFFE20, 0xC0); // Clear out stack?
- }
- es = 0
- hl = 0x4F8C
- de = 0xFD32
- branch: 0xD6F.
- --
- ax = hl (4F8C)
- while (ax != 0x4FC2)
- {
- *(de) = a // (0x4F)
- hl++;
- de++;
- ax = hl
- // Set 0xFFD32-0xFFD66 to 0x4F [?]
- }
- hl = 0xF902
- ax = 0xFD32
- branch: d81
- while (ax != hl)
- {
- *(hl) = 0
- hl++;
- //zero_out(0xF902, 0x430);
- }
- hl = 0x4F81
- de = 0xfd68
- branch: d93
- ax = hl;
- while (ax != 0x4F81) { // does undocumented stuff } // This never runs...ax == 0x4F81
- hl = 0xfd68;
- ax = 0xfd68;
- while (ax != hl) { // does undocumented stuff } // Again, weird while loop...nothing!
- call 0xCE:
- hl = sp
- WDTE = 0xAC // Watchdog timer
- push hl
- hl = 0xF0
- cy = hl.7 // cy = 1
- pop hl
- if (cy)
- *(0xff924) |= 1
- a = RESF
- *(hl + 1) = a
- a = *(hl + 1)
- a &= 0x10
- if (a) // Reset occurred due to Watchdog timer
- *(0xFFBDA) |= 2
- *(0xFF924) |= 1
- else
- a = *(hl + 1)
- a &= 0x80
- if (a) // Reset occurred due to illegal instruction
- *(0xFF924) |= 1
- a = *(0xFF924)
- if (!(a & 1))
- ax = 0
- ax--; // ax = 0xFFFF
- *hl = ax
- ax = 0
- while (ax != hl) // Wait loop?
- (*hl)--;
- ax = 0
- call 0x1C5: // reset_registers(), maybe?
- a = *0xFF924
- if (a & 1)
- P0 = 3
- P3 = 7
- P14 = 0
- else
- P0 = 0
- P3 = 6
- P14 = 0
- PM0 = 0xFF
- PM3 = 0xF0
- PM14 = 0xFC
- a = 0xFF924
- if (!(a & 1))
- *0xf0510 = 0
- P1 = 0xC0
- P2 = 0
- P4 = 8
- P5 = 0
- P6 = 0x0
- P7 = 0x40
- P12 = 0x0
- P15 = 0
- *F00F2 &= 0xFE
- ax = 0x00FF
- TT0 = ax
- ax = 0
- IF0 = ax
- IF1 = ax
- IF2 = ax
- MK0 = 0xFFFF
- MK1 = 0xFFFF
- MK2 = 0xFFFF
- *(0xF0511) = 0xFC
- PM1 = 0
- PM2 = 0xE9
- PM4 = 0xF3
- PM5 = 0xF2
- PM6 = 0xFC
- PM7 = 0x4F
- PM12 = 0xFF
- PM15 = 0xFF
- *(0xf0512) = 0x11
- PU0 = 0
- PU1 = 0
- PU3 = 0
- PU4 = 0
- PU5 = 2
- PU7 = 0x19
- PU12 = 0x0
- PU14 = 0x0
- *(0xf0043) = 0 // PIM3? What is this SFR
- *(0xf0047) = 0 // PIM7?
- *(0xF0053) = 6 // POM3?
- *(0xf0057) = 0 // POM6?
- PR00 = 0xFFFF
- PR01 = 0xFFFF
- PR10 = 0xFFFF
- PR11 = 0xFFFE
- PR02L = 0xFF
- PR12L = 0xFF
- EGP0 = 0x31 // External interrupt rising edge enable
- EGN0 = 0x60 // External interrupt falling edge enable
- *(0xf0538) = 0xA
- *(0xf0539) = 0x0
- KRM = 0
- PER0 &= 0xDF // ADCEN = 0, disables clock supply to A/D converter input, disables A/D SFRs
- ADM0 = 0 // Does this do anything? ADCEN just got disabled, so A/D is in reset mode...
- PER0 &= 0xFB // SAU0EN = 0, Disables Serial Array unit 0.
- x = 0x87 // a is 0, so ax == 0x0087
- SRC0 = ax // 0x87
- SRC1 = ax // 0x87
- SRC2 = ax // 0x87
- SRC3 = ax // 0x87
- PER0 &= 0xEF // ICA0EN = 0, disables clock supply to IICA0, disables IICA0 SFRs (I2C)
- // Given the trends, these must be the I2C registers:
- IICCTL00 = 0
- *(0xF0501) &= 0xFE
- *(0xF0550) = 0
- // DMA control register clearing
- DRC0 = 0
- DRC1 = 0
- // Clock output select clearing
- CKS0 = 0
- CKS1 = 0
- *(hl) = 0x0000
- // [NOT FINISHED DOCUMENTING YET]
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