task uputc;
        input [7:0] data;
        begin
            tx_data <= data;
            while (fifo_full)
                @ (posedge sys_clock);
            fifo_wr <= 1;
            @ (posedge sys_clock);
            fifo_wr <= 0;
            @ (posedge sys_clock);
        end
    endtask : uputc

    task ugetc;
        @ (posedge sys_clock);
        while (fifo_empty)
            @ (posedge sys_clock);
        fifo_rd <= 1;
        @ (posedge sys_clock);
        fifo_rd <= 0;
        @ (posedge sys_clock);
    endtask : ugetc