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  1. #ifndef XPARAMETERS_H   /* prevent circular inclusions */
  2. #define XPARAMETERS_H   /* by using protection macros */
  3.  
  4. /* Definition for CPU ID */
  5. #define XPAR_CPU_ID 0
  6.  
  7. /* Definitions for peripheral PS7_CORTEXA9_0 */
  8. #define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 650000000
  9.  
  10.  
  11. /******************************************************************/
  12.  
  13. /* Canonical definitions for peripheral PS7_CORTEXA9_0 */
  14. #define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 650000000
  15.  
  16.  
  17. /******************************************************************/
  18.  
  19. #include "xparameters_ps.h"
  20.  
  21. #define STDIN_BASEADDRESS 0xF8800000
  22. #define STDOUT_BASEADDRESS 0xF8800000
  23.  
  24. /******************************************************************/
  25.  
  26.  
  27. /* Definitions for peripheral PS7_DDR_0 */
  28. #define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
  29. #define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
  30.  
  31.  
  32. /******************************************************************/
  33.  
  34. /* Definitions for driver DEVCFG */
  35. #define XPAR_XDCFG_NUM_INSTANCES 1
  36.  
  37. /* Definitions for peripheral PS7_DEV_CFG_0 */
  38. #define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
  39. #define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
  40. #define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
  41.  
  42.  
  43. /******************************************************************/
  44.  
  45. /* Canonical definitions for peripheral PS7_DEV_CFG_0 */
  46. #define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
  47. #define XPAR_XDCFG_0_BASEADDR 0xF8007000
  48. #define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
  49.  
  50.  
  51. /******************************************************************/
  52.  
  53. /* Definitions for driver DMAPS */
  54. #define XPAR_XDMAPS_NUM_INSTANCES 2
  55.  
  56. /* Definitions for peripheral PS7_DMA_NS */
  57. #define XPAR_PS7_DMA_NS_DEVICE_ID 0
  58. #define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
  59. #define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
  60.  
  61.  
  62. /* Definitions for peripheral PS7_DMA_S */
  63. #define XPAR_PS7_DMA_S_DEVICE_ID 1
  64. #define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
  65. #define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
  66.  
  67.  
  68. /******************************************************************/
  69.  
  70. /* Canonical definitions for peripheral PS7_DMA_NS */
  71. #define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
  72. #define XPAR_XDMAPS_0_BASEADDR 0xF8004000
  73. #define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
  74.  
  75. /* Canonical definitions for peripheral PS7_DMA_S */
  76. #define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
  77. #define XPAR_XDMAPS_1_BASEADDR 0xF8003000
  78. #define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
  79.  
  80.  
  81. /******************************************************************/
  82.  
  83.  
  84. /* Definitions for peripheral PS7_AFI_0 */
  85. #define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
  86. #define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
  87.  
  88.  
  89. /* Definitions for peripheral PS7_AFI_1 */
  90. #define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
  91. #define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
  92.  
  93.  
  94. /* Definitions for peripheral PS7_AFI_2 */
  95. #define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
  96. #define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
  97.  
  98.  
  99. /* Definitions for peripheral PS7_AFI_3 */
  100. #define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
  101. #define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
  102.  
  103.  
  104. /* Definitions for peripheral PS7_DDRC_0 */
  105. #define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
  106. #define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
  107.  
  108.  
  109. /* Definitions for peripheral PS7_GLOBALTIMER_0 */
  110. #define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
  111. #define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
  112.  
  113.  
  114. /* Definitions for peripheral PS7_GPV_0 */
  115. #define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
  116. #define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
  117.  
  118.  
  119. /* Definitions for peripheral PS7_INTC_DIST_0 */
  120. #define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
  121. #define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
  122.  
  123.  
  124. /* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
  125. #define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
  126. #define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
  127.  
  128.  
  129. /* Definitions for peripheral PS7_L2CACHEC_0 */
  130. #define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
  131. #define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
  132.  
  133.  
  134. /* Definitions for peripheral PS7_OCMC_0 */
  135. #define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
  136. #define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
  137.  
  138.  
  139. /* Definitions for peripheral PS7_PL310_0 */
  140. #define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
  141. #define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
  142.  
  143.  
  144. /* Definitions for peripheral PS7_PMU_0 */
  145. #define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
  146. #define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
  147. #define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
  148. #define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
  149.  
  150.  
  151. /* Definitions for peripheral PS7_QSPI_LINEAR_0 */
  152. #define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
  153. #define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
  154.  
  155.  
  156. /* Definitions for peripheral PS7_RAM_0 */
  157. #define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
  158. #define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
  159.  
  160.  
  161. /* Definitions for peripheral PS7_RAM_1 */
  162. #define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
  163. #define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
  164.  
  165.  
  166. /* Definitions for peripheral PS7_SCUC_0 */
  167. #define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
  168. #define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
  169.  
  170.  
  171. /* Definitions for peripheral PS7_SLCR_0 */
  172. #define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
  173. #define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
  174.  
  175.  
  176. /* Definitions for peripheral FLOATPROTOTYPEC_0 */
  177. #define XPAR_FLOATPROTOTYPEC_0_S_AXI_SLV0_BASEADDR 0x43C00000
  178. #define XPAR_FLOATPROTOTYPEC_0_S_AXI_SLV0_HIGHADDR 0x43C0FFFF
  179.  
  180.  
  181. /******************************************************************/
  182.  
  183. /* Definitions for driver GPIO */
  184. #define XPAR_XGPIO_NUM_INSTANCES 3
  185.  
  186. /* Definitions for peripheral BUTTONS */
  187. #define XPAR_BUTTONS_BASEADDR 0x41220000
  188. #define XPAR_BUTTONS_HIGHADDR 0x4122FFFF
  189. #define XPAR_BUTTONS_DEVICE_ID 0
  190. #define XPAR_BUTTONS_INTERRUPT_PRESENT 0
  191. #define XPAR_BUTTONS_IS_DUAL 0
  192.  
  193.  
  194. /* Definitions for peripheral LEDS */
  195. #define XPAR_LEDS_BASEADDR 0x41210000
  196. #define XPAR_LEDS_HIGHADDR 0x4121FFFF
  197. #define XPAR_LEDS_DEVICE_ID 1
  198. #define XPAR_LEDS_INTERRUPT_PRESENT 0
  199. #define XPAR_LEDS_IS_DUAL 0
  200.  
  201.  
  202. /* Definitions for peripheral SWITCHES */
  203. #define XPAR_SWITCHES_BASEADDR 0x41200000
  204. #define XPAR_SWITCHES_HIGHADDR 0x4120FFFF
  205. #define XPAR_SWITCHES_DEVICE_ID 2
  206. #define XPAR_SWITCHES_INTERRUPT_PRESENT 0
  207. #define XPAR_SWITCHES_IS_DUAL 0
  208.  
  209.  
  210. /******************************************************************/
  211.  
  212. /* Canonical definitions for peripheral BUTTONS */
  213. #define XPAR_GPIO_0_BASEADDR 0x41220000
  214. #define XPAR_GPIO_0_HIGHADDR 0x4122FFFF
  215. #define XPAR_GPIO_0_DEVICE_ID XPAR_BUTTONS_DEVICE_ID
  216. #define XPAR_GPIO_0_INTERRUPT_PRESENT 0
  217. #define XPAR_GPIO_0_IS_DUAL 0
  218.  
  219. /* Canonical definitions for peripheral LEDS */
  220. #define XPAR_GPIO_1_BASEADDR 0x41210000
  221. #define XPAR_GPIO_1_HIGHADDR 0x4121FFFF
  222. #define XPAR_GPIO_1_DEVICE_ID XPAR_LEDS_DEVICE_ID
  223. #define XPAR_GPIO_1_INTERRUPT_PRESENT 0
  224. #define XPAR_GPIO_1_IS_DUAL 0
  225.  
  226. /* Canonical definitions for peripheral SWITCHES */
  227. #define XPAR_GPIO_2_BASEADDR 0x41200000
  228. #define XPAR_GPIO_2_HIGHADDR 0x4120FFFF
  229. #define XPAR_GPIO_2_DEVICE_ID XPAR_SWITCHES_DEVICE_ID
  230. #define XPAR_GPIO_2_INTERRUPT_PRESENT 0
  231. #define XPAR_GPIO_2_IS_DUAL 0
  232.  
  233.  
  234. /******************************************************************/
  235.  
  236. /* Definitions for driver QSPIPS */
  237. #define XPAR_XQSPIPS_NUM_INSTANCES 1
  238.  
  239. /* Definitions for peripheral PS7_QSPI_0 */
  240. #define XPAR_PS7_QSPI_0_DEVICE_ID 0
  241. #define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
  242. #define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
  243. #define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
  244. #define XPAR_PS7_QSPI_0_QSPI_MODE 0
  245.  
  246.  
  247. /******************************************************************/
  248.  
  249. /* Canonical definitions for peripheral PS7_QSPI_0 */
  250. #define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
  251. #define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
  252. #define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
  253. #define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
  254. #define XPAR_XQSPIPS_0_QSPI_MODE 0
  255.  
  256.  
  257. /******************************************************************/
  258.  
  259. /* Definitions for driver SCUGIC */
  260. #define XPAR_XSCUGIC_NUM_INSTANCES 1U
  261.  
  262. /* Definitions for peripheral PS7_SCUGIC_0 */
  263. #define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
  264. #define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
  265. #define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
  266. #define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
  267.  
  268.  
  269. /******************************************************************/
  270.  
  271. /* Canonical definitions for peripheral PS7_SCUGIC_0 */
  272. #define XPAR_SCUGIC_0_DEVICE_ID 0U
  273. #define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
  274. #define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
  275. #define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
  276.  
  277.  
  278. /******************************************************************/
  279.  
  280. /* Definitions for driver SCUTIMER */
  281. #define XPAR_XSCUTIMER_NUM_INSTANCES 1
  282.  
  283. /* Definitions for peripheral PS7_SCUTIMER_0 */
  284. #define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
  285. #define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
  286. #define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
  287.  
  288.  
  289. /******************************************************************/
  290.  
  291. /* Canonical definitions for peripheral PS7_SCUTIMER_0 */
  292. #define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
  293. #define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
  294. #define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
  295.  
  296.  
  297. /******************************************************************/
  298.  
  299. /* Definitions for driver SCUWDT */
  300. #define XPAR_XSCUWDT_NUM_INSTANCES 1
  301.  
  302. /* Definitions for peripheral PS7_SCUWDT_0 */
  303. #define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
  304. #define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
  305. #define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
  306.  
  307.  
  308. /******************************************************************/
  309.  
  310. /* Canonical definitions for peripheral PS7_SCUWDT_0 */
  311. #define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
  312. #define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
  313. #define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
  314.  
  315.  
  316. /******************************************************************/
  317.  
  318. /* Definitions for driver UARTPS */
  319. #define XPAR_XUARTPS_NUM_INSTANCES 1
  320.  
  321. /* Definitions for peripheral PS7_UART_1 */
  322. #define XPAR_PS7_UART_1_DEVICE_ID 0
  323. #define XPAR_PS7_UART_1_BASEADDR 0xE0001000
  324. #define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
  325. #define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000
  326. #define XPAR_PS7_UART_1_HAS_MODEM 0
  327.  
  328.  
  329. /******************************************************************/
  330.  
  331. /* Canonical definitions for peripheral PS7_UART_1 */
  332. #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
  333. #define XPAR_XUARTPS_0_BASEADDR 0xE0001000
  334. #define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
  335. #define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
  336. #define XPAR_XUARTPS_0_HAS_MODEM 0
  337.  
  338.  
  339. /******************************************************************/
  340.  
  341. /* Definitions for driver XADCPS */
  342. #define XPAR_XADCPS_NUM_INSTANCES 1
  343.  
  344. /* Definitions for peripheral PS7_XADC_0 */
  345. #define XPAR_PS7_XADC_0_DEVICE_ID 0
  346. #define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
  347. #define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
  348.  
  349.  
  350. /******************************************************************/
  351.  
  352. /* Canonical definitions for peripheral PS7_XADC_0 */
  353. #define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
  354. #define XPAR_XADCPS_0_BASEADDR 0xF8007100
  355. #define XPAR_XADCPS_0_HIGHADDR 0xF8007120
  356.  
  357.  
  358. /******************************************************************/
  359.  
  360. #endif  /* end of protection macro */
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