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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 12:20:15 04/19/2017
- -- Design Name:
- -- Module Name: MUX_8x1 - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity MUX_8x1 is
- Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
- S : in STD_LOGIC_VECTOR (2 downto 0);
- Y : out STD_LOGIC);
- end MUX_8x1;
- architecture Behavioral of MUX_8x1 is
- begin
- process (S,I)
- begin
- case S is
- when "000" => Y <= I(0);
- when "001" => Y <= I(1);
- when "010" => Y <= I(2);
- when "011" => Y <= I(3);
- when "100" => Y <= I(4);
- when "101" => Y <= I(5);
- when "110" => Y <= I(6);
- when "111" => Y <= I(7);
- when others => Y <= '0';
- end case;
- end process;
- end Behavioral;
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