sum1.sv

module sum1(
        input logic a,
        input logic b,
        input logic c,
        input logic d,
        output logic q,
        output logic o
    );

always @(posedge c) begin
    assign q = (a & ~b & ~d) | (~a & b & ~d) | (~a & ~b & d) | (a & b & d);
    o <= (a & b & ~d) | (~a & b & d) | (a & ~b & d) | (a & b & d);
end

endmodule