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Matqux

I2S_transmitter

Feb 27th, 2024
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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 02/25/2024 06:29:54 PM
  7. // Design Name:
  8. // Module Name: I2S_receiver
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21.  
  22. module I2S_receiver
  23. (
  24.     input wire clk,
  25.     input wire rstn,
  26.     input wire en,
  27.     input wire lrclk,
  28.     input wire bclk,
  29.     input wire sdi,
  30.    
  31.     output reg [23:0] adc_data,
  32.     output wire adc_valid_l ,
  33.     output wire adc_valid_r
  34. );
  35.  
  36. // LRCLK edge detection
  37. reg [2:0] lrclk_reg;
  38. wire lrclk_rising;
  39. wire lrclk_falling;
  40. always @ (posedge clk)
  41. begin
  42.     if(rstn == 1'b0)
  43.         lrclk_reg <= 3'b000;
  44.     else
  45.         lrclk_reg <= {lrclk_reg[1:0], lrclk};
  46. end
  47. assign lrclk_rising = (lrclk_reg == 3'b011);
  48. assign lrclk_falling = (lrclk_reg == 3'b100);
  49.  
  50. //BCLK edge detection
  51. reg [2:0] bclk_reg;
  52. wire bclk_rising;
  53. wire bclk_falling;
  54. always @ (posedge clk)
  55. begin
  56.     if(rstn == 1'b0)
  57.         bclk_reg <= 3'b000;
  58.     else
  59.         bclk_reg <= {bclk_reg[1:0], bclk};
  60. end
  61. assign bclk_rising = (bclk_reg == 3'b011);
  62. assign bclk_falling = (bclk_reg == 3'b100);
  63.  
  64. //Shift register handling
  65. always @ (posedge clk)
  66. begin
  67.     if(rstn == 1'b0)
  68.         adc_data <= 24'd0;
  69.     else if (bclk_rising == 1'b1)
  70.         adc_data <= {adc_data[22:0], sdi};
  71. end
  72.  
  73. //L valid signal generation
  74. assign adc_valid_l = lrclk_falling && en;
  75.  
  76. //R valid signal generation
  77. assign adc_valid_r = lrclk_rising && en;
  78.  
  79. endmodule
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