PLL = get_pll(platform)
        self.freq = get_clock_freq(platform)
        self.pll = PLL(self.freq, 48e6)

    def elaborate(self, platform):
        m = Module()

        # Connect the PLL to generate 48MHz for the "sync" domain

        m.submodules += self.pll

        clk_i = platform.request(platform.default_clk).i
        cd = ClockDomain("sync")

        m.domains += cd

        m.d.comb += [
            self.pll.clkin.eq(clk_i),
            ClockSignal("sync").eq(self.pll.clkout[0]),
        ]
        # ....